[PATCH] softmmu: Add missing trace-events file

Commit c7f419f584 moved softmmu-only files out of the root directory, but forgot to move the trace events, which should no longer be generated to "trace-root.h". Fix that by adding softmmu/trace-events. Signed-off-by: Philippe Mathieu-Daudé --- Makefile.objs| 1 + softmmu/balloon.c|

Re: [PATCH v4 04/18] tests/qapi/doc-good.json: Clean up markup

The subject is a bit misleading. The markup doesn't need cleanup. It purposefully tests corner cases of the doc comment parser. For some of them, the conversion to rST will change the meaning. This commit tweaks the test so it passes before and after the conversion. Makes it a worse test for t

Re: device compatibility interface for live migration with assigned devices

Wed, Aug 05, 2020 at 11:33:38AM CEST, yan.y.z...@intel.com wrote: >On Wed, Aug 05, 2020 at 04:02:48PM +0800, Jason Wang wrote: >> >> On 2020/8/5 下午3:56, Jiri Pirko wrote: >> > Wed, Aug 05, 2020 at 04:41:54AM CEST, jasow...@redhat.com wrote: >> > > On 2020/8/5 上午10:16, Yan Zhao wrote: >> > > > On W

Re: device compatibility interface for live migration with assigned devices

Wed, Aug 05, 2020 at 04:41:54AM CEST, jasow...@redhat.com wrote: > >On 2020/8/5 上午10:16, Yan Zhao wrote: >> On Wed, Aug 05, 2020 at 10:22:15AM +0800, Jason Wang wrote: >> > On 2020/8/5 上午12:35, Cornelia Huck wrote: >> > > [sorry about not chiming in earlier] >> > > >> > > On Wed, 29 Jul 2020 16:05

Re: [Bug 1890360] [NEW] Assertion failure in address_space_unmap through virtio-blk

On Tue, Aug 04, 2020 at 10:00:59PM -0400, Alexander Bulekov wrote: > Hi Stefan, > This looks an awful lot like the one you looked at here: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg705719.html > though this one is for virtio-pci, while that one was for virtio-mmio: > > They are proba

Re: [PATCH] softmmu: Add missing trace-events file

Philippe Mathieu-Daudé writes: > Commit c7f419f584 moved softmmu-only files out of the root > directory, but forgot to move the trace events, which should > no longer be generated to "trace-root.h". Fix that by adding > softmmu/trace-events. Dang! I'd like to have this in 5.1 if at all possible

Re: [PATCH for-5.1?] qcow2-cluster: Fix integer left shift error in qcow2_alloc_cluster_link_l2()

On 8/5/20 4:22 AM, Tuguoyi wrote: When calculating the offset, the result of left shift operation will be promoted to type int64 automatically because the left operand of + operator is uint64_t. but the result after integer promotion may be produce an error value for us and trigger the following

Re: [PATCH] qcow2-cluster: Fix integer left shift error in qcow2_alloc_cluster_link_l2()

Am 05.08.2020 um 11:22 hat Tuguoyi geschrieben: > When calculating the offset, the result of left shift operation will be > promoted > to type int64 automatically because the left operand of + operator is > uint64_t. > but the result after integer promotion may be produce an error value for us >

Re: [PATCH v4 04/18] tests/qapi/doc-good.json: Clean up markup

On Wed, 5 Aug 2020 at 14:03, Markus Armbruster wrote: > > The subject is a bit misleading. The markup doesn't need cleanup. It > purposefully tests corner cases of the doc comment parser. For some of > them, the conversion to rST will change the meaning. This commit tweaks > the test so it pas

Re: [PATCH] qcow2-cluster: Fix integer left shift error in qcow2_alloc_cluster_link_l2()

On Wed 05 Aug 2020 11:22:58 AM CEST, Tuguoyi wrote: > This patch fix it by casting @i to uint64_t before doing left shift > operation The patch seems fine and I also think that it's perhaps worth a test case (although it only seems to happen with preallocation=falloc or full so the test would need

Re: [PATCH] qcow2-cluster: Fix integer left shift error in qcow2_alloc_cluster_link_l2()

On Wed 05 Aug 2020 03:44:08 PM CEST, Alberto Garcia wrote: > On Wed 05 Aug 2020 11:22:58 AM CEST, Tuguoyi wrote: >> This patch fix it by casting @i to uint64_t before doing left shift >> operation > > The patch seems fine and I also think that it's perhaps worth a test > case (although it only seem

Re: [PATCH 2/3] block: add logging facility for long standing IO requests

On 8/5/20 12:08 PM, Denis V. Lunev wrote: > There are severe delays with IO requests processing if QEMU is running in > virtual machine or over software defined storage. Such delays potentially > results in unpredictable guest behavior. For example, guests over IDE or > SATA drive could remount fil

Re: [PATCH] softmmu: Add missing trace-events file

On 8/5/20 3:02 PM, Philippe Mathieu-Daudé wrote: > Commit c7f419f584 moved softmmu-only files out of the root > directory, but forgot to move the trace events, which should > no longer be generated to "trace-root.h". Fix that by adding > softmmu/trace-events. > > Signed-off-by: Philippe Mathieu-Da

Re: [PATCH] softmmu: Add missing trace-events file

On 8/5/20 3:27 PM, Markus Armbruster wrote: > Philippe Mathieu-Daudé writes: > >> Commit c7f419f584 moved softmmu-only files out of the root >> directory, but forgot to move the trace events, which should >> no longer be generated to "trace-root.h". Fix that by adding >> softmmu/trace-events. >

Re: [PATCH 2/3] block: add logging facility for long standing IO requests

On 8/5/20 4:51 PM, Philippe Mathieu-Daudé wrote: > On 8/5/20 12:08 PM, Denis V. Lunev wrote: >> There are severe delays with IO requests processing if QEMU is running in >> virtual machine or over software defined storage. Such delays potentially >> results in unpredictable guest behavior. For exam

Re: [PATCH] qcow2-cluster: Fix integer left shift error in qcow2_alloc_cluster_link_l2()

Am 05.08.2020 um 15:44 hat Alberto Garcia geschrieben: > On Wed 05 Aug 2020 11:22:58 AM CEST, Tuguoyi wrote: > > This patch fix it by casting @i to uint64_t before doing left shift > > operation > > The patch seems fine and I also think that it's perhaps worth a test > case (although it only seems

Re: [PATCH v2] qapi/block-core.json: Remove stale description of 'blockdev-add'

On 8/5/20 5:01 AM, Kashyap Chamarthy wrote: On a 'qemu-discuss' thread[1], Kevin identifies that the current doc blurb for @blockdev-add is stale: This is actually a documentation bug. @id doesn't exist, blockdev-add never creates a BlockBackend. This was different in the very fir

Re: [PATCH-for-5.2] memory: Display bigger regions first in 'info mtree' output

Hi Peter, On 7/27/20 8:09 PM, Peter Xu wrote: > On Mon, Jul 27, 2020 at 07:45:43PM +0200, Philippe Mathieu-Daudé wrote: >> When different regions have the same address, we currently >> sort them by the priority. Also sort them by the region >> size. >> >> Signed-off-by: Philippe Mathieu-Daudé >>

[Bug 1890290] Re: PowerPC L2(nested virt) kvm guest fails to boot with ic-mode=dual, kernel-irqchip=on - `KVM is too old to support ic-mode=dual, kernel-irqchip=on`

Hmm... the documentation might need an update. I'll have a look. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1890290 Title: PowerPC L2(nested virt) kvm guest fails to boot with ic-mode=dual ,ke

Re: [PATCH] qcow2-cluster: Fix integer left shift error in qcow2_alloc_cluster_link_l2()

On Wed 05 Aug 2020 04:16:57 PM CEST, Kevin Wolf wrote: >> nb_clusters is an int and there are more cases of >> >> nb_clusters << s->cluster_bits >> >> I can see at least these: handle_alloc(), qcow2_free_any_clusters(), >> qcow2_alloc_cluster_abort(). > > Actuallyx, handle_alloc() and everyth

Re: [PATCH-for-5.2] memory: Display bigger regions first in 'info mtree' output

On 8/5/20 4:21 PM, Philippe Mathieu-Daudé wrote: > Hi Peter, > > On 7/27/20 8:09 PM, Peter Xu wrote: >> On Mon, Jul 27, 2020 at 07:45:43PM +0200, Philippe Mathieu-Daudé wrote: >>> When different regions have the same address, we currently >>> sort them by the priority. Also sort them by the region

[PATCH v1] aspeed: include build AT24X EEPROM devices

Since Yadro, Intel and many other manufactures use ASPEED-based BMCs with attached ATMEL AT24X EEPROM devices, the qemu-device AT24C must be added to ASPEED_SOC dependencies. Signed-off-by: Igor Kononenko Change-Id: Ibf4fb7a3057bd43998c94d44609f402d3f088863 --- hw/arm/Kconfig | 1 + 1 file chang

[Bug 1879587] Re: Register number in ESR is incorrect for certain banked registers when switching from AA32 to AA64

It seems like this is your patch plus my fixup so this is good to me and already tested locally. Thanks again. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1879587 Title: Register number in ESR is

vhost-user protocol feature negotiation

Quoting from the definition of VHOST_USER_SET_PROTOCOL_FEATURES in vhost-user.rst: > Only legal if feature bit ``VHOST_USER_F_PROTOCOL_FEATURES`` is present in > ``VHOST_USER_GET_FEATURES``. > > .. Note:: >Slave that reported ``VHOST_USER_F_PROTOCOL_FEATURES`` must support >this messa

Re: [PATCH] qcow2-cluster: Fix integer left shift error in qcow2_alloc_cluster_link_l2()

On Wed, 5 Aug 2020 at 10:24, Tuguoyi wrote: > > When calculating the offset, the result of left shift operation will be > promoted > to type int64 automatically because the left operand of + operator is > uint64_t. > but the result after integer promotion may be produce an error value for us >

[Bug 1879587] Re: Register number in ESR is incorrect for certain banked registers when switching from AA32 to AA64

Hey Julien, what fixup do you need on top of Peter's v2? -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1879587 Title: Register number in ESR is incorrect for certain banked registers when switchi

Re: [PATCH v2 for-5.1?] target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64

On 8/4/20 12:39 PM, Peter Maydell wrote: > When a coprocessor instruction in an AArch32 guest traps to AArch32 > Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields > which are simply copies of the Rt and Rt2 fields from the trapped > instruction. However, if the instruction is trapp

[Bug 1879587] Re: Register number in ESR is incorrect for certain banked registers when switching from AA32 to AA64

Peter's v2 already includes the fixup (update #6) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1879587 Title: Register number in ESR is incorrect for certain banked registers when switching from

[PATCH] spapr: Clarify error and documentation for broken KVM XICS

When starting an L2 KVM guest with `ic-mode=dual,kernel-irqchip=on`, QEMU fails with: KVM is too old to support ic-mode=dual,kernel-irqchip=on This error message was introduced to detect older KVM versions that didn't allow destruction and re-creation of the XICS KVM device that we do at reboot.

Re: qemu-img convert asserts while converting from vhdx to raw

Hi Max, Thanks for the response. I checked internally and looks like it always fails. Also in the code I see comment saying "We only support 512 currently" at block/vhdx.c: vhdx_parse_metadata() As you suggested we can just refuse to open images with 4K logical sector size, I will send an patch

Re: [PATCH v12 07/11] qcow2_format.py: Dump bitmap table serialized entries

30.07.2020 17:15, Andrey Shinkevich wrote: Add bitmap table information to the QCOW2 metadata dump. Bitmap name bitmap-1 ... Bitmap table typesize offset 0 serialized 6553610092544 1 all-zeroes 655360 For s

[Bug 1890290] Re: PowerPC L2(nested virt) kvm guest fails to boot with ic-mode=dual, kernel-irqchip=on - `KVM is too old to support ic-mode=dual, kernel-irqchip=on`

Posted a patch to the list. http://patchwork.ozlabs.org/project/qemu- devel/patch/159664243614.622889.18307368735989783528.st...@bahia.lan/ Satheesh, Can you please review and test ? ** Changed in: qemu Status: New => In Progress ** Changed in: qemu Assignee: (unassigned) => Greg

Re: cleanups with long-term benefits (was Re: [PATCH] schemas: Add vim modeline)

On 8/5/20 3:36 AM, Markus Armbruster wrote: John Snow writes: On 8/4/20 4:03 AM, Markus Armbruster wrote: The pain of tweaking the parser is likely dwarved several times over by the pain of the flag day. You mention this often; I wonder if I misunderstand the critique, because the pain of a

Re: [PATCH-for-5.1 v3 1/2] exec: Restrict icount to softmmu

On 8/5/20 3:01 AM, Philippe Mathieu-Daudé wrote: > 'icount' feature is only meaningful when using softmmu. > Move it out of the globally used exec.c, and define it as > 'false' in user-mode emulation. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/sysemu/cpus.h | 4 > exec.c

Re: [PATCH v12 08/11] qcow2.py: Introduce '-j' key to dump in JSON format

30.07.2020 17:15, Andrey Shinkevich wrote: Add the command key to the qcow2.py arguments list to dump QCOW2 metadata in JSON format. Here is the suggested way to do that. The implementation of the dump in JSON format is in the patch that follows. Signed-off-by: Andrey Shinkevich Reviewed-by: V

Re: v8.1M cpu emulation and target-arm feature-identification strategy

On 8/5/20 4:08 AM, Peter Maydell wrote: > Mostly recently we've been aiming for QEMU emulation code in > target/arm to use ID register fields to determine whether a > feature is present or not (the isar_feature_* functions) rather > than the old style of defining ARM_FEATURE_* flags. This seems to

Re: cleanups with long-term benefits

Am 05.08.2020 um 12:08 hat Daniel P. Berrangé geschrieben: > On Wed, Aug 05, 2020 at 11:11:55AM +0200, Cornelia Huck wrote: > > On Wed, 5 Aug 2020 10:05:40 +0100 > > Daniel P. Berrangé wrote: > > > > > On Wed, Aug 05, 2020 at 10:49:35AM +0200, Paolo Bonzini wrote: > > > > On 05/08/20 10:39, Dr.

Re: [PATCH v2 2/3] async: always set ctx->notified in aio_notify()

On 05/08/20 12:00, Stefan Hajnoczi wrote: > aio_notify() does not set ctx->notified when called with > ctx->aio_notify_me disabled. Therefore aio_notify_me needs to be enabled > during polling. > > This is suboptimal since expensive event_notifier_set(&ctx->notifier) > and event_notifier_test_and_

Re: [PATCH] spapr: Clarify error and documentation for broken KVM XICS

On 8/5/20 5:47 PM, Greg Kurz wrote: > When starting an L2 KVM guest with `ic-mode=dual,kernel-irqchip=on`, > QEMU fails with: > > KVM is too old to support ic-mode=dual,kernel-irqchip=on > > This error message was introduced to detect older KVM versions that > didn't allow destruction and re-crea

Re: [PATCH v2 for-5.1?] target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64

On Wed, 5 Aug 2020 at 16:26, Richard Henderson wrote: > > On 8/4/20 12:39 PM, Peter Maydell wrote: > > When a coprocessor instruction in an AArch32 guest traps to AArch32 > > Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields > > which are simply copies of the Rt and Rt2 fields from

Re: [PATCH v2 3/3] aio-posix: keep aio_notify_me disabled during polling

On 05/08/20 12:00, Stefan Hajnoczi wrote: > + > +/* > + * aio_notify can avoid the expensive event_notifier_set if > + * everything (file descriptors, bottom halves, timers) will > + * be re-evaluated before the next blocking poll(). This is > + * already tr

Re: v8.1M cpu emulation and target-arm feature-identification strategy

Richard Henderson writes: > On 8/5/20 4:08 AM, Peter Maydell wrote: >> Mostly recently we've been aiming for QEMU emulation code in >> target/arm to use ID register fields to determine whether a >> feature is present or not (the isar_feature_* functions) rather >> than the old style of defining

Re: cleanups with long-term benefits

On Wed, Aug 05, 2020 at 06:23:23PM +0200, Kevin Wolf wrote: > Am 05.08.2020 um 12:08 hat Daniel P. Berrangé geschrieben: > > On Wed, Aug 05, 2020 at 11:11:55AM +0200, Cornelia Huck wrote: > > > On Wed, 5 Aug 2020 10:05:40 +0100 > > > Daniel P. Berrangé wrote: > > > > > > > On Wed, Aug 05, 2020

Re: [PATCH-for-5.0 1/2] hw/acpi/piix4: Add 'system-hotplug-support' property

On Wed, 5 Aug 2020 08:01:24 +0200 Philippe Mathieu-Daudé wrote: > On 8/5/20 7:56 AM, Philippe Mathieu-Daudé wrote: > > On 3/19/20 11:02 AM, Paolo Bonzini wrote: > >> On 19/03/20 10:42, Philippe Mathieu-Daudé wrote: > >>> On 3/19/20 10:36 AM, Paolo Bonzini wrote: > On 18/03/20 23:15, Ph

Re: [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions

On 8/3/20 7:40 PM, Frank Chang wrote: > This isn't what spike does. > > The manual could really stand to be more specific here... > > Isn't Spike's vsaddu.vi immediate value also > signed-extended?  > /riscv/insns/vsaddu_vi.h:/ > /vd = vs2 + (insn.v_simm5() & (UINT64_M

[Bug 1879587] Re: Register number in ESR is incorrect for certain banked registers when switching from AA32 to AA64

** Changed in: qemu Status: In Progress => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1879587 Title: Register number in ESR is incorrect for certain banked registers when

Re: v8.1M cpu emulation and target-arm feature-identification strategy

On Wed, 5 Aug 2020 at 17:45, Alex Bennée wrote: > I wouldn't test other feature bits but what stopping us adding: > > struct ARMISARegisters { > uint32_t id_isar0; > ... > uint64_t id_aa64dfr1; > /* > * The following are synthetic flags for features not

Re: [PATCH v12 09/11] qcow2_format.py: collect fields to dump in JSON format

30.07.2020 17:15, Andrey Shinkevich wrote: As __dict__ is being extended with class members we do not want to print, add the to_dict() method to classes that returns a dictionary with desired fields and their values. Extend it in subclass when necessary to print the final dictionary in the JSON o

Re: v8.1M cpu emulation and target-arm feature-identification strategy

On 8/5/20 9:52 AM, Peter Maydell wrote: > On Wed, 5 Aug 2020 at 17:45, Alex Bennée wrote: >> I wouldn't test other feature bits but what stopping us adding: >> >> struct ARMISARegisters { >> uint32_t id_isar0; >> ... >> uint64_t id_aa64dfr1; >> /* >> *

Re: [PATCH v3 0/8] Generalize start-powered-off property from ARM

Thiago Jung Bauermann writes: > Philippe Mathieu-Daudé writes: > >> Le jeu. 30 juil. 2020 03:00, David Gibson a >> écrit : >> >>> On Tue, Jul 28, 2020 at 09:56:36PM -0300, Thiago Jung Bauermann wrote: >>> > >>> > Thiago Jung Bauermann writes: >>> > >>> > > The ARM code has a start-powered-of

Re: [RFC v3 0/8] QEMU cpus.c refactoring part2

On 8/3/20 1:48 PM, Alex Bennée wrote: > > Claudio Fontana writes: > >> Motivation and higher level steps: >> >> https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg04628.html >> >> The biggest open item for me is, does it makes sense to: >> >> >> 1) make icount TCG-only (building the icount

Re: [PATCH v12 10/11] qcow2_format.py: support dumping metadata in JSON format

30.07.2020 17:15, Andrey Shinkevich wrote: Implementation of dumping QCOW2 image metadata. The sample output: { "Header_extensions": [ { "name": "Feature table", "magic": 1745090647, "length": 192, "data_str": "" },

Re: [PATCH v12 11/11] iotests: dump QCOW2 header in JSON in #303

30.07.2020 17:15, Andrey Shinkevich wrote: Extend the test case #303 by dumping QCOW2 image metadata in JSON format. Signed-off-by: Andrey Shinkevich Reviewed-by: Vladimir Sementsov-Ogievskiy -- Best regards, Vladimir

[PATCH for-5.2 1/5] spapr/xive: Fix xive->fd if kvm_create_device() fails

If the creation of the KVM XIVE device fails for some reasons, the negative errno ends up in xive->fd, but the rest of the code assumes that xive->fd either contains an open fd, ie. positive value, or -1. This doesn't cause any misbehavior except kvmppc_xive_disconnect() that will try to close(xiv

[PATCH for-5.2 0/5] spapr: Cleanups for XIVE and PHB

Recent cleanup patch "spapr: Simplify error handling in spapr_phb_realize" had to be dropped from ppc-for-5.2 because it would cause QEMU to crash at init time on some POWER9 setups (eg. Boston systems), as reported by Daniel. The crash was happening because the kvmppc_xive_source_reset_one() func

[PATCH for-5.2 2/5] spapr/xive: Simplify kvmppc_xive_disconnect()

Since this function begins with: /* The KVM XIVE device is not in use */ if (!xive || xive->fd == -1) { return; } we obviously don't need to check xive->fd again. Signed-off-by: Greg Kurz --- hw/intc/spapr_xive_kvm.c |6 ++ 1 file changed, 2 insertions(+), 4 deletio

[PATCH for-5.2 4/5] spapr/xive: Convert KVM device fd checks to assert()

All callers guard these functions with kvmppc_xive_in_kernel() or one of its variants. Make it clear that these functions are only to be called when the KVM XIVE device is active. Note that the check on xive is dropped in kvmppc_xive_disconnect(). It really cannot be NULL since it comes from set_a

[PATCH for-5.2 3/5] ppc/xive: Introduce dedicated kvm_irqchip_in_kernel() wrappers

Calls to the KVM XIVE device are guarded by kvm_irqchip_in_kernel(). This ensures that QEMU won't try to use the device if KVM is disabled or if an in-kernel irqchip isn't required. When using ic-mode=dual with the pseries machine, we have two possible interrupt controllers: XIVE and XICS. The kvm

[PATCH for-5.2 5/5] spapr: Simplify error handling in spapr_phb_realize()

The spapr_phb_realize() function has a local_err variable which is used to: 1) check failures of spapr_irq_findone() and spapr_irq_claim() 2) prepend extra information to the error message Recent work from Markus Armbruster highlighted we get better code when testing the return value of a functi

Re: [PATCH for-5.2 0/5] spapr: Cleanups for XIVE and PHB

Patchew URL: https://patchew.org/QEMU/159664891296.638781.18417631893299150932.st...@bahia.lan/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SC

RE: [PATCH v2 4/4] net/colo: Match is-enabled probe to tracepoint

> -Original Message- > From: Stefan Hajnoczi > Sent: Wednesday, August 5, 2020 6:53 PM > To: Zhang, Chen > Cc: Roman Bolshakov ; Li Zhijian > ; Jason Wang ; qemu- > de...@nongnu.org; Cameron Esfahani ; Philippe > Mathieu-Daudé ; Daniel Berrange > > Subject: Re: [PATCH v2 4/4] net/colo

[PATCH v1 04/21] target/avr: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 02/21] target/alpha: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 01/21] accel/tcg: Change interrupt/exception handling to remove implied BQL

This change removes the implied BQL from the cpu_handle_interrupt, and cpu_handle_exception paths. This BQL acquire is being pushed down into the per arch implementation. Signed-off-by: Robert Foley --- accel/tcg/cpu-exec.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(

[PATCH v1 00/21] accel/tcg: remove implied BQL from cpu_handle_interrupt/exception path

The purpose of this change is to set the groundwork so that an arch could move towards removing the BQL from the cpu_handle_interrupt/exception paths. The BQL is a bottleneck in scaling to more cores. And this cpu_handle_interrupt/exception path is one of the key BQL users as measured by the QEMU

[PATCH v1 03/21] target/arm: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 10/21] target/microblaze: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 06/21] target/hppa: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 12/21] target/nios2: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 11/21] target/mips: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 05/21] target/cris: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 15/21] target/riscv: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 09/21] target/m68k: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 13/21] target/openrisc: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 07/21] target/i386: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 19/21] target/sparc: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 18/21] target/sh4: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 20/21] target/unicore32: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 14/21] target/ppc: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 08/21] target/lm32: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 17/21] target/s390x: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 16/21] target/rx: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH v1 21/21] target/xtensa: add BQL to do_interrupt and cpu_exec_interrupt

This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec

[PATCH 2/2] travis.yml: Drop the Python 3.5 and 3.6 builds

Python 3.5 is already the default in Ubuntu Xenial (which we use for most jobs on Travis), and Python 3.6 is the default on Ubuntu Bionic (which we use for the s390x jobs on Travis for example already), so explicitely defining tests for Python 3.5 and 3.6 seems redundant. Signed-off-by: Thomas Hut

[RFC PATCH] travis.yml: Drop the default softmmu builds

The total runtime of all Travis jobs is very long and we are testing all softmmu targets in the gitlab-CI already - so we can speed up the Travis testing a little bit by not testing the softmmu targets here anymore. Signed-off-by: Thomas Huth --- Well, ok, we do not test all the softmmu targets

Re: v8.1M cpu emulation and target-arm feature-identification strategy

On Wed, 5 Aug 2020 at 18:00, Richard Henderson wrote: > I've always assumed we'd never get rid of all of them. > > Older ones like XSCALE are obvious, but I don't think there's a clear > indicator > for V{5,6,7,8} either. MIDR.Architecture lets you distinguish v4/v4T/v5/v5T/v5TE/v5TEJ/v6, and th

Re: [PATCH v3 0/8] Generalize start-powered-off property from ARM

On Wed, 5 Aug 2020 at 18:01, Thiago Jung Bauermann wrote: > Any news on this? Is there something I should be doing? I saw -rc3 today > but not these patches. Sorry, you've missed the bus for 5.1 at this point. I'd assumed that the relevant bits of the patchset would go into a PPC pullreq if it wa

Re: v8.1M cpu emulation and target-arm feature-identification strategy

On Wed, 5 Aug 2020 at 18:00, Richard Henderson wrote: > Older ones like XSCALE are obvious Looking at the XScale manual we could actually implement ARM_FEATURE_XSCALE as (cpu->midr & 0x == 0x6905) [Vendor=intel, arch=ARMv5TE], and ARM_FEATURE_IWMMXT as (cpu->midr & 0xe000 == 0x690

Re: [PATCH v1 02/21] target/alpha: add BQL to do_interrupt and cpu_exec_interrupt

On 8/5/20 11:12 AM, Robert Foley wrote: > @@ -299,8 +299,12 @@ void alpha_cpu_do_interrupt(CPUState *cs) > { > AlphaCPU *cpu = ALPHA_CPU(cs); > CPUAlphaState *env = &cpu->env; > -int i = cs->exception_index; > - > +int i; > +bool bql = !qemu_mutex_iothread_locked(); > +if

Re: [PATCH v1 01/21] accel/tcg: Change interrupt/exception handling to remove implied BQL

On 8/5/20 11:12 AM, Robert Foley wrote: > This change removes the implied BQL from the cpu_handle_interrupt, > and cpu_handle_exception paths. This BQL acquire is being pushed > down into the per arch implementation. > > Signed-off-by: Robert Foley > --- > accel/tcg/cpu-exec.c | 19 +++--

[PATCH] ide: Get rid of IDEDrive struct

The struct had a single field (IDEDevice dev), and is only used in the QOM type declarations and property lists. We can simply use the IDEDevice struct directly instead. Signed-off-by: Eduardo Habkost --- hw/ide/qdev.c | 25 + 1 file changed, 9 insertions(+), 16 deletion

Re: [PATCH v1 02/21] target/alpha: add BQL to do_interrupt and cpu_exec_interrupt

On Wed, 5 Aug 2020 at 15:18, Richard Henderson wrote: > > On 8/5/20 11:12 AM, Robert Foley wrote: > > @@ -299,8 +299,12 @@ void alpha_cpu_do_interrupt(CPUState *cs) > > { > > AlphaCPU *cpu = ALPHA_CPU(cs); > > CPUAlphaState *env = &cpu->env; > > -int i = cs->exception_index; > > - >

Re: [PATCH v3 0/8] Generalize start-powered-off property from ARM

Peter Maydell writes: > On Wed, 5 Aug 2020 at 18:01, Thiago Jung Bauermann > wrote: >> Any news on this? Is there something I should be doing? I saw -rc3 today >> but not these patches. > > Sorry, you've missed the bus for 5.1 at this point. I'd assumed > that the relevant bits of the patchset

[Bug 1890370] Re: Segfault in artist vram_bit_write

** Changed in: qemu Assignee: (unassigned) => Helge Deller (hdeller) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1890370 Title: Segfault in artist vram_bit_write Status in QEMU: Invalid

Re: [PATCH] ide: Get rid of IDEDrive struct

On Wed, 5 Aug 2020 at 20:49, Eduardo Habkost wrote: > > The struct had a single field (IDEDevice dev), and is only used > in the QOM type declarations and property lists. We can simply > use the IDEDevice struct directly instead. > > Signed-off-by: Eduardo Habkost > @@ -327,7 +323,6 @@ static vo

Re: [PATCH v3 7/8] hw/display/artist: Refactor artist_rop8() to avoid buffer over-run

Hello Alexander, * Alexander Bulekov : > On 200804 2320, Helge Deller wrote: > > * Alexander Bulekov : > > > I applied this series and it fixes most of the problems I saw before. > > > I still see a few crashes - I made issues for them on launchpad: > > > https://bugs.launchpad.net/qemu/+bug/18903

[ANNOUNCE] QEMU 5.1.0-rc3 is now available

Hello, On behalf of the QEMU Team, I'd like to announce the availability of the fourth release candidate for the QEMU 5.1 release. This release is meant for testing purposes and should not be used in a production environment. http://download.qemu-project.org/qemu-5.1.0-rc3.tar.xz http://down

[PATCH] target/arm: Delete unused ARM_FEATURE_CRC

In commit 962fcbf2efe57231a9f5df we converted the uses of the ARM_FEATURE_CRC bit to use the aa32_crc32 isar_feature test instead. However we forgot to remove the now-unused definition of the feature name in the enum. Delete it now. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 - 1 file

Re: [PATCH] target/arm: Delete unused ARM_FEATURE_CRC

On 8/5/20 2:08 PM, Peter Maydell wrote: > In commit 962fcbf2efe57231a9f5df we converted the uses of the > ARM_FEATURE_CRC bit to use the aa32_crc32 isar_feature test > instead. However we forgot to remove the now-unused definition > of the feature name in the enum. Delete it now. > > Signed-off-by

[PATCH] block/vhdx: Support vhdx image only with 512 bytes logical sector size

block/vhdx uses qemu block layer where sector size is always 512 byte. This may have issues with 4K logical sector sized vhdx image. For e.g qemu-img convert on such images fails with following assert: $qemu-img convert -f vhdx -O raw 4KTest1.vhdx test.raw qemu-img: util/iov.c:388: qiov_slice: A

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