Re: [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU

On Tue, Jun 23, 2020 at 2:08 AM Markus Armbruster wrote: > > Bin Meng writes: > > > Hi Alistair, > > > > On Sat, Jun 20, 2020 at 1:09 AM Alistair Francis > > wrote: > >> > >> From: Bin Meng > >> > >> There is no need to have two functions that have exactly the same > >> codes for 32-bit and 64-

[PATCH v11 49/61] target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 35 ++ target/riscv/vector_helper.c| 40

[PATCH v11 50/61] target/riscv: vector mask population count vmpopc

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 20 4 f

[PATCH v6 0/4] Introduce Xilinx ZynqMP CAN controller

Changelog: v5 -> v6: Add ptimer based counter for time stamping on RX messages. Fix reset issues. Rebase the patches with master latest changes. Added reference clock property for CAN ptimer. v4 -> v5: Add XlnxZynqMPCAN controller id to debug messages. Drop parameter errp

[PATCH v11 51/61] target/riscv: vmfirst find-first-set mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 19 +++ 4 fi

[PATCH v11 52/61] target/riscv: set-X-first mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 28 +++ target/riscv/vector_helper.c| 63 + 4 files

[PATCH v11 53/61] target/riscv: vector iota instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 27 +++ target/riscv/vector_helper.c| 29

[PATCH v11 54/61] target/riscv: vector element index instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 25 + target/riscv/vector_helper.c| 24 +

[PATCH v11 55/61] target/riscv: integer extract instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 116 2 files changed, 117 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6f2

[PATCH v11 56/61] target/riscv: integer scalar move instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 60 + target/riscv/internals.h| 6 +++ 3 files changed, 67 insertions(+) diff --git a/target/riscv/insn

[PATCH v11 57/61] target/riscv: floating-point scalar move instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 49 + 2 files changed, 52 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e06c

[PATCH v11 58/61] target/riscv: vector slide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 target/riscv/vector_helper.c| 114 4 files c

[PATCH v11 59/61] target/riscv: vector register gather instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvv.inc.c | 78 + target/riscv/vector_helper.c| 60 +++

[PATCH v11 60/61] target/riscv: vector compress instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 26 +++

Re: [PATCH v6 0/4] Introduce Xilinx ZynqMP CAN controller

Patchew URL: https://patchew.org/QEMU/1592954616-65393-1-git-send-email-fnu.vik...@xilinx.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SC

[PATCH v11 61/61] target/riscv: configure and turn on vector extension from command line

Vector extension is default off. The only way to use vector extension is 1. use cpu rv32 or rv64 2. turn on it by command line "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size in bits, default val

Re: [PATCH v11 00/61] target/riscv: support vector extension v0.7.1

Patchew URL: https://patchew.org/QEMU/20200623215920.2594-1-zhiwei_...@c-sky.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v11 00/61] target/riscv: support vector extension v0.7.1 Type: series Message-id: 20200623215920.2

Re: [PATCH qemu v9] spapr: Implement Open Firmware client interface

Ping? On 02/06/2020 21:40, Alexey Kardashevskiy wrote: > Ping? > > On 13/05/2020 13:58, Alexey Kardashevskiy wrote: >> The PAPR platform which describes an OS environment that's presented by >> a combination of a hypervisor and firmware. The features it specifies >> require collaboration between

Re: [PATCH] target/ppc: Remove TIDR from POWER10 processor

On Tue, Jun 23, 2020 at 05:45:34PM +0200, Cédric Le Goater wrote: > It is not part of Power ISA Version 3.1. Applied to ppc-for-5.1, thanks. > > Signed-off-by: Cédric Le Goater > --- > target/ppc/translate_init.inc.c | 5 - > 1 file changed, 5 deletions(-) > > diff --git a/target/ppc/tran

Re: [PATCH for-5.1 V5 2/4] hw/intc: Add Loongson liointc support

在 2020/6/23 22:50, Aleksandar Markovic 写道: уто, 23. јун 2020. у 14:13 Huacai Chen > је написао/ла: Loongson-3 has an integrated liointc (Local I/O interrupt controller). It is similar to goldfish interrupt controller, but more powerful (e.g., Any p

[PATCH V2 0/2] net/colo-compare.c: Expose "max_queue_size" to users and clean up

From: Zhang Chen This series make a way to config COLO "max_queue_size" parameters according to user's scenarios and environments and do some clean up for descriptions. V2: - Rebase on upstream code. Zhang Chen (2): net/colo-compare.c: Expose compare "max_queue_size" to users qemu-options.

[PATCH V2 1/2] net/colo-compare.c: Expose compare "max_queue_size" to users

From: Zhang Chen This patch allow users to set the "max_queue_size" according to their environment. Signed-off-by: Zhang Chen --- net/colo-compare.c | 43 ++- qemu-options.hx| 5 +++-- 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/

[PATCH V2 2/2] qemu-options.hx: Clean up and fix typo for colo-compare

From: Zhang Chen Fix some typo and optimized some descriptions. Signed-off-by: Zhang Chen --- qemu-options.hx | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 3ee19a4b0d..aa7ffb34db 100644 --- a/qemu-

Re: how to build QEMU with the peripheral device modules

Hi ,   Thanks for the hints. I get better understanding to the kconfig tool now.   I added "select  TI_DMA" in my DSP kconfig file. It is done. best regards, xiaolei -- Original -- From: "Philippe Mathieu-Daudé"

Re: [PATCH] timer: Handle decrements of PIT counter

On Sat, Jun 13, 2020 at 02:19:12PM +0300, Roman Bolshakov wrote: > There's a fallback to PIT if TSC is not present but it doesn't work > properly. It prevents boot from floppy on isapc and 486 cpu [1][2]. > > SeaBIOS configures PIT in Mode 2. PIT counter is decremented in the mode > but timer_adju

RE: [PATCH 0/2] net/colo-compare.c: Expose "max_queue_size" to users and clean up

> -Original Message- > From: Jason Wang > Sent: Tuesday, June 23, 2020 1:54 PM > To: Zhang, Chen ; Lukas Straub > > Cc: qemu-dev ; Zhang Chen > > Subject: Re: [PATCH 0/2] net/colo-compare.c: Expose "max_queue_size" to > users and clean up > > > On 2020/6/23 上午9:47, Zhang, Chen wrote:

Re: sysbus failed assert for xen_sysdev

On Tue, Jun 23, 2020 at 7:46 AM Paul Durrant wrote: > > > -Original Message- > > From: Markus Armbruster > > Sent: 23 June 2020 09:41 > > To: Jason Andryuk > > Cc: Mark Cave-Ayland ; Anthony PERARD > > ; xen- > > devel ; Paul Durrant ; QEMU > > > > Subject: Re: sysbus failed assert fo

Re: sysbus failed assert for xen_sysdev

On Tue, Jun 23, 2020 at 9:22 AM Paul Durrant wrote: > > > -Original Message- > > From: Jason Andryuk > > Sent: 23 June 2020 13:57 > > To: Markus Armbruster > > Cc: Mark Cave-Ayland ; Anthony PERARD > > ; xen- > > devel ; Paul Durrant ; QEMU > > > > Subject: Re: sysbus failed assert fo

Re: [PATCH v9 1/5] Allow vu_message_read to be replaced

On Thu, Jun 18, 2020 at 12:43:47PM +0200, Kevin Wolf wrote: Am 14.06.2020 um 20:39 hat Coiby Xu geschrieben: Allow vu_message_read to be replaced by one which will make use of the QIOChannel functions. Thus reading vhost-user message won't stall the guest. Signed-off-by: Coiby Xu _vu_queue_n

-enablefips

I never knew what this option did, but the answer is ... strange! It's only defined for linux, in os-posix.c. When called, it calls fips_set_state(true), located in osdep.c. This will read /proc/sys/crypto/fips_enabled and set the static global 'fips_enabled' to true if this setting is on. (Tang

Re: [PATCH v9 0/5] vhost-user block device backend implementation

On Thu, Jun 18, 2020 at 09:27:48AM +0100, Stefan Hajnoczi wrote: On Tue, Jun 16, 2020 at 02:52:16PM +0800, Coiby Xu wrote: On Sun, Jun 14, 2020 at 12:16:28PM -0700, no-re...@patchew.org wrote: > Patchew URL: https://patchew.org/QEMU/20200614183907.514282-1-coiby...@gmail.com/ > > > > Hi, > > Th

Re: [PATCH v9 5/5] new qTest case to test the vhost-user-blk-server

On Thu, Jun 18, 2020 at 04:17:51PM +0100, Stefan Hajnoczi wrote: On Mon, Jun 15, 2020 at 02:39:07AM +0800, Coiby Xu wrote: This test case has the same tests as tests/virtio-blk-test.c except for tests have block_resize. Since vhost-user server can only server one client one time, two instances o

Re: [PATCH v9 0/5] vhost-user block device backend implementation

On Fri, Jun 19, 2020 at 01:07:46PM +0100, Stefan Hajnoczi wrote: On Mon, Jun 15, 2020 at 02:39:02AM +0800, Coiby Xu wrote: v9 - move logical block size check function to a utility function - fix issues regarding license, coding style, memory deallocation, etc. I have replied with patches tha

Re: [PATCH] Revert "tests/migration: Reduce autoconverge initial bandwidth"

On 23/06/2020 19.35, Philippe Mathieu-Daudé wrote: > On 6/23/20 7:07 PM, Thomas Huth wrote: >> On 23/06/2020 17.39, Philippe Mathieu-Daudé wrote: >>> On 6/23/20 4:56 PM, Michael S. Tsirkin wrote: This reverts commit 6d1da867e65f ("tests/migration: Reduce autoconverge initial bandwidth")

[Bug 1884507] Re: 'none' machine should use 'none' display option

Actually, thinking about this twice, I think you made a wrong assumption here. "-display" is about the GUI backend that should be used. "-M" is about the emulated hardware. The emulated hardware options should never influence the host backend options. And it is e.g. perfectly valid to use the "non

[PATCH] scripts/simplebench: compare write request performance

The script 'bench_write_req.py' allows comparing performances of write request for two qemu-img binary files. Suggested-by: Denis V. Lunev Suggested-by: Vladimir Sementsov-Ogievskiy Signed-off-by: Andrey Shinkevich --- scripts/simplebench/bench_write_req.py | 150 ++

Re: [PATCH] libqos: pci-pc: use 32-bit write for EJ register

On 23/06/20 22:55, Michael S. Tsirkin wrote: > On Tue, Jun 23, 2020 at 12:18:51PM -0400, Paolo Bonzini wrote: >> The memory region ops have min_access_size == 4 so obey it. >> >> Signed-off-by: Paolo Bonzini > > Reviewed-by: Michael S. Tsirkin > > I assume you are queueing this with the memory

Re: [PATCH] libqos: usb-hcd-ehci: use 32-bit write for config register

On 23/06/20 22:56, Michael S. Tsirkin wrote: > On Tue, Jun 23, 2020 at 12:18:52PM -0400, Paolo Bonzini wrote: >> The memory region ops have min_access_size == 4 so obey it. >> >> Signed-off-by: Paolo Bonzini > > Makes sense. > > Acked-by: Michael S. Tsirkin > > I assume you are queueing this w

Re: [PATCH for-5.1 V5 0/4] mips: Add Loongson-3 machine support (with KVM)

Hi, Aleksandar, On Tue, Jun 23, 2020 at 9:58 PM Aleksandar Markovic wrote: > > > > уторак, 23. јун 2020., је написао/ла: >> >> Patchew URL: >> https://patchew.org/QEMU/1592914438-30317-1-git-send-email-che...@lemote.com/ >> >> >> >> Hi, >> >> This series seems to have some coding style problems

Building plugin failed on Windows with mingw

Hi all,   I want to build QEMU 4.2.0 with the plugin module on Windows 7 with Mingw, but the building process faild.    The step I follow is listed below: 1. create "dsp_build" diretory under source file folder  2.  change directory to dsp_build , and run ../configure --target-list=dsp-softmmu

Re: [PATCH for-5.1 V5 4/4] MAINTAINERS: Add Loongson-3 maintainer and reviewer

Hi, Aleksandar, On Tue, Jun 23, 2020 at 9:50 PM Aleksandar Markovic wrote: > > > > уторак, 23. јун 2020., Huacai Chen је написао/ла: >> >> Add myself as a maintainer of Loongson-3 virtual platform, and also add >> Jiaxun Yang as a reviewer. >> >> Signed-off-by: Huacai Chen >> Co-developed-by: J

Re: [PATCH] ibex_uart: fix XOR-as-pow

On 23/06/20 22:07, Eric Blake wrote: >> >> uint64_t baud = ((value & UART_CTRL_NCO) >> 16); >>   baud *= 1000; >> -    baud /= 2 ^ 20; >> +    baud >>= 20; > > Dividing by 1M instead of 22 seems much more logical, indeed :) Based on the spec, the "* 1000"

Re: [PATCH for-5.1 V5 3/4] hw/mips: Add Loongson-3 machine support (with KVM)

Hi, Aleksandar, On Tue, Jun 23, 2020 at 10:04 PM Aleksandar Markovic wrote: > > > > уторак, 23. јун 2020., Huacai Chen је написао/ла: >> >> Add Loongson-3 based machine support, it use i8259 as the interrupt >> controler and use GPEX as the pci controller. Currently it can only >> work with KVM,

qemu plugins bulid on windows

Hi all, I want to build QEMU 4.2.0 with the plugin module on Windows 7 with Mingw, but the building process faild. The step I follow is listed below: 1. create "dsp_build" diretory under source file folder 2. change directory to dsp_build , and run ../configure --target-list=dsp-softmmu

Re: -enablefips

On Tue, Jun 23, 2020 at 11:51:09PM -0400, John Snow wrote: > I never knew what this option did, but the answer is ... strange! > > It's only defined for linux, in os-posix.c. When called, it calls > fips_set_state(true), located in osdep.c. > > This will read /proc/sys/crypto/fips_enabled and set

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