On Mon, May 04, 2020 at 12:35:39PM +0200, Philippe Mathieu-Daudé wrote:
> Hi Roger,
>
> On 5/4/20 12:14 PM, Roger Pau Monne wrote:
> > has_igd_gfx_passthru is only available when QEMU is built with
> > CONFIG_XEN_PCI_PASSTHROUGH, and hence shouldn't be used in common
> > code without checking if i
Else the log will be flooded if there is a lot of network
traffic.
Signed-off-by: Lukas Straub
Reviewed-by: Zhang Chen
---
net/colo-compare.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
index 2a4e7f7c4e..56db3d3bfc 10064
On Thu, Apr 16, 2020 at 11:36:23PM +0300, Maxim Levitsky wrote:
> Some code might race with placement of new devices on a bus.
> We currently first place a (unrealized) device on the bus
> and then realize it.
>
> As a workaround, users that scan the child device list, can
> check the realized pro
> -Original Message-
> From: Grzegorz Uriasz
> Sent: 29 April 2020 04:04
> To: qemu-devel@nongnu.org
> Cc: Grzegorz Uriasz ;
marma...@invisiblethingslab.com; ar...@puzio.waw.pl;
> ja...@bartmin.ski; j.nowa...@student.uw.edu.pl; Stefano Stabellini
; Anthony
> Perard ; Paul Durrant ;
xen-de.
On Mon, 4 May 2020, at 19:07, Joel Stanley wrote:
> There are minimal differences from Qemu's point of view between the A0
> and A1 silicon revisions.
>
> As the A1 exercises different code paths in u-boot it is desirable to
> emulate that instead.
>
> Signed-off-by: Joel Stanley
> ---
> hw/
On Thu, Apr 16, 2020 at 11:36:20PM +0300, Maxim Levitsky wrote:
> Hi!
>
> This is a patch series that is a result of my discussion with Paulo on
> how to correctly fix the root cause of the BZ #1812399.
>
> The root cause of this bug is the fact that IO thread is running mostly
> unlocked versus
On Tue, 28 Apr 2020 at 17:03, Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Calling access_el3_aa32ns() works for AArch32 only cores
> but it does not handle 32-bit EL2 on top of 64-bit EL3
> for mixed 32/64-bit cores.
>
> Fold access_el3_aa32ns() into access_el3_aa32ns_aa64any()
> a
On Wed, 29 Apr 2020 07:51:04 +0200
Markus Armbruster wrote:
> David Hildenbrand writes:
>
> > On 24.04.20 21:20, Markus Armbruster wrote:
> >> Commit e47970f51d "s390x/cpumodel: Fix query-cpu-model-FOO error API
> >> violations" neglected to change visit_end_struct()'s Error ** argument
> >>
On Mon, May 04, 2020 at 11:06:48AM +0100, Peter Maydell wrote:
> On Mon, 4 May 2020 at 10:57, Michael S. Tsirkin wrote:
>
> > > ./scripts/checkpatch.pl --mailback base..
>
> > > 2/7 Checking commit 5554e78b18ea (nvdimm: Use configurable ACPI IO base
> > > and size)
> > > ERROR: Do not add expec
On 04/05/20 12:45, Stefan Hajnoczi wrote:
>> @@ -983,7 +983,7 @@ static void device_set_realized(Object *obj, bool value,
>> Error **errp)
>> }
>>
>> assert(local_err == NULL);
>> -dev->realized = value;
>> +atomic_set(&dev->realized, value);
> A memory barrier is probably need
On 16/04/20 22:36, Maxim Levitsky wrote:
> Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1812399
>
> Suggested-by: Paolo Bonzini
> Signed-off-by: Maxim Levitsky
> ---
> hw/scsi/virtio-scsi.c | 18 +-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/hw/
On 5/4/20 12:28 PM, Lukas Straub wrote:
Else the log will be flooded if there is a lot of network
traffic.
Signed-off-by: Lukas Straub
Reviewed-by: Zhang Chen
---
net/colo-compare.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/net/colo-compare.c b/net/colo-
Patchew URL: https://patchew.org/QEMU/20200504084615.27642-1-f4...@amsat.org/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/
On Fri, 17 Apr 2020 14:11:05 +1000
Alexey Kardashevskiy wrote:
> At the moment the VCPU init sequence includes setting PVR which in case of
> KVM-HV only checks if it matches the hardware PVR mask as PVR cannot be
> virtualized by the hardware. In order to cope with various CPU revisions
> only t
On Mon, 2020-05-04 at 13:22 +0200, Paolo Bonzini wrote:
> On 04/05/20 12:45, Stefan Hajnoczi wrote:
> > > @@ -983,7 +983,7 @@ static void device_set_realized(Object *obj, bool
> > > value, Error **errp)
> > > }
> > >
> > > assert(local_err == NULL);
> > > -dev->realized = value;
>
On 21.04.20 23:20, Eric Blake wrote:
> It's useful to know how much space can be occupied by qcow2 persistent
> bitmaps, even though such metadata is unrelated to the guest-visible
> data. Report this value as an additional field. Update iotest 190 to
> cover it and a portion of the just-added qe
Patchew URL: https://patchew.org/QEMU/20200504084615.27642-1-f4...@amsat.org/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
export A
On 04/05/20 12:59, Stefan Hajnoczi wrote:
> Regarding drive_del, I guess the issue here is that this HMP command's
> semantics need to include not synchronize_rcu() but some kind of
> drain_call_rcu() operation as well that ensures deletion has completed?
Good idea, this would be Linux's rcu_barri
On 5/4/20 1:30 PM, Greg Kurz wrote:
> On Fri, 17 Apr 2020 14:11:05 +1000
> Alexey Kardashevskiy wrote:
>
>> At the moment the VCPU init sequence includes setting PVR which in case of
>> KVM-HV only checks if it matches the hardware PVR mask as PVR cannot be
>> virtualized by the hardware. In o
On Mon, 2020-05-04 at 13:38 +0200, Paolo Bonzini wrote:
> On 04/05/20 12:59, Stefan Hajnoczi wrote:
> > Regarding drive_del, I guess the issue here is that this HMP command's
> > semantics need to include not synchronize_rcu() but some kind of
> > drain_call_rcu() operation as well that ensures del
Some QOM patches worth salvaging while doing housekeeping.
Since v1:
- Fixed test build failure (patchew)
Philippe Mathieu-Daudé (3):
qom/object: Move Object typedef to 'qemu/typedefs.h'
io/task: Move 'qom/object.h' header to source
qom/object: Make reparenting error more verbose
include/
Display child and parent names when reparenting occurs.
Signed-off-by: Philippe Mathieu-Daudé
---
qom/object.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/qom/object.c b/qom/object.c
index be700e831f..417fd90aa5 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -1683,
We need "qom/object.h" to call object_ref()/object_unref(),
and to test the TYPE_DUMMY.
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Add missing header in tests/test-io-task.c (patchew)
---
include/io/task.h| 2 --
io/task.c| 1 +
tests/test-io-task.c | 1 +
3 files changed, 2 i
From: Chen Qun
Clang static code analyzer show warning:
hw/display/blizzard.c:940:9: warning: Value stored to 'data' is never read
data >>= 5;
^~
Reported-by: Euler Robot
Signed-off-by: Chen Qun
Reviewed-by: Laurent Vivier
Message-Id: <20200325025919.21316-3-kuhn.chen
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
CC blockdev.o
blockdev.c:2744:5: warning: Value stored to 'ret' is never read
ret = blk_truncate(blk, size, false, PREALLOC_MODE_OFF, errp);
^ ~
From: Chen Qun
Fix: eaec903c5b8
Reported-by: Euler Robot
Signed-off-by: Chen Qun
Acked-by: Daniel P. Berrangé
Reviewed-by: Laurent Vivier
Message-Id: <20200325092137.24020-4-kuhn.chen...@huawei.com>
Signed-off-by: Laurent Vivier
---
crypto/cipher-builtin.c | 6 ++
1 file changed, 2 ins
We use the Object type all over the place.
Forward declare it in "qemu/typedefs.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/typedefs.h | 1 +
include/qom/object.h | 2 --
include/qom/qom-qobject.h | 2 --
include/sysemu/sysemu.h | 1 -
4 files changed, 1 insertion(+), 5 d
From: Wainer dos Santos Moschetta
The error report in pc_dimm_pre_plug() now has the slot
number printed.
Signed-off-by: Wainer dos Santos Moschetta
Message-Id: <20200310180510.19489-2-waine...@redhat.com>
Signed-off-by: Laurent Vivier
---
hw/mem/pc-dimm.c | 4 ++--
1 file changed, 2 insertio
ch-for-5.1-pull-request
for you to fetch changes up to 4341a0106781043a708c061b676312e5bb5d4488:
hw/timer/pxa2xx_timer: Add assertion to silent static analyzer warning (202=
0-05-04 12:06:21 +0200)
trivial patches (20200504)
Sil
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
CC hw/timer/stm32f2xx_timer.o
hw/timer/stm32f2xx_timer.c:225:9: warning: Value stored to 'value' is never
read
value = timer_val;
^ ~
Reported-by: Clang Static Analyzer
From: Mikhail Gusarov
macOS API for dealing with serial ports/ttys is identical to BSDs.
Signed-off-by: Mikhail Gusarov
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20200426210956.17324-1-dotted...@dottedmag.net>
Signed-off-by: Laurent Vivier
---
charde
From: Wainer dos Santos Moschetta
Signed-off-by: Wainer dos Santos Moschetta
Message-Id: <20200310180510.19489-3-waine...@redhat.com>
Signed-off-by: Laurent Vivier
---
hw/mem/pc-dimm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c
ind
From: Chen Qun
Clang static code analyzer show warning:
hw/scsi/esp-pci.c:198:9: warning: Value stored to 'size' is never read
size = 4;
^ ~
Reported-by: Euler Robot
Signed-off-by: Chen Qun
Reviewed-by: Laurent Vivier
Message-Id: <20200325025919.21316-2-kuhn.chen...@hua
From: Chen Qun
Clang static code analyzer show warning:
hw/timer/exynos4210_mct.c:1370:9: warning: Value stored to 'index' is never read
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
^ ~
hw/timer/exynos4210_mct.c:1399:9: warning: Value st
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
CC hw/i2c/pm_smbus.o
hw/i2c/pm_smbus.c:187:17: warning: Value stored to 'ret' is never read
ret = 0;
^ ~
Reported-by: Clang Static Analyzer
Reviewed-by: Alistair F
From: Philippe Mathieu-Daudé
Michael Walle expressed his desire to orphan the lm32 target [*]:
I guess it is time to pull the plug. Mainly, because I have
no time for this anymore. I've always worked on this on my
spare time and life changed. And secondly, I guess RISC-V is
taking over ;
From: Peter Maydell
Calling g_mapped_file_unref() on a NULL pointer is not valid, and
glib will assert if you try it.
$ qemu-system-arm -M virt -display none -device loader,file=/tmp/bad.elf
qemu-system-arm: -device loader,file=/tmp/bad.elf: GLib: g_mapped_file_unref:
assertion 'file != NULL' f
From: Philippe Mathieu-Daudé
keith.bu...@intel.com address is being rejected.
Replace by the email address Keith is actively using.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Keith Busch
Message-Id: <20200421122236.24867-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
MAINTAINERS |
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
hw/gpio/aspeed_gpio.c:717:18: warning: Value stored to 'g_idx' during its
initialization is never read
int set_idx, g_idx = *group_idx;
^ ~~
Reported-by: Clang Static Analy
From: Simran Singhal
Compress two lines into a single line if immediate return statement is found.
It also remove variables progress, val, data, ret and sock
as they are no longer needed.
Remove space between function "mixer_load" and '(' to fix the
checkpatch.pl error:-
ERROR: space prohibited
From: Philippe Mathieu-Daudé
Rename the unique variable assigned as 'pit' which better
represents what it holds, to fix a warning reported by the
Clang static code analyzer:
CC hw/isa/i82378.o
hw/isa/i82378.c:108:5: warning: Value stored to 'isa' is never read
isa = isa_create_s
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
block.c:3167:5: warning: Value stored to 'ret' is never read
ret = bdrv_fill_options(&options, filename, &flags, &local_err);
^ ~
Fixes: 462
Fix a couple of bugs that surfaced.
Michael S. Tsirkin (2):
checkpatch: fix acpi check with multiple file name
checkpatch: ignore allowed diff list
scripts/checkpatch.pl | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
--
MST
Allow changing allowed diff list at any point:
- when changing code under test
- when adding expected files
It's just a list of files so easy to review and merge anyway.
Signed-off-by: Michael S. Tsirkin
---
scripts/checkpatch.pl | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
CC hw/ide/sii3112.o
hw/ide/sii3112.c:204:9: warning: Value stored to 'val' is never read
val = 0;
^ ~
Fixes: a9dd6604
Reported-by: Clang Static Analyzer
Reviewed-by: BALATON Zolta
On 5/4/20 1:27 PM, Philippe Mathieu-Daudé wrote:
On 5/4/20 12:28 PM, Lukas Straub wrote:
Else the log will be flooded if there is a lot of network
traffic.
Signed-off-by: Lukas Straub
Reviewed-by: Zhang Chen
---
net/colo-compare.c | 10 ++
1 file changed, 6 insertions(+), 4 deletio
From: Philippe Mathieu-Daudé
pxa2xx_timer_tick4() takes an opaque pointer, then calls
pxa2xx_timer_update4(), so the static analyzer can not
verify that the 'n < 8':
425 static void pxa2xx_timer_tick4(void *opaque)
426 {
427 PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
428 PXA2xxTi
Using global expected/nonexpected values causes
false positives when testing multiple patches in one
checkpatch run: one patch can change expected,
another one non-expected.
Use local variables within process() to fix that.
Signed-off-by: Michael S. Tsirkin
---
scripts/checkpatch.pl | 22 ++
From: Philippe Mathieu-Daudé
Since commit 5a1f49718 the 'olen' variable is not really
used. Remove it to fix a warning reported by Clang static
code analyzer:
CC hw/input/adb-kbd.o
hw/input/adb-kbd.c:200:5: warning: Value stored to 'olen' is never read
olen = 0;
^ ~
On 21.04.20 23:20, Eric Blake wrote:
> Make it easier to copy all the persistent bitmaps of a source image
> along with the contents, by adding a boolean flag for use with
> qemu-img convert. This is basically shorthand, as the same effect
> could be accomplished with a series of 'qemu-img bitmap
On Thu, 30 Apr 2020 at 19:10, Peter Maydell wrote:
>
> This patchseries starts in on the job of converting the Arm
> Neon decoder to decodetree.
>
> Neon insns come in three major parts:
> * the 'v8.0-and-later' extensions
> * the 'loads and stores' group
> * the 'data processing' group
>
> Thi
On Mon, 4 May 2020, Philippe Mathieu-Daudé wrote:
On 5/4/20 12:12 PM, Philippe Mathieu-Daudé wrote:
On 5/4/20 10:48 AM, BALATON Zoltan wrote:
On Mon, 4 May 2020, Philippe Mathieu-Daudé wrote:
As target-specific code use this header, move it to the publicly
accessible include/ folder.
$ git g
c analyzer warning (202=
> 0-05-04 12:06:21 +0200)
>
> ----
> trivial patches (20200504)
>
> Silent static analyzer warning
> Remove dead assignments
> Support -chardev serial on macOS
> Update MAINTAINERS
> Some cosmetic changes
Compile
d4488:
>>
>> hw/timer/pxa2xx_timer: Add assertion to silent static analyzer warning
>> (202=
>> 0-05-04 12:06:21 +0200)
>>
>>
>> trivial patches (20200504)
>>
>> Silent static ana
From: Philippe Mathieu-Daudé
By using the TYPE_* definitions for devices, we can:
- quickly find where devices are used with 'git-grep'
- easily rename a device (one-line change).
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200428154650.21991-1-f4...@amsat.org
Reviewed-by: Peter Mayde
We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
TLB. However we never actually use the TLB -- all stage 2 lookups
are done by direct calls to get_phys_addr_lpae() followed by a
physical address load via address_space_ld*().
Remove Stage2 from the list of ARM MMU indexes which c
From: Fredrik Strupe
According to Arm ARM, VQDMULL is only valid when U=0, while having
U=1 is unallocated.
Signed-off-by: Fredrik Strupe
Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon
3-regs-different-widths")
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
targe
The access_type argument to get_phys_addr_lpae() is an MMUAccessType;
use the enum constant MMU_DATA_LOAD rather than a literal 0 when we
call it in S1_ptw_translate().
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Richard Henderson
Message-id: 20200330210400.11724-3-
From: "Edgar E. Iglesias"
Move misplaced comment.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-3-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 2
The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
translation table descriptors from just bit [54] to bits [54:53],
allowing stage 2 to control execution permissions separately for EL0
and EL1. Implement the new semantics of the XN field and enable
the feature for our 'max' CPU.
Signed-o
:56 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20200504
for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:
target/arm: Move gen_ function typedefs to translate.h (2020-05-04
From: "Edgar E. Iglesias"
Remove inclusion of arm_gicv3_common.h, this already gets
included via xlnx-versal.h.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-2-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
From: "Edgar E. Iglesias"
Embed the ADMAs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-7-edgar.igles...@gmail.com
Signed-off-by: Pete
For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know
whether the stage 1 access is for EL0 or not, because whether
exec permission is given can depend on whether this is an EL0
or EL1 access. Add a new argument to get_phys_addr_lpae() so
the call sites can pass this information in.
Since
From: Philippe Mathieu-Daudé
MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
Represent it in QEMU's ARMCPU struct with a uint64_t, not a
uint32_t.
This fixes an error when compiling with -Werror=conversion
because we were manipulating the register value using a
local uint64_
From: "Edgar E. Iglesias"
Add support for SD.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-9-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
include/hw/arm/xlnx-versal.h
In aarch64_max_initfn() we update both 32-bit and 64-bit ID
registers. The intended pattern is that for 64-bit ID registers we
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
registers use FIELD_DP32 and the uint32_t 'u' register. For
ID_AA64DFR0 we accidentally used 'u', meaning th
From: "Edgar E. Iglesias"
Fix typo xlnx-ve -> xlnx-versal.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-4-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/xlnx-ver
Convert the VCADD (vector) insns to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-6-peter.mayd...@linaro.org
---
target/arm/neon-shared.decode | 3 +++
target/arm/translate-neon.inc.c | 37 +
target/ar
From: "Edgar E. Iglesias"
Add support for SD.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-11-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 46 +
From: "Edgar E. Iglesias"
Embed the UARTs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-5-edgar.igles...@gmail.com
Signed-off-by: Pete
From: "Edgar E. Iglesias"
hw/arm: versal: Add support for the RTC.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-10-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
includ
Convert the V[US]DOT (vector) insns to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-7-peter.mayd...@linaro.org
---
target/arm/neon-shared.decode | 4
target/arm/translate-neon.inc.c | 32
target
We were accidentally permitting decode of Thumb Neon insns even if
the CPU didn't have the FEATURE_NEON bit set, because the feature
check was being done before the call to disas_neon_data_insn() and
disas_neon_ls_insn() in the Arm decoder but was omitted from the
Thumb decoder. Push the feature b
Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
to decodetree. These are the last ones in the group so we can remove
all the legacy decode for the group.
Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be
Convert the Neon "load/store single structure to one lane" insns to
decodetree.
As this is the last set of insns in the neon load/store group,
we can remove the whole disas_neon_ls_insn() function.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-14-p
Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 Neon encodings. At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.
We follow the same pattern we did for the VFP decodetree conversion
(commit 78e138bc1f672
From: "Edgar E. Iglesias"
Embed the GEMs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-6-edgar.igles...@gmail.com
Signed-off-by: Peter
Convert the VCMLA (vector) insns in the 3same extension group to
decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-5-peter.mayd...@linaro.org
---
target/arm/neon-shared.decode | 11 ++
target/arm/translate-neon.inc.c | 37
From: "Edgar E. Iglesias"
Embed the APUs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-8-edgar.igles...@gmail.com
Signed-off-by: Peter
Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
3-reg-same grouping to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-20-peter.mayd...@linaro.org
---
target/arm/neon-dp.decode | 9 +++
target/arm/translate-neon.inc.c |
106781043a708c061b676312e5bb5d4488:
> >
> > hw/timer/pxa2xx_timer: Add assertion to silent static analyzer warning
> > (202=
> > 0-05-04 12:06:21 +0200)
> >
> >
> > trivial patches (20200504)
Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-9-peter.mayd...@linaro.org
---
target/arm/neon-shared.decode | 5 +
target/arm/translate-neon.inc.c | 40 +++
From: "Edgar E. Iglesias"
Add support for the RTC.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Message-id: 20200427181649.26851-12-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 22 ++
1 fi
Le 03/04/2020 à 10:47, Laurent Vivier a écrit :
> Le 25/03/2020 à 10:21, Chen Qun a écrit :
>> Fix: eaec903c5b8
>>
>> Reported-by: Euler Robot
>> Signed-off-by: Chen Qun
>> ---
>> Cc: "Daniel P. Berrangé"
>> ---
>> crypto/cipher-builtin.c | 6 ++
>> 1 file changed, 2 insertions(+), 4 deleti
Convert the Neon "load/store multiple structures" insns to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-12-peter.mayd...@linaro.org
---
target/arm/neon-ls.decode | 7 ++
target/arm/translate-neon.inc.c | 124 +++
Somewhere along theline we accidentally added a duplicate
"using D16-D31 when they don't exist" check to do_vfm_dp()
(probably an artifact of a patchseries rebase). Remove it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20200430181
On Wed, Apr 29, 2020 at 03:59:48PM +0200, Gerd Hoffmann wrote:
> First batch of microvm patches, some generic acpi stuff.
> Split the acpi-build.c monster, specifically split the
> pc and q35 and pci bits into a separate file which we
> can skip building at some point in the future.
OK I applied 1
Convert the Neon "load single structure to all lanes" insns to
decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-13-peter.mayd...@linaro.org
---
target/arm/neon-ls.decode | 5 +++
target/arm/translate-neon.inc.c | 73
Convert the VFM[AS]L (vector) insns to decodetree. This is the last
insn in the legacy decoder for the 3same_ext group, so we can
delete the legacy decoder function for the group entirely.
Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false
Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-10-peter.mayd...@linaro.org
---
target/arm/neon-shared.decode | 3 +++
target/arm/translate-neon.inc.c | 35 +++
Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.
Note that we don't need the neon_3r_sizes[op] check here because all
size values are OK for VADD and VSUB; we'll add this when we convert
the first insn that has size restrictions.
For this we need one of the GVecGen*Fn typedefs curre
Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-17-peter.mayd...@linaro.org
---
target/arm/neon-dp.decode | 5 +
target/arm/translate-neon.inc.c | 14 ++
target/arm
Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
Note that for the logic ops the 'size' field forms part of their
decode and the actual operations are always bitwise.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-16-peter.mayd...
Convert the Neon comparison ops in the 3-reg-same grouping
to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-18-peter.mayd...@linaro.org
---
target/arm/neon-dp.decode | 8
target/arm/translate-neon.inc.c | 22
Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-19-peter.mayd...@linaro.org
---
target/arm/neon-dp.decode | 6 ++
target/arm/translate-neon.inc.c | 15 +++
81043a708c061b676312e5bb5d4488:
> >
> > hw/timer/pxa2xx_timer: Add assertion to silent static analyzer warning
> > (202=
> > 0-05-04 12:06:21 +0200)
> >
> >
> > trivial patches (20200504)
>
We're going to want at least some of the NeonGen* typedefs
for the refactored 32-bit Neon decoder, so move them all
to translate.h since it makes more sense to keep them in
one group.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200430181003.21682-23-peter.mayd...@li
trivial-branch-for-5.1-pull-request
>>>
>>> for you to fetch changes up to 4341a0106781043a708c061b676312e5bb5d4488:
>>>
>>> hw/timer/pxa2xx_timer: Add assertion to silent static analyzer warning
>>> (202=
>>> 0-05-04 12:06:21 +0200)
>>>
>>&
On 28/04/20 18:34, Markus Armbruster wrote:
> Includes one actual bug fix for s390x.
I reviewed everything except patch 8 and it looks good. Thanks very much!
Paolo
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