Let's link getchar.o to use puts and getchar from the
tests.
Then allow tests belonging to the migration group to
trigger the migration from the test code by putting
"migrate" into the uart. Then the code can wait for the
migration completion by using getchar().
The __getchar implement is minimal
Patchew URL: https://patchew.org/QEMU/2020030919.17624-1-kra...@redhat.com/
Hi,
This series failed the docker-clang@ubuntu build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
its_enable_defaults() enable LPIs at distributor level
and ITS level.
gicv3_enable_defaults must be called before.
Signed-off-by: Eric Auger
---
v3 -> v4:
- use GITS_BASER_INDIRECT & GITS_BASER_VALID in its_setup_baser()
- don't parse BASERs again in its_enable_defaults
- rename its_setup_baser
Triggers LPIs through the INT command.
the test checks the LPI hits the right CPU and triggers
the right LPI intid, ie. the translation is correct.
Updates to the config table also are tested, along with inv
and invall commands.
Signed-off-by: Eric Auger
---
v3 -> v4:
- assert in lpi_handler
On 3/9/2020 5:16 PM, Laurent Vivier wrote:
> Le 07/03/2020 à 11:39, Marc-André Lureau a écrit :
>> Hi
>>
>> On Sat, Mar 7, 2020 at 3:53 AM Pan Nengyuan wrote:
>>>
>>> Fix a memory leak in qdev_get_gpio_out_connector().
>>>
>>> Reported-by: Euler Robot
>>> Signed-off-by: Pan Nengyuan
>>
>> goo
hello, is this patch ready to merge now? Thanks!
On Fri, Feb 21, 2020 at 08:25:59AM +0800, Changbin Du wrote:
> Recently when debugging an arm32 system on qemu, I found sometimes the
> single-step command (stepi) is not working. This can be reproduced by
> below steps:
> 1) start qemu-system-arm
On 3/9/20 10:57 AM, Daniel P. Berrangé wrote:
On Sat, Mar 07, 2020 at 06:22:21PM +0100, Philippe Mathieu-Daudé wrote:
The Simple Authentication and Security Layer (SASL) library
re-defines the struct iovec on Win32 [*]. QEMU also re-defines
it in "qemu/osdep.h". The two definitions then clash on
Patchew URL: https://patchew.org/QEMU/20200309100342.14921-1-coiby...@gmail.com/
Hi,
This series failed the docker-clang@ubuntu build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#
On Mon, Mar 09, 2020 at 10:16:28AM +0100, Laurent Vivier wrote:
> Le 07/03/2020 à 11:39, Marc-André Lureau a écrit :
> > Hi
> >
> > On Sat, Mar 7, 2020 at 3:53 AM Pan Nengyuan wrote:
> >>
> >> Fix a memory leak in qdev_get_gpio_out_connector().
> >>
> >> Reported-by: Euler Robot
> >> Signed-off-
Le 09/03/2020 à 11:41, Pan Nengyuan a écrit :
>
>
> On 3/9/2020 5:16 PM, Laurent Vivier wrote:
>> Le 07/03/2020 à 11:39, Marc-André Lureau a écrit :
>>> Hi
>>>
>>> On Sat, Mar 7, 2020 at 3:53 AM Pan Nengyuan wrote:
Fix a memory leak in qdev_get_gpio_out_connector().
Reported-
On 3/9/20 7:30 AM, Yoshinori Sato wrote:
On Mon, 09 Mar 2020 01:20:05 +0900,
Philippe Mathieu-Daudé wrote:
On 2/24/20 3:19 PM, Yoshinori Sato wrote:
From: Philippe Mathieu-Daudé
Add two tests for the rx-virt machine, based on the recommended test
setup from Yoshinori Sato:
https://lists.gnu.
On Mon, Mar 09, 2020 at 11:24:10AM +0100, Eric Auger wrote:
> ipi_enable() code would be reusable for other interrupts
> than IPI. Let's rename it setup_irq() and pass an interrupt
> handler pointer.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - do not export setup_irq anymore
> ---
>
Hi Peter,
On 2/27/20 2:35 PM, Philippe Mathieu-Daudé wrote:
On 2/27/20 1:13 PM, Peter Maydell wrote:
On Thu, 27 Feb 2020 at 11:27, Stephanos Ioannidis
wrote:
The ARMv7-M CPU reset handler, which loads the initial SP and PC
register values from the vector table, is currently executed before
t
On 09.03.20 11:05, Paolo Bonzini wrote:
> On 09/03/20 11:03, Igor Mammedov wrote:
>>> +qemu_cond_init(&page_cond);
>>> +qemu_mutex_init(&page_mutex);
>> Is it possible for touch_all_pages to be called several times?
>> If it's then it probably needs a guard against that to make
>> sure i
On 03.03.20 11:05, Peter Maydell wrote:
> The CPUClass has a 'reset' method. This is a legacy from when
> TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
> more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
> function is kept as the API which most places u
Thanks, in fact,do_touch_pages is called just when vm starts up, but using
init flag and Gonce maybe more elegant !
if needed,I can submit a new patch !
thanks very much!
bauerchen
From: Christian Borntraeger
Date: 2020-03-09 19:01
To: Paolo Bonzini; Igor Mammedov
CC: qemu-devel; qemu-s390x;
On Tue, 3 Mar 2020 at 20:15, Niek Linnenbank wrote:
> On Tue, Mar 3, 2020 at 1:09 PM Alex Bennée wrote:
>> Niek Linnenbank writes:
>> > +static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
>> > +{
>> > +int ret;
>> > +
>> > +trace_allwinner_cpucfg_cpu_reset(cpu_id, s
On Mon, Mar 09, 2020 at 11:24:13AM +0100, Eric Auger wrote:
> Detect the presence of an ITS as part of the GICv3 init
> routine, initialize its base address and read few registers
> the IIDR, the TYPER to store its dimensioning parameters.
> Parse the BASER registers. As part of the init sequence w
On Wed, 4 Mar 2020 at 20:55, Niek Linnenbank wrote:
>
> Hello Alex,
>
> On Wed, Mar 4, 2020 at 11:35 AM Alex Bennée wrote:
>>
>>
>> Niek Linnenbank writes:
>> > ---
>> > docs/orangepi.rst | 226
>> > ++
>>
>> I suspect there is a better place to put th
Protected guests save the instruction control blocks in the SIDA
instead of QEMU/KVM directly accessing the guest's memory.
Let's introduce new functions to access the SIDA.
Also the new memops are available with KVM_CAP_S390_PROTECTED, so
let's check for that.
Signed-off-by: Janosch Frank
Revi
Ballooning in protected VMs can only be done when the guest shares the
pages it gives to the host. If pages are not shared, the integrity
checks will fail once those pages have been altered and are given back
to the guest.
Hence, until we have a solution for this in the guest kernel, we
inhibit ba
Most of the QEMU changes for PV are related to the new IPL type with
subcodes 8 - 10 and the execution of the necessary Ultravisor calls to
IPL secure guests. Note that we can only boot into secure mode from
normal mode, i.e. stfle 161 is not active in secure mode.
The other changes related to dat
Signed-off-by: Janosch Frank
---
linux-headers/linux/kvm.h | 45 +--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 265099100e..c30344ab00 100644
--- a/linux-headers/linux/kvm.h
+++ b/l
SCLP for a protected guest is done over the SIDAD, so we need to use
the s390_cpu_pv_mem_* functions to access the SIDAD instead of guest
memory when reading/writing SCBs.
To not confuse the sclp emulation, we set 0x4000 as the SCCB address,
since the function that injects the sclp external interr
For protected guests the IPIB is written/read to/from the SIDA, so we
need those accesses to go through s390_cpu_pv_mem_read/write().
Signed-off-by: Janosch Frank
---
target/s390x/diag.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/target/s3
Migration is not yet supported.
Signed-off-by: Janosch Frank
---
hw/s390x/s390-virtio-ccw.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index f718cfc591..4bb38704ff 100644
--- a/hw/s390x/s
The unpack facility provides the means to setup a protected guest. A
protected guest can not be introspected by the hypervisor or any
user/administrator of the machine it is running on.
Protected guests are encrypted at rest and need a special boot
mechanism via diag308 subcode 8 and 10.
Code 8 s
For protected guests, we need to put the STSI emulation results into
the SIDA, so SIE will write them into the guest at the next entry.
Signed-off-by: Janosch Frank
Reviewed-by: David Hildenbrand
---
target/s390x/kvm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --gi
IO instruction data is routed through SIDAD for protected guests, so
adresses do not need to be checked, as this is kernel memory.
Signed-off-by: Janosch Frank
Reviewed-by: Thomas Huth
Reviewed-by: David Hildenbrand
---
target/s390x/ioinst.c | 32 +---
1 file change
Handling of CPU reset and setting of the IPL psw from guest storage at
offset 0 is done by a Ultravisor call. Let's only fetch it if
necessary.
Signed-off-by: Janosch Frank
Reviewed-by: Thomas Huth
Reviewed-by: David Hildenbrand
---
target/s390x/cpu.c | 23 ++-
1 file chang
Secure guests no longer intercept with code 4 for an instruction
interception. Instead they have codes 104 and 108 for secure
instruction interception and secure instruction notification
respectively.
The 104 mirrors the 4 interception.
The 108 is a notification interception to let KVM and QEMU k
Lets add some documentation for the Protected VM functionality.
Signed-off-by: Janosch Frank
---
docs/system/index.rst| 1 +
docs/system/protvirt.rst | 56
2 files changed, 57 insertions(+)
create mode 100644 docs/system/protvirt.rst
diff --git a/d
For protected guests, we need to put the IO emulation results into the
SIDA, so SIE will write them into the guest at the next entry.
Signed-off-by: Janosch Frank
---
target/s390x/ioinst.c | 87 ++-
1 file changed, 61 insertions(+), 26 deletions(-)
diff -
From: Christian Borntraeger
The unpack facility is an indication that diagnose 308 subcodes 8-10
are available to the guest. That means, that the guest can put itself
into protected mode.
Once it is in protected mode, the hardware stops any attempt of VM
introspection by the hypervisor.
Some fe
Le 06/03/2020 à 17:57, Philippe Mathieu-Daudé a écrit :
> The socket_scm_helper path got corrupted during the mechanical
> refactor moving the qtests files into their own sub-directory.
>
> Fixes: 1e8a1fae7 ("test: Move qtests to a separate directory")
> Signed-off-by: Philippe Mathieu-Daudé
> --
Le 06/03/2020 à 18:04, Philippe Mathieu-Daudé a écrit :
> Currently the print-variable rule can only be used in the
> root directory:
>
> $ make print-vhost-user-json-y
> vhost-user-json-y= contrib/vhost-user-gpu/50-qemu-gpu.json
> tools/virtiofsd/50-qemu-virtiofsd.json
>
> $ make -C i386-
For protected VMs status storing is not done by QEMU anymore.
Signed-off-by: Janosch Frank
Reviewed-by: Thomas Huth
Reviewed-by: David Hildenbrand
---
target/s390x/helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index ed72684911..
On Mon, Mar 09, 2020 at 11:24:14AM +0100, Eric Auger wrote:
> its_enable_defaults() enable LPIs at distributor level
> and ITS level.
>
> gicv3_enable_defaults must be called before.
>
> Signed-off-by: Eric Auger
>
> ---
> v3 -> v4:
> - use GITS_BASER_INDIRECT & GITS_BASER_VALID in its_setup_ba
'nested' parameter for kvm_intel module controls whether you're able to
run nested configurations and it is enabled by default, it doesn't say
anything about whether your configuration is nested or not.
Could you please describe your environment? In case it is nested, it will look
like:
L0(host)
On Thu, 5 Mar 2020 at 10:53, Chen Qun wrote:
>
> The current code causes clang static code analyzer generate warning:
> hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
> value = value & 0x000f;
> ^ ~~
> hw/net/imx_fec.c:864:9: warnin
Le 05/03/2020 à 13:45, Philippe Mathieu-Daudé a écrit :
> Reviewed-by: Laurent Vivier
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/audio/fmopl.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/audio/fmopl.c b/hw/audio/fmopl.c
> index 9f50a89b4a..173a7521f2
On Mon, Mar 09, 2020 at 11:24:14AM +0100, Eric Auger wrote:
> its_enable_defaults() enable LPIs at distributor level
> and ITS level.
>
> gicv3_enable_defaults must be called before.
>
> Signed-off-by: Eric Auger
>
> ---
> v3 -> v4:
> - use GITS_BASER_INDIRECT & GITS_BASER_VALID in its_setup_ba
On 3/5/20 11:37 PM, Alex Williamson wrote:
On Fri, 28 Feb 2020 13:08:00 +0100
Roman Kapl wrote:
For MSI-X interrupts, remember what the last used eventfd was (KVM
bypass vs QEMU) and only call vfio_set_irq_signaling if it has changed.
This not only helps with performance, but it seems that in
Le 06/03/2020 à 10:25, Paolo Bonzini a écrit :
> On 05/03/20 02:04, Philippe Mathieu-Daudé wrote:
>> More memory footprint reduction, similar to:
>> https://lists.gnu.org/archive/html/qemu-devel/2020-03/msg00984.html
>>
>> The elf-dissector tool [1] [2] helped to notice the big array.
>>
>> [1] htt
On Mon, Mar 09, 2020 at 11:24:17AM +0100, Eric Auger wrote:
...
> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
> index 0096de6..956d7b8 100644
> --- a/lib/arm/asm/gic-v3-its.h
> +++ b/lib/arm/asm/gic-v3-its.h
> @@ -5,9 +5,8 @@
> *
> * This work is licensed under the terms of
Hi Drew,
On 3/9/20 12:39 PM, Andrew Jones wrote:
> On Mon, Mar 09, 2020 at 11:24:14AM +0100, Eric Auger wrote:
>> its_enable_defaults() enable LPIs at distributor level
>> and ITS level.
>>
>> gicv3_enable_defaults must be called before.
>>
>> Signed-off-by: Eric Auger
>>
>> ---
>> v3 -> v4:
>> -
Hi,
On 3/9/20 12:19 PM, Andrew Jones wrote:
> On Mon, Mar 09, 2020 at 11:24:13AM +0100, Eric Auger wrote:
>> Detect the presence of an ITS as part of the GICv3 init
>> routine, initialize its base address and read few registers
>> the IIDR, the TYPER to store its dimensioning parameters.
>> Parse
On Mon, Mar 09, 2020 at 12:45:34PM +0100, Auger Eric wrote:
> >> - for_each_present_cpu(cpu) {
> >> + for (cpu = 0; cpu < nr_cpus; cpu++) {
> >
> > You don't mention this change in the changelog.
> Hey, you can see the changelog is pretty long already & accurate. But
> you're right I missed that
Le 28/02/2020 à 12:46, Philippe Mathieu-Daudé a écrit :
> [Rebased since v1]:
> https://www.mail-archive.com/qemu-block@nongnu.org/msg57485.html
>
> This is a follow-up of Markus's cleanup series:
> Tame a few "touch this, recompile the world"
> https://www.mail-archive.com/qemu-devel@nongnu.org/m
On Mon, Mar 09, 2020 at 11:24:07AM +0100, Eric Auger wrote:
> This series is a revival of an RFC series sent in Dec 2016 [1].
> Given the amount of code and the lack of traction at that time,
> I haven't respinned until now. However a recent bug found related
> to the ITS migration convinced me tha
Le 27/02/2020 à 14:28, Paolo Bonzini a écrit :
> On 26/10/19 15:32, Laurent Vivier wrote:
>> Le 26/10/2019 à 14:20, Philippe Mathieu-Daudé a écrit :
>>> Hi,
>>>
>>> On 10/14/19 4:22 PM, Philippe Mathieu-Daudé wrote:
This is a follow-up of Markus's cleanup series:
Tame a few "touch this, r
On Fri, Mar 6, 2020 at 3:42 PM wrote:
> Patchew URL:
> https://patchew.org/QEMU/20200306132648.27577-1-christian.ehrha...@canonical.com/
>
>
>
> Hi,
>
> This series failed the docker-mingw@fedora build test. Please find the
> testing commands and
> their output below. If you have Docker installed
On Mon, Mar 09, 2020 at 12:57:51PM +0100, Andrew Jones wrote:
> This looks pretty good to me. It just needs some resquashing cleanups.
> Does Andre plan to review? I've only been reviewing with respect to
> the framework, not ITS. If no other reviews are expected, then I'll
> queue the next version
Le 07/03/2020 à 04:07, Pan Nengyuan a écrit :
> Fix a memory leak in qdev_get_gpio_out_connector().
>
> Reported-by: Euler Robot
> Signed-off-by: Pan Nengyuan
> ---
> hw/core/qdev.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/core/qdev.c b/hw/core/qdev.c
> index
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 71 +
4 files changed, 122 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 7 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 11 +++
4 files changed, 24 insertions(+)
diff --git a/target/
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 17 ++
target/riscv/vector_helper.c| 76 +
4 files changed, 134 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 10 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 5
target/riscv/vector_helper.c| 39 +
4 files changed, 58 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvv.inc.c | 28 +
target/riscv/vector_helper.c| 40 +
4 files changed, 85 insert
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
target/riscv/vector_helper.c| 50 +
4 files changed, 58 insertions(+)
diff --git a/t
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 20
4 files changed, 55 insertions(+)
cpu_reset() might modify architecture-specific fields allocated
by qemu_init_vcpu(). To avoid bugs similar to the one fixed in
commit 00d0f7cb66 when introducing new architectures, move the
cpu_reset() calls after qemu_init_vcpu().
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/cpu.c|
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 19 +++
4 files changed, 54 insertions(+)
d
Two trivial patches to avoid each (new) architecture to track
a bug already resolved once on ARM: cpu_reset() modify fields
in the CpuState while the state is not yet allocated.
Philippe Mathieu-Daudé (2):
cpu: Do not reset a vCPU before it is created
cpu: Assert a vCPU is created before reset
Le 02/03/2020 à 14:07, Chen Qun a écrit :
> Clang static code analyzer show warning:
> block/stream.c:186:9: warning: Value stored to 'ret' is never read
> ret = 0;
> ^ ~
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
> Reviewed-by: John Snow
> Reviewed-by: Kevin Wolf
cpu_reset() might modify architecture-specific fields allocated
by qemu_init_vcpu(). To avoid bugs similar to the one fixed in
commit 00d0f7cb66 when introducing new architectures, assert a
vCPU is created before resetting it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/cpu.c | 1 +
1 file
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 11 +++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 42 +
target/riscv/vector_helper.c| 42 +
4 files changed, 10
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makefile.objs |
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74 +
4 files changed, 125 insertions(+)
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49
target/riscv/insn32.decode | 16 +++
target/riscv/insn_trans/trans_rvv.inc.c | 154
target/riscv/vector_helper.c| 112 +
4 files changed, 331 in
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 128
4 files changed, 155 insertions(+)
diff --g
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode pro
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35 +++
target/riscv/insn32.decode
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c| 51 +
4 files changed, 96 insertions(
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvv.inc.c | 9 +
target/riscv/vector_helper.c| 45 +
4 files changed, 83 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 180
4 files changed, 218 insertions(+)
diff --gi
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 107
target/riscv/vector_helper.c| 89
4 files changed, 217 inse
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 21 +++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 220
target/riscv/vector_helper.c| 122 +
4 files changed, 373 insertions(+
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
target/riscv/vector_helper.c| 76 +
4 files changed, 109 insertions(+)
diff -
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 129
4 files changed, 158 insertions(+)
diff --g
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 91 +
target/riscv/vector_helper.c| 14
4 files changed, 124 insertions(+)
diff --g
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 131
target/riscv/vector_helper.c| 77 ++
4 files changed, 233 insertions(
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 103
4 files changed, 118 insertions(+)
diff --git
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 88 +
4 files changed, 139 insertions(+)
di
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 37 +++
target/riscv/vector_helper.c| 40 +
4 files changed, 84 insert
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 109
4 files changed, 140 insertions(+)
diff --
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 24 ++
target/riscv/vector_helper.c| 58 +
4 files changed, 94 insertions(+)
dif
Le 02/03/2020 à 14:07, Chen Qun a écrit :
> Clang static code analyzer show warning:
> block/file-posix.c:891:9: warning: Value stored to 'op' is never read
> op = RAW_PL_ABORT;
> ^
>
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
> Reviewed-by: Kevin Wolf
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16 +
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 48 +
4 files changed, 76 insertions(+)
dif
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51 +
4 files changed, 84 insertions(+)
dif
Le 02/03/2020 à 14:07, Chen Qun a écrit :
> Clang static code analyzer show warning:
> hw/scsi/esp-pci.c:198:9: warning: Value stored to 'size' is never read
> size = 4;
> ^ ~
>
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
> ---
> Cc: Paolo Bonzini
> Cc:Fam Zheng
Le 02/03/2020 à 14:07, Chen Qun a écrit :
> Clang static code analyzer show warning:
> hw/display/pxa2xx_lcd.c:596:9: warning: Value stored to 'format' is never read
> format = 0;
> ^~
>
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
> ---
> Cc: Andrzej Zaborowski
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 ++
target/riscv/vector_helper.c| 278
4 files changed, 337 insertions(+)
diff --gi
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 147
4 files changed, 198 insertions(+)
diff
101 - 200 of 548 matches
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