On Mon, Mar 09, 2020 at 10:17:38AM +0800, Pan Nengyuan wrote:
> We neglect to free port->bh on the error paths. Fix that.
> Reproducer:
> {'execute': 'device_add', 'arguments': {'id': 'virtio_serial_pci0',
> 'driver': 'virtio-serial-pci', 'bus': 'pci.0', 'addr': '0x5'}, 'id':
> 'yVkZcGgV'}
>
Hi Kirti:
What kind of platform/IO are you using now to do the basic code
verification?
I just want to check if I can verify it on my platform, and if any open
IO cards available?
Thanks.
Regards
Zengtao
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.ke
On 09/03/2020 03:17, Pan Nengyuan wrote:
> We neglect to free port->bh on the error paths. Fix that.
> Reproducer:
> {'execute': 'device_add', 'arguments': {'id': 'virtio_serial_pci0',
> 'driver': 'virtio-serial-pci', 'bus': 'pci.0', 'addr': '0x5'}, 'id':
> 'yVkZcGgV'}
> {'execute': 'dev
"Michael S. Tsirkin" writes:
> On Mon, Mar 09, 2020 at 10:17:38AM +0800, Pan Nengyuan wrote:
>> We neglect to free port->bh on the error paths. Fix that.
>> Reproducer:
>> {'execute': 'device_add', 'arguments': {'id': 'virtio_serial_pci0',
>> 'driver': 'virtio-serial-pci', 'bus': 'pci.0', '
On Mon, 2020-03-09 at 03:02 -0400, Michael S. Tsirkin wrote:
> On Mon, Mar 09, 2020 at 10:17:38AM +0800, Pan Nengyuan wrote:
> > We neglect to free port->bh on the error paths. Fix that.
> > Reproducer:
> > {'execute': 'device_add', 'arguments': {'id':
> > 'virtio_serial_pci0', 'driver': 'virt
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode pro
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 21 +++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 220
target/riscv/vector_helper.c| 122 +
4 files changed, 373 insertions(+
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makefile.objs |
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49
target/riscv/insn32.decode | 16 +++
target/riscv/insn_trans/trans_rvv.inc.c | 154
target/riscv/vector_helper.c| 112 +
4 files changed, 331 in
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 88 +
4 files changed, 139 insertions(+)
di
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35 +++
target/riscv/insn32.decode
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 129
4 files changed, 158 insertions(+)
diff --g
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 103
4 files changed, 118 insertions(+)
diff --git
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16 +
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 48 +
4 files changed, 76 insertions(+)
dif
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c| 51 +
4 files changed, 96 insertions(
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 109
4 files changed, 140 insertions(+)
diff --
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 ++
target/riscv/vector_helper.c| 278
4 files changed, 337 insertions(+)
diff --gi
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74 +
4 files changed, 125 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 84 +
4 files changed, 119 insertions(+)
diff --
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51 +
4 files changed, 84 insertions(+)
dif
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 12 +++
target/riscv/vector_helper.c| 28 +
4 files changed, 45 insertions(+)
dif
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 147
4 files changed, 198 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
target/riscv/vector_helper.c| 62 +
4 files changed, 70 insertions(+)
diff --git a/t
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 44 +
target/riscv/vector_helper.c| 82 +
4 files changed, 160 insertion
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 107
target/riscv/vector_helper.c| 89
4 files changed, 217 inse
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 91 +
target/riscv/vector_helper.c| 14
4 files changed, 124 insertions(+)
diff --g
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 180
4 files changed, 218 insertions(+)
diff --gi
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 42 +++
target/riscv/vector_helper.c| 45 +
4 files changed, 103 i
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvv.inc.c | 9 +
target/riscv/vector_helper.c| 45 +
4 files changed, 83 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 7 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 11 +++
4 files changed, 24 insertions(+)
diff --git a/target/
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 131
target/riscv/vector_helper.c| 77 ++
4 files changed, 233 insertions(
Support for VIRTIO_NET_F_RSS feature in QEMU for reference
purpose. Implements Toeplitz hash calculation for incoming
packets according to configuration provided by driver.
Changes from v1:
Changes in standard virtio_net.h moved to virtio-net.c until
standard Linux header is updated and merged to
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 128
4 files changed, 155 insertions(+)
diff --g
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 24 ++
target/riscv/vector_helper.c| 58 +
4 files changed, 94 insertions(+)
dif
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode | 20
target/riscv/insn_trans/trans_rvv.inc.c | 66
target/riscv/vector_helper.c| 130
4 files changed, 273 ins
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 37
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvv.inc.c | 33
target/riscv/vector_helper.c| 221
4 files changed, 303 insertions(+)
diff
Signed-off-by: Yuri Benditovich
---
hw/net/virtio-net.c | 95 +
1 file changed, 95 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 3627bb1717..9545b0e84f 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -71,6 +71
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 108 ++
target/riscv/vector_helper.c| 140
4 files changed, 291 inse
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvv.inc.c | 28 +
target/riscv/vector_helper.c| 40 +
4 files changed, 85 insert
Optionally report RSS feature.
Handle RSS configuration command and keep RSS parameters
in virtio-net device context.
Signed-off-by: Yuri Benditovich
---
hw/net/trace-events| 3 +
hw/net/virtio-net.c| 148 +++--
include/hw/virtio/virtio-net.h
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 37 +++
target/riscv/vector_helper.c| 40 +
4 files changed, 84 insert
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 6 +
target/riscv/vector_helper.c| 33 +
4 files changed, 56 insertions(+)
d
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.inc.c | 6 ++
target/riscv/vector_helper.c| 27 +
4 files changed, 50 insertions(+
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 11 +++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 42 +
target/riscv/vector_helper.c| 42 +
4 files changed, 10
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 228
4 files changed, 311 insertions(+)
diff -
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
target/riscv/vector_helper.c| 76 +
4 files changed, 109 insertions(+)
diff -
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22 ++
4 files changed, 33 insertions(+)
diff --git
If VIRTIO_NET_F_RSS negotiated and RSS is enabled, process
incoming packets, calculate packet's hash and place the
packet into respective RX virtqueue.
Signed-off-by: Yuri Benditovich
---
hw/net/virtio-net.c| 86 +-
include/hw/virtio/virtio-net.h | 1
Block migration for reference implementation of
RSS feature in QEMU. When we add support for RSS
on backend side, we'll implement migration of
current RSS settings.
Signed-off-by: Yuri Benditovich
---
hw/net/virtio-net.c| 18 ++
include/hw/virtio/virtio-net.h | 1 +
Le 09/03/2020 à 03:51, Jason Wang a écrit :
>
> On 2020/3/8 下午5:52, Laurent Vivier wrote:
>> Le 04/03/2020 à 04:23, Finn Thain a écrit :
>>> A portion of a recent patch got lost due to a merge snafu. That patch is
>>> now commit 88f632fbb1 ("dp8393x: Mask EOL bit from descriptor
>>> addresses").
>
Le 20/02/2020 à 17:22, Eric Blake a écrit :
> We are converting more doc files to *.rst rather than *.texi. Most
> doc files are already listed early in diffs due to our catchall
> docs/*, but a few top-level files get missed by that glob.
>
> Signed-off-by: Eric Blake
> ---
>
> Both *.texi and
Patchew URL:
https://patchew.org/QEMU/20200309083438.2389-1-yuri.benditov...@daynix.com/
Hi,
This series failed the docker-clang@ubuntu build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BE
'type/id' forgot to free in qmp_object_add, this patch fix that.
The leak stack:
Direct leak of 84 byte(s) in 6 object(s) allocated from:
#0 0x7fe2a5ebf768 in __interceptor_malloc (/lib64/libasan.so.5+0xef768)
#1 0x7fe2a505 in g_malloc (/lib64/libglib-2.0.so.0+0x52445)
#2 0x7fe2a50
Le 07/03/2020 à 11:39, Marc-André Lureau a écrit :
> Hi
>
> On Sat, Mar 7, 2020 at 3:53 AM Pan Nengyuan wrote:
>>
>> Fix a memory leak in qdev_get_gpio_out_connector().
>>
>> Reported-by: Euler Robot
>> Signed-off-by: Pan Nengyuan
>
> good catch,
> Reviewed-by: Marc-André Lureau
trivial ques
On 06.03.20 10:57, bauerchen(陈蒙蒙) wrote:
> Very sorry for my fault, in fact,I test in a old qemu version ,and patch
> generated based a new one ;
> All in all，its my fault, and I will check and test patch carefully In the
> future
> If I need to submit the patch again ?
Can you test and rev
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode pro
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
On Mon, 9 Mar 2020 at 00:56, Pan Nengyuan wrote:
>
>
>
> On 3/8/2020 9:29 PM, Peter Maydell wrote:
> > On Thu, 5 Mar 2020 at 06:39, Pan Nengyuan wrote:
> >> -/* Init VIAs 1 and 2 */
> >> -sysbus_init_child_obj(OBJECT(dev), "via1", &m->mos6522_via1,
> >> - sizeof(m
On 3/4/2020 9:37 PM, Paolo Bonzini wrote:
On 04/03/20 09:06, Zhang, Chen wrote:
Hi Eric and Paolo, Can you give some comments about this series?
No news for a while...
We already have some users(Cloud Service Provider) try to use is module in
their product.
But they also need to follow the
On 3/4/20 8:09 PM, David Hildenbrand wrote:
> On 04.03.20 12:42, Janosch Frank wrote:
>> Lets add some documentation for the Protected VM functionality.
>>
>> Signed-off-by: Janosch Frank
>> ---
>> docs/system/index.rst| 1 +
>> docs/system/protvirt.rst | 57 +
On Mon, 9 Mar 2020 17:22:12 +0800
Pan Nengyuan wrote:
> 'type/id' forgot to free in qmp_object_add, this patch fix that.
>
> The leak stack:
> Direct leak of 84 byte(s) in 6 object(s) allocated from:
> #0 0x7fe2a5ebf768 in __interceptor_malloc (/lib64/libasan.so.5+0xef768)
> #1 0x7fe2a50
On Sat, Mar 07, 2020 at 06:22:22PM +0100, Philippe Mathieu-Daudé wrote:
> Install the SASL library to build the VNC SASL auth protocol code.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/docker/dockerfiles/debian-amd64.docker | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Daniel
Suggest
scripts: Coccinelle script to use auto-propagated errp
or
scripts: Coccinelle script to use ERRP_AUTO_PROPAGATE()
Vladimir Sementsov-Ogievskiy writes:
> Script adds ERRP_AUTO_PROPAGATE macro invocation where appropriate and
> does corresponding changes in code (look for detail
On Sat, Mar 07, 2020 at 06:22:21PM +0100, Philippe Mathieu-Daudé wrote:
> The Simple Authentication and Security Layer (SASL) library
> re-defines the struct iovec on Win32 [*]. QEMU also re-defines
> it in "qemu/osdep.h". The two definitions then clash on a MinGW
> build.
> We can avoid the SASL d
The bochs-display mmio bar has some sub-regions with the actual hardware
registers. What happens when the guest access something outside those
regions depends on the archirecture. On x86 those reads succeed (and
return 0xff I think). On risc-v qemu aborts.
This patch adds handlers for the paren
On 3/9/2020 5:21 PM, Peter Maydell wrote:
> On Mon, 9 Mar 2020 at 00:56, Pan Nengyuan wrote:
>>
>>
>>
>> On 3/8/2020 9:29 PM, Peter Maydell wrote:
>>> On Thu, 5 Mar 2020 at 06:39, Pan Nengyuan wrote:
-/* Init VIAs 1 and 2 */
-sysbus_init_child_obj(OBJECT(dev), "via1", &m->mos
v5:
* re-use vu_kick_cb in libvhost-user
* keeping processing VhostUserMsg in the same coroutine until there is
detachment/attachment of AIOContext
* Spawn separate coroutine for each VuVirtqElement
* Other changes including relocating vhost-user-blk-server.c, coding
style etc.
v4:
* ad
vhost-user-blk could have played as vhost-user backend but it only supports raw
file and don't support VIRTIO_BLK_T_DISCARD and VIRTIO_BLK_T_WRITE_ZEROES
operations on raw file (ioctl(fd, BLKDISCARD) is only valid for real
block device).
Kevin's qemu-storage-daemon will be used to replace this
too
On Fri, 6 Mar 2020 03:50:14 -0500
Christian Borntraeger wrote:
> Guests with mem-prealloc do fail with
> qemu-system-s390x: /home/cborntra/REPOS/qemu/util/qemu-thread-posix.c:76:
> qemu_mutex_lock_impl: Assertion `mutex->initialized' failed.
> qemu-system-s390x: /home/cborntra/REPOS/qemu/util/q
By making use of libvhost, multiple block device drives can be exported
and each drive can serve multiple clients simultaneously.
Since vhost-user-server needs a block drive to be created first, delay
the creation of this object.
Signed-off-by: Coiby Xu
---
block/Makefile.objs |
Allow vu_message_read to be replaced by one which will make use of the
QIOChannel functions. Thus reading vhost-user message won't stall the
guest.
Remove watch for kick fd in vu_deinit. When QEMU as vhost-user client
process is restarted in gdb, QEMU as vhost-user-server will still dispatch
the e
This test case has the same tests as tests/virtio-blk-test.c except for
tests have block_resize.
Signed-off-by: Coiby Xu
---
tests/Makefile.include | 3 +-
tests/qtest/Makefile.include| 2 +
tests/qtest/libqos/vhost-user-blk.c | 126 +
tests/qtest/libqos/vhost-user-b
Sharing QEMU devices via vhost-user protocol
Signed-off-by: Coiby Xu
---
util/Makefile.objs | 3 +
util/vhost-user-server.c | 360 +++
util/vhost-user-server.h | 57 ++
3 files changed, 420 insertions(+)
create mode 100644 util/vhost-user-server.
On 09/03/20 11:03, Igor Mammedov wrote:
>> +qemu_cond_init(&page_cond);
>> +qemu_mutex_init(&page_mutex);
> Is it possible for touch_all_pages to be called several times?
> If it's then it probably needs a guard against that to make
> sure it won't explode, something like:
>
> static bool
Cc'ing Kevin in the hope of a review.
Pan Nengyuan writes:
> 'type/id' forgot to free in qmp_object_add, this patch fix that.
>
> The leak stack:
> Direct leak of 84 byte(s) in 6 object(s) allocated from:
> #0 0x7fe2a5ebf768 in __interceptor_malloc (/lib64/libasan.so.5+0xef768)
> #1 0x7f
On Mon, 9 Mar 2020 at 10:02, Pan Nengyuan wrote:
> On 3/9/2020 5:21 PM, Peter Maydell wrote:
> > Could you explain more? My thought is that we should be using
> > sysbus_init_child_obj() and we should be doing it in the init method.
> > Why does that break the tests ? It's the same thing various o
On Fri, Mar 06, 2020 at 09:09:17AM -0500, Jason Andryuk wrote:
> Currently usb-serial devices are unable to send data into guests with
> the xhci controller. Data is copied into the usb-serial's buffer, but
> it is not sent into the guest. Data coming out of the guest works
> properly. usb-seria
On Wed, Feb 26, 2020 at 04:46:46PM +0800, kuhn.chen...@huawei.com wrote:
> From: Chen Qun
>
> The "again" assignment is meaningless before g_assert_not_reached.
> In addition, the break statements no longer needs to be after
> g_assert_not_reached.
>
> Clang static code analyzer show warning:
>
On Mon, Mar 09, 2020 at 10:51:45AM +0100, Igor Mammedov wrote:
> On Mon, 9 Mar 2020 17:22:12 +0800
> Pan Nengyuan wrote:
>
> > 'type/id' forgot to free in qmp_object_add, this patch fix that.
> >
> > The leak stack:
> > Direct leak of 84 byte(s) in 6 object(s) allocated from:
> > #0 0x7fe2a5
On 3/9/2020 5:51 PM, Igor Mammedov wrote:
> On Mon, 9 Mar 2020 17:22:12 +0800
> Pan Nengyuan wrote:
>
>> 'type/id' forgot to free in qmp_object_add, this patch fix that.
>>
>> The leak stack:
>> Direct leak of 84 byte(s) in 6 object(s) allocated from:
>> #0 0x7fe2a5ebf768 in __interceptor_
On 3/9/2020 6:15 PM, Daniel P. Berrangé wrote:
> On Mon, Mar 09, 2020 at 10:51:45AM +0100, Igor Mammedov wrote:
>> On Mon, 9 Mar 2020 17:22:12 +0800
>> Pan Nengyuan wrote:
>>
>>> 'type/id' forgot to free in qmp_object_add, this patch fix that.
>>>
>>> The leak stack:
>>> Direct leak of 84 byte(
Compute the power of 2 order of a size. Use it in
page_memalign. Other users are looming.
Signed-off-by: Eric Auger
---
lib/alloc_page.c | 7 ++-
lib/alloc_page.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/lib/alloc_page.c b/lib/alloc_page.c
index ed23638..7c8461a 1
This series is a revival of an RFC series sent in Dec 2016 [1].
Given the amount of code and the lack of traction at that time,
I haven't respinned until now. However a recent bug found related
to the ITS migration convinced me that this work may deserve to be
respinned and enhanced.
Tests exercis
Introduce additional SZ_256, SZ_8K, SZ_16K macros that will
be used by ITS tests.
Signed-off-by: Eric Auger
Reviewed-by: Thomas Huth
---
lib/libcflat.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index ea19f61..7092af2 100644
--- a/lib/libcflat.h
+++ b
Add two new migration tests. One testing the migration of
a topology where collection were unmapped. The second test
checks the migration of the pending table.
Signed-off-by: Eric Auger
---
v3 -> v4:
- do not talk about odd/even CPUs, use pe0 and pe1
- comment the delay
v2 -> v3:
- tests belon
ipi_enable() code would be reusable for other interrupts
than IPI. Let's rename it setup_irq() and pass an interrupt
handler pointer.
Signed-off-by: Eric Auger
---
v2 -> v3:
- do not export setup_irq anymore
---
arm/gic.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions
Allocate the LPI configuration and per re-distributor pending table.
Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled
by default in the config table.
Also introduce a helper routine that allows to set the pending table
bit for a given LPI.
Signed-off-by: Eric Auger
---
v2 -> v
Introduce an helper functions to register
- a new device, characterized by its device id and the
max number of event IDs that dimension its ITT (Interrupt
Translation Table). The function allocates the ITT.
- a new collection, characterized by its ID and the
target processing engine (PE).
Implement main ITS commands. The code is largely inherited from
the ITS driver.
Signed-off-by: Eric Auger
---
v3 -> v4:
- device's itt now is a VGA
- pass verbose to choose whether we shall print the cmd
- use printf instead of report_info
v2 -> v3:
- do not use report() anymore
- assert if cm
PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management.
Signed-off-by: Eric Auger
Reviewed-by: Zenghui Yu
---
v3 -> v4:
- replace some spaces by tabs and added Zenghui's R-b
---
lib/arm/asm/gic-v3.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/arm/asm/gic-v3.h b/li
This test maps LPIs (populates the device table, the collection table,
interrupt translation tables, configuration table), migrates and make
sure the translation is correct on the destination.
Signed-off-by: Eric Auger
---
v3 -> v4:
- assert in its_get_device/collection if the id is not found
-
Detect the presence of an ITS as part of the GICv3 init
routine, initialize its base address and read few registers
the IIDR, the TYPER to store its dimensioning parameters.
Parse the BASER registers. As part of the init sequence we
also init all the requested tables.
This is our first ITS test, b
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