HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for packet semantics
store buffer (masked stores and scatter/gather)
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h |
Philippe Mathieu-Daudé writes:
> On 2/28/20 7:56 AM, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
>>> On 2/27/20 3:55 PM, Philippe Mathieu-Daudé wrote:
On 2/27/20 3:52 PM, Markus Armbruster wrote:
> Philippe Mathieu-Daudé writes:
>
>> This fixes when adding a 'Sin
Lists the register and immediate operands for each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 86 +++
1 file changed, 86 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index 499f0e0..0c7
Implementation of Linux user emulation for RISC-V
Some common files modified in addition to new files in linux-user/hexagon
Signed-off-by: Taylor Simpson
---
linux-user/hexagon/sockbits.h | 18 ++
linux-user/hexagon/syscall_nr.h | 346
linux-user/h
Signed-off-by: Taylor Simpson
---
target/hexagon/Makefile.objs | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/Makefile.objs b/target/hexagon/Makefile.objs
index be0d08f..d18b41f 100644
--- a/target/hexagon/Makefile.objs
+++ b/target/hexagon/Makefil
On 2/28/20 8:22 AM, Peter Maydell wrote:
>> +if (ri->state == ARM_CP_STATE_AA32) {
>> +/*
>> + * Writes from aarch32 mode have more RES0 bits.
>> + * This includes TDZ, RW, E2H, and more.
>> + */
>> +valid_mask &= ~0xff80ff8c9000ull;
>> +}
>
> Is
Philippe Mathieu-Daudé writes:
> On 2/28/20 10:50 AM, Philippe Mathieu-Daudé wrote:
[...]
>> Thanks for your review. I'll drop the changes in util/oslib-win32.c
>> for for now, and add a note in my TODO for after the 5.0 release.
>
> Well if I follow this line, I'v to drop the changes in util/osd
Public bug reported:
Hi,
I run qemu in an xterm terminal, with TERM=vt100. My keyboard is french AZERTY.
sudo ./qemu-system-hppa -monitor /dev/pts/2 -k fr -boot d -drive
if=scsi,bus=0,index=5,file=../../hpux_11iv1.img,format=raw -serial
mon:stdio -D qemu1.log -nographic -m 512 -d nochain -cdrom
On Fri, 28 Feb 2020 at 16:57, Richard Henderson
wrote:
>
> On 2/28/20 8:22 AM, Peter Maydell wrote:
> >> +if (ri->state == ARM_CP_STATE_AA32) {
> >> +/*
> >> + * Writes from aarch32 mode have more RES0 bits.
> >> + * This includes TDZ, RW, E2H, and more.
> >> +
On 2/28/20 9:49 AM, Auger Eric wrote:
Hi Stefan,
On 2/28/20 3:37 PM, Stefan Berger wrote:
On 2/27/20 3:07 AM, Auger Eric wrote:
Hi Stefan,
On 2/26/20 11:44 PM, Stefan Berger wrote:
On 2/26/20 3:59 PM, Eric Auger wrote:
This series adds the capability to instantiate an MMIO TPM TIS
in ARM virt
On Thu, Feb 27, 2020 at 05:18:30PM +, Stefan Hajnoczi wrote:
> On Mon, Feb 24, 2020 at 03:55:39PM -0500, Jagannathan Raman wrote:
> > From: Elena Ufimtseva
> >
> > Validate the incoming commands to confirm that they would not cause any
> > errors in the remote process.
> >
> > Signed-off-by:
anquintela/tags/pull-migration-pull-request' into staging
> (2020-02-28 14:02:31 +)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20200228
>
> for you to fetch changes up to 1904f9b5f1d94fe12
On 28.02.20 17:49, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-
>> From: David Hildenbrand [mailto:da...@redhat.com]
>> Sent: 13 February 2020 17:09
>> To: Shameerali Kolothum Thodi ;
>> Igor Mammedov
>> Cc: peter.mayd...@linaro.org; xiaoguangrong.e...@gmail.com;
>> m...@re
In an xterm to switch to/from QEMU monitor use "Ctrl-A c"
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1865188
Title:
Switching from the monitor to the emulated machine with a French
keyboard (A
Hi Stefan -- I meant to cc you on these but forgot, relating to the
"qemu.nsi needs updating to know that it should install
Sphinx documentation these days" part...
On Fri, 28 Feb 2020 at 15:36, Peter Maydell wrote:
>
> Hi; this series does a complete conversion of qemu-doc from
> Texinfo to rST,
On Thu, Feb 27, 2020 at 04:58:04PM +, Stefan Hajnoczi wrote:
> On Mon, Feb 24, 2020 at 03:55:41PM -0500, Jagannathan Raman wrote:
> > From: Elena Ufimtseva
> >
> > Signed-off-by: Elena Ufimtseva
> > Signed-off-by: Jagannathan Raman
> > Signed-off-by: John G Johnson
> > ---
> > docs/qemu-m
Sorry Peter, I missed the email.
Reviewed-by: Edgar E. Iglesias
Best regards,
Edgar
On Fri, 28 Feb. 2020, 10:00 Peter Maydell, wrote:
> On Thu, 20 Feb 2020 at 15:05, Peter Maydell
> wrote:
> >
> > On Sat, 15 Feb 2020 at 12:23, Guenter Roeck wrote:
> > >
> > > USB ports on Xilinx Zync must
On Thu, Feb 27, 2020 at 05:11:40PM +, Stefan Hajnoczi wrote:
> On Mon, Feb 24, 2020 at 03:55:40PM -0500, Jagannathan Raman wrote:
> > From: John G Johnson
> >
> > Signed-off-by: John G Johnson
> > Signed-off-by: Elena Ufimtseva
> > Signed-off-by: Jagannathan Raman
> > ---
> > docs/devel/i
On 2/28/20 1:19 AM, LIU Zhiwei wrote:
>>> +#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ETYPE, MTYPE, H, DO_OP, SUF) \
>>> +static void vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
>>> + uint32_t wd, uint32_t idx, CPURISCVState *env, uintptr_t retaddr)\
>>> +{
On 2/28/20 9:34 AM, Peter Maydell wrote:
> One of us is miscounting, and I don't *think* it's me...
>
> bits 63..0: ff80ff8c9000
> bits 63..32: ff80ff8c
> bits 64..48: ff80
>
> bit 48 looks like it's 0 to me.
Oops, yes, it's me.
> You could refine the valid mask as the & of the bits which
On Fri, 28 Feb 2020 at 18:55, Richard Henderson
wrote:
>
> On 2/28/20 9:34 AM, Peter Maydell wrote:
> > You could refine the valid mask as the & of the bits which we
> > do want to exist in aarch32, rather than &~ of the reserved bits:
> >
> > valid_mask &= TTLBIS | TOCU | TICAB | ...
> >
> > ?
>
Igor Mammedov writes:
> On Thu, 27 Feb 2020 20:07:24 +0100
> Niek Linnenbank wrote:
>
>> Hi Richard,
>>
>> On Thu, Feb 27, 2020 at 1:57 PM Richard Henderson <
>> richard.hender...@linaro.org> wrote:
>>
>> > On 2/27/20 4:31 AM, Alex Bennée wrote:
>> > >> It does not make sense for a linux
Hi,
A few tweaks to the final commit so we are a little less greedy for
translation buffer, especially for the CONFIG_USER case. Otherwise
I've applied the review tags.
Alex Bennée (4):
accel/tcg: use units.h for defining code gen buffer sizes
accel/tcg: remove link between guest ram and TCG
There is no particular reason to use a static codegen buffer on 64 bit
hosts as we have address space to burn. Allow the common CONFIG_USER
case to use the mmap'ed buffers like SoftMMU.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Phil
It's easier to read.
Signed-off-by: Alex Bennée
Reviewed-by: Niek Linnenbank
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
accel/tcg/translate-all.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --g
Basing the TB cache size on the ram_size was always a little heuristic
and was broken by a1b18df9a4 which caused ram_size not to be fully
realised at the time we initialise the TCG translation cache.
The current DEFAULT_CODE_GEN_BUFFER_SIZE may still be a little small
but follow-up patches will ad
While 32mb is certainly usable a full system boot ends up flushing the
codegen buffer nearly 100 times. Increase the default on 64 bit hosts
to take advantage of all that spare memory. After this change I can
boot my tests system without any TB flushes.
As we usually run more CONFIG_USER binaries
On Thu, Feb 27, 2020 at 11:12:02AM +0100, David Hildenbrand wrote:
> Let's implement ram_block_resized(), allowing resizeable mappings.
>
> For resizeable mappings, we reserve $max_size IOVA address space, but only
> map $size of it. When resizing, unmap the old part and remap the new
> part. We'l
On Thu, Feb 27, 2020 at 11:11:57AM +0100, David Hildenbrand wrote:
> Let's factor out calculating the size of the guard page and rename the
> variable to make it clearer that this pagesize only applies to the
> guard page.
>
> Cc: "Michael S. Tsirkin"
> Cc: Murilo Opsfelder Araujo
> Cc: Greg Kur
On Thu, Feb 27, 2020 at 11:12:01AM +0100, David Hildenbrand wrote:
> Implement resizeable mmaps. For now, the actual resizing is not wired up.
> Introduce qemu_ram_mmap_resizeable() and qemu_ram_mmap_resize(). Make
> qemu_ram_mmap() a wrapper of qemu_ram_mmap_resizeable().
>
> Cc: Richard Henderso
On Thu, Feb 27, 2020 at 11:12:02AM +0100, David Hildenbrand wrote:
> +static void qemu_vfio_dma_map_resize(QEMUVFIOState *s, void *host,
> + size_t old_size, size_t new_size)
> +{
> +IOVAMapping *m;
> +int index = 0;
> +
> +qemu_mutex_lock(&s->lock);
On Thu, Feb 27, 2020 at 11:12:03AM +0100, David Hildenbrand wrote:
> Introduce qemu_anon_ram_alloc_resizeable() and qemu_anon_ram_resize().
> Implement them under POSIX and make them return NULL under WIN32.
>
> Under POSIX, we make use of resizeable mmaps. An implementation under
> WIN32 is theor
On Thu, Feb 27, 2020 at 11:12:04AM +0100, David Hildenbrand wrote:
> We want to actually use resizeable allocations in resizeable ram blocks
> (IOW, make everything between used_length and max_length inaccessible) -
> however, not all ram block notifiers can support that.
>
> Introduce a way to de
> Am 28.02.2020 um 20:43 schrieb Peter Xu :
>
> On Thu, Feb 27, 2020 at 11:12:02AM +0100, David Hildenbrand wrote:
>> Let's implement ram_block_resized(), allowing resizeable mappings.
>>
>> For resizeable mappings, we reserve $max_size IOVA address space, but only
>> map $size of it. When re
On Fri, Feb 28, 2020 at 8:24 PM Alex Bennée wrote:
> Basing the TB cache size on the ram_size was always a little heuristic
> and was broken by a1b18df9a4 which caused ram_size not to be fully
> realised at the time we initialise the TCG translation cache.
>
> The current DEFAULT_CODE_GEN_BUFFER_
On Fri, Feb 28, 2020 at 8:24 PM Alex Bennée wrote:
> While 32mb is certainly usable a full system boot ends up flushing the
> codegen buffer nearly 100 times. Increase the default on 64 bit hosts
> to take advantage of all that spare memory. After this change I can
> boot my tests system without
> Am 28.02.2020 um 20:55 schrieb Peter Xu :
>
> On Thu, Feb 27, 2020 at 11:12:02AM +0100, David Hildenbrand wrote:
>> +static void qemu_vfio_dma_map_resize(QEMUVFIOState *s, void *host,
>> + size_t old_size, size_t new_size)
>> +{
>> +IOVAMapping *m;
>> +
On Thu, Feb 27, 2020 at 11:12:05AM +0100, David Hildenbrand wrote:
[...]
> +static void ram_block_alloc_ram(RAMBlock *rb)
> +{
> +const bool shared = qemu_ram_is_shared(rb);
> +
> +/*
> + * If we can, try to allocate actually resizeable ram. Will also fail
> + * if qemu_anon_ram_a
On Fri, Feb 28, 2020 at 03:19:45PM -0500, David Hildenbrand wrote:
>
>
> > Am 28.02.2020 um 20:55 schrieb Peter Xu :
> >
> > On Thu, Feb 27, 2020 at 11:12:02AM +0100, David Hildenbrand wrote:
> >> +static void qemu_vfio_dma_map_resize(QEMUVFIOState *s, void *host,
> >> +
> Am 28.02.2020 um 21:49 schrieb Peter Xu :
>
> On Fri, Feb 28, 2020 at 03:19:45PM -0500, David Hildenbrand wrote:
>>
>>
Am 28.02.2020 um 20:55 schrieb Peter Xu :
>>>
>>> On Thu, Feb 27, 2020 at 11:12:02AM +0100, David Hildenbrand wrote:
+static void qemu_vfio_dma_map_resize(QEMU
On Fri, Feb 28, 2020 at 09:16:28PM +0100, David Hildenbrand wrote:
>
[...]
> >> @@ -631,7 +658,7 @@ int qemu_vfio_dma_map(QEMUVFIOState *s, void *host,
> >> size_t size,
> >> qemu_vfio_remove_mapping(s, mapping);
> >> goto out;
> >> }
> >> -
> -Original Message-
> From: Paolo Bonzini
> Sent: Friday, February 28, 2020 2:45 AM
> To: Sunil Muthuswamy ; Richard Henderson
> ; Eduardo Habkost
>
> Cc: qemu-devel@nongnu.org; Stefan Weil
> Subject: [EXTERNAL] Re: PATCH] WHPX: TSC get and set should be dependent on
> VM state
>
> O
From: Philippe Mathieu-Daudé
It would be confusing to have multiple default machines.
Abort if this ever occurs.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20200207161948.15972-4-phi...@redhat.com>
Reviewed-by: Marc-André Lureau
Signed-off-by: Eduardo Habkost
Reviewed-by: Laurent Vivi
From: Philippe Mathieu-Daudé
There is no declaration of the 'NMI' type. INTERFACE_CHECK()
returns an abstract type (see commit aa1b35b975d8). The abstract
type corresponding to the TYPE_NMI interface is 'NMIState'.
Fixes: 9cb805fd267
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <2019120709
The following changes since commit e0175b71638cf4398903c0d25f93fe62e0606389:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200228'
into staging (2020-02-28 16:39:27 +)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/ma
From: Philippe Mathieu-Daudé
The MachineClass is already zeroed on creation.
Note: The code setting is_default=0 in hw/i386/pc_piix.c is
different (related to compat options). When adding a
new versioned machine, we want it to be the new default,
so we have to mark the previous
From: Philippe Mathieu-Daudé
There's no good reason for it to be type int, change it to bool.
Suggested-by: Richard Henderson
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20200207161948.15972-3-phi...@redhat.com>
Reviewed-by: Marc-André Lureau
Reviewed-b
Am 28.02.20 um 19:36 schrieb Peter Maydell:
> Hi Stefan -- I meant to cc you on these but forgot, relating to the
> "qemu.nsi needs updating to know that it should install
> Sphinx documentation these days" part...
>
> On Fri, 28 Feb 2020 at 15:36, Peter Maydell wrote:
[...]
>> A couple of notes:
On Wed, Feb 12, 2020 at 04:13:26PM +0800, Tao Xu wrote:
> Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
> CPU model to remove MONITOR/MWAIT feature.
>
> After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
> (commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd)
On Wed, Feb 12, 2020 at 04:13:25PM +0800, Tao Xu wrote:
> Because MPX is being removed from the linux kernel, remove MPX feature
> from Denverton.
>
> Signed-off-by: Tao Xu
Queued, thanks!
--
Eduardo
On Wed, Feb 12, 2020 at 04:13:27PM +0800, Tao Xu wrote:
> Add additional information for -cpu help to indicate the changes in this
> version of CPU model.
>
> Suggested-by: Eduardo Habkost
> Signed-off-by: Tao Xu
Queued, thanks!
--
Eduardo
On Wed, Feb 12, 2020 at 04:13:28PM +0800, Tao Xu wrote:
> Add which features are added or removed in this version. Remove the
> changed model-id in versioned CPU models, to keep the model name
> unchanged at /proc/cpuinfo inside the VM.
>
> Signed-off-by: Tao Xu
> ---
>
> Changes in v2:
> -
On Wed, 19 Feb 2020, BALATON Zoltan wrote:
On Wed, 19 Feb 2020, BALATON Zoltan wrote:
faster or doing something differently? Does someone know what interrupts
are generated on real hardware in DMA mode so we can compare that to what
we see with QEMU?
The document Programming Interface for Bus
On 2/28/20 11:03 AM, Peter Maydell wrote:
> It occurs to me that we should check what the required
> semantics are for the opposite half of the register
> if the guest writes to one half of it via hcr_writehigh()
> or hcr_writelow() -- is the un-accessed half supposed
> to stay exactly as it is, or
On Fri, Feb 28, 2020 at 12:44:19PM -0600, Edgar E. Iglesias wrote:
> Sorry Peter, I missed the email.
>
> Reviewed-by: Edgar E. Iglesias
>
Thanks a lot everyone!
Guenter
> Best regards,
> Edgar
>
>
> On Fri, 28 Feb. 2020, 10:00 Peter Maydell, wrote:
>
> > On Thu, 20 Feb 2020 at 15:05, Pet
Hi Igor,
On 2020/2/28 17:39, Igor Mammedov wrote:
On Thu, 27 Feb 2020 17:12:21 +0800
Heyi Guo wrote:
On 2020/2/25 17:24, Philippe Mathieu-Daudé wrote:
On 2/25/20 8:50 AM, Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present
I also discovered just a few days ago the problem that sparse VHD/VHDX
image files are not being accepted by Windows.
It appears that qemu-img on Windows always tries to create images as
sparse files. Only in some cases (e.g. when operating on a NTFS file
system) will the file actually be a sparse
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0b84742b66..0ae07a72e4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1410,6 +1410,7 @@ static inline void xpsr_write(CPUARMState *e
Changes for v5:
* Patch 1 was broken for aa32. Not just the masking vs the "other"
32-bit register that Peter noticed, but more explicitly in that
"ri" was dereferenced as NULL -- hcr_write{high,low} did not pass
along the structure. Oops.
Break out a new helper that is passed
We have disabled EL2 and EL3 for user-only, which means that these
registers "don't exist" and should not be set.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 33c28fe868..af541431e6 100644
Update the {TGE,E2H} == '11' masking to ARMv8.6.
If EL2 is configured for aarch32, disable all of
the bits that are RES0 in aarch32 mode.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 31 +++
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/
Don't merely start with v8.0, handle v7VE as well. Ensure that writes
from aarch32 mode do not change bits in the other half of the register.
Protect reads of aa64 id registers with ARM_FEATURE_AARCH64.
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 38 +
This bit traps EL1 access to cache maintenance insns that operate
to the point of unification. There are no longer any references to
plain aa64_cacheop_access, so remove it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Fix el0 fallthru (pmm).
---
target/arm/helper.c | 53
These bits trap EL1 access to various virtual memory controls.
Buglink: https://bugs.launchpad.net/bugs/1855072
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Include TTBCR.
v3: Include not_v8_cp_reginfo, lpae_cp_reginfo, CONTEXTIDR_S;
exclude not_v7_cp_reginfo (pmm).
--
In arm_cpu_reset, we configure many system registers so that user-only
behaves as it should with a minimum of ifdefs. However, we do not set
all of the system registers as required for a cpu with EL2 and EL3.
Disabling EL2 and EL3 mean that we will not look at those registers,
which means that we
This bit traps EL1 access to cache maintenance insns that operate
to the point of coherency or persistence.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Fix el0 fallthru (pmm).
---
target/arm/helper.c | 39 +++
1 file changed, 31 insert
These bits trap EL1 access to set/way cache maintenance insns.
Buglink: https://bugs.launchpad.net/bugs/1863685
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/
This bit traps EL1 access to the auxiliary control registers.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ddef3d7dc3..2
Make the output just a bit prettier when running by hand.
Cc: Alex Bennée
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/pauth-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/tcg/aarch64/pauth-1.c b/tests/tcg/aarch64/pauth-1.c
index ea0984ea82..d3878cbeb6 1
This bit traps EL1 access to tlb maintenance insns.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 85 +
1 file changed, 55 insertions(+), 30 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
i
On 2/28/20 11:24 AM, Alex Bennée wrote:
> Hi,
>
> A few tweaks to the final commit so we are a little less greedy for
> translation buffer, especially for the CONFIG_USER case. Otherwise
> I've applied the review tags.
>
> Alex Bennée (4):
> accel/tcg: use units.h for defining code gen buffer s
On Fri, Feb 21, 2020 at 12:29 PM Lirong Yuan wrote:
>
> This change adds the support for AT_EXECFN and AT_EXECFD auxval.
>
> Signed-off-by: Lirong Yuan
> ---
> linux-user/elfload.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/linux-user/elfload.c b/linux
On Fri, Feb 21, 2020 at 5:09 PM Lirong Yuan wrote:
>
> This change allows us to set custom base address for guest programs. It is
> needed to allow qemu to work with Thread Sanitizer (TSan), which has specific
> boundary definitions for memory mappings on different platforms:
> https://github.co
On 2/27/20 6:24 PM, Robert Hoo wrote:
> If it is enabled, config-host.mak will have CONFIG_AVX512F_OPT defined.
>
> AVX512F instruction set is available since Intel Skylake, and can be enabled
> in
> compiling with -mavx512f.
> More info:
> https://software.intel.com/sites/default/files/managed/c
On 2/27/20 6:24 PM, Robert Hoo wrote:
> if ((bv & 6) == 6 && (b & bit_AVX2)) {
> cache |= CACHE_AVX2;
> }
> +if ((bv & 6) == 6 && (b & bit_AVX512F)) {
> +cache |= CACHE_AVX512F;
> +}
Oh, one more thing I missed -- w
>-Original Message-
>From: Kevin Wolf [mailto:kw...@redhat.com]
>Sent: Friday, February 28, 2020 6:55 PM
>To: Chenqun (kuhn)
>Cc: qemu-devel@nongnu.org; qemu-triv...@nongnu.org;
>peter.mayd...@linaro.org; Zhanghailiang ;
>Euler Robot ; Ronnie Sahlberg
>; Paolo Bonzini ; Peter
>Lieven ; Max
From: Alex Bennée
The bug describes a race whereby cpu_exec_step_atomic can acquire a TB
which is invalidated by a tb_flush before we execute it. This doesn't
affect the other cpu_exec modes as a tb_flush by it's nature can only
occur on a quiescent system. The race was described as:
B2. tcg_c
The following changes since commit e0175b71638cf4398903c0d25f93fe62e0606389:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200228'
into staging (2020-02-28 16:39:27 +)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tag
From: Alex Bennée
While 32mb is certainly usable a full system boot ends up flushing the
codegen buffer nearly 100 times. Increase the default on 64 bit hosts
to take advantage of all that spare memory. After this change I can
boot my tests system without any TB flushes.
As we usually run more C
From: Richard Henderson
We will shortly use this function from tcg_out_op as well.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.
From: Alex Bennée
There is no particular reason to use a static codegen buffer on 64 bit
hosts as we have address space to burn. Allow the common CONFIG_USER
case to use the mmap'ed buffers like SoftMMU.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Da
From: Alex Bennée
Basing the TB cache size on the ram_size was always a little heuristic
and was broken by a1b18df9a4 which caused ram_size not to be fully
realised at the time we initialise the TCG translation cache.
The current DEFAULT_CODE_GEN_BUFFER_SIZE may still be a little small
but follo
From: Alex Bennée
It's easier to read.
Signed-off-by: Alex Bennée
Reviewed-by: Niek Linnenbank
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20200228192415.19867-2-alex.ben...@linaro.org>
Signed-off-by: Richard Henderson
-
From: Zenghui Yu
Our robot reported the following compile-time warning while compiling
Qemu with -fno-inline cflags:
In function 'load_memop',
inlined from 'load_helper' at /qemu/accel/tcg/cputlb.c:1578:20,
inlined from 'full_ldub_mmu' at /qemu/accel/tcg/cputlb.c:1624:12:
/qemu/accel/tcg
From: Richard Henderson
It is, after all, just two instructions.
Profiling on a cortex-a15, using -d nochain to increase the number
of exit_tb that are executed, shows a minor improvement of 0.5%.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 12 ++--
1 file changed,
On Fri, 2020-02-28 at 18:09 -0800, Richard Henderson wrote:
> On 2/27/20 6:24 PM, Robert Hoo wrote:
> > if ((bv & 6) == 6 && (b & bit_AVX2)) {
> > cache |= CACHE_AVX2;
> > }
> > +if ((bv & 6) == 6 && (b & bit_AVX512F)) {
> > +ca
On 2/25/20 4:15 AM, Laurent Vivier wrote:
> This will be used when we'll import syscall.tbl from the kernel
>
> Add a script to remove all the dependencies to syscall_nr.h
> that point to source directory and not to the build directory.
> The list of arch will be update while the generated files a
On 2/25/20 4:15 AM, Laurent Vivier wrote:
> Copy syscall.tbl and syscallhdr.sh from linux/arch/alpha/kernel/syscalls v5.5
> Update syscallhdr.sh to generate QEMU syscall_nr.h
>
> Signed-off-by: Laurent Vivier
> ---
> configure | 3 +-
> linux-user/Makefile.objs | 2
On 2/25/20 4:15 AM, Laurent Vivier wrote:
>hppa)
> mttcg="yes"
> +TARGET_SYSTBL_ABI=common,64
We only support hppa32. We don't even emulate a 64-bit cpu.
Of course... I wasn't even aware that linux had any support for a 64-bit
userland for hppa, which was one of the reasons why I h
Public bug reported:
For a better out of the box user experience on the Windows platform it
would be nice if a QEMU GUI would be by installed by the same QEMU
installer. Currently it is required to first install QEMU and then
install a QEMU GUI.
I don't know all QEMU GUIs but looks like Virt Mana
Public bug reported:
Please consider providing a QEMU Windows portable [1] [2] [3] version on
official qemu.org.
Reasons:
* This would improve usability, the out of the box user experience of laymen
(non-technical) users.
* Linux distributions could add the QEMU Windows portable to their instal
On Fri, Feb 28, 2020 at 01:39:02PM +0100, Cédric Le Goater wrote:
> On 2/28/20 1:33 PM, Philippe Mathieu-Daudé wrote:
> > Signed-off-by: Philippe Mathieu-Daudé
>
> Reviewed-by: Cédric Le Goater
Applied to ppc-for-5.0, thanks.
>
> Thnaks,
>
> C.
>
>
> > ---
> > hw/ppc/pnv_lpc.c | 2 +-
> >
On 27.02.2020 13:09, Vladimir Sementsov-Ogievskiy wrote:
27.02.2020 13:04, Vladimir Sementsov-Ogievskiy wrote:
27.02.2020 10:29, Denis Plotnikov wrote:
Affected tests: 049, 060, 061, 065, 144, 182, 242, 255
After adding the compression type feature for qcow2, the compression
type
is repor
On 27.02.2020 13:29, Vladimir Sementsov-Ogievskiy wrote:
27.02.2020 10:29, Denis Plotnikov wrote:
The test checks fulfilling qcow2 requiriements for the compression
type feature and zstd compression type operability.
Signed-off-by: Denis Plotnikov
---
tests/qemu-iotests/287 | 123
28.02.2020 11:23, Denis Plotnikov wrote:
On 27.02.2020 13:29, Vladimir Sementsov-Ogievskiy wrote:
27.02.2020 10:29, Denis Plotnikov wrote:
The test checks fulfilling qcow2 requiriements for the compression
type feature and zstd compression type operability.
Signed-off-by: Denis Plotnikov
--
On 27.02.2020 16:48, Eric Blake wrote:
On 2/27/20 1:29 AM, Denis Plotnikov wrote:
The patch adds some preparation parts for incompatible compression type
feature to Qcow2 that indicates which allow to use different compression
to qcow2, allowing the use of different
methods for image clus
Aleksandar Markovic wrote:
> On Thursday, February 27, 2020, Juan Quintela wrote:
>
> Marc-André Lureau wrote:
> > Hi Juan
> >
> > On Wed, Jan 8, 2020 at 2:08 PM Juan Quintela wrote:
> >>
> >> Marc-André Lureau wrote:
> >> n> Check the host pointer is correctly aligned, otherwise we may
Hi Maz,
thanks for the information!
The situation we're in is where we are suspecting the file locking on a
shared network file system to be broken, so we were looking for ways to
avoid any locking. I had tried some variations on your image-opts style
invocation, but did not find any variant wher
On 2020/2/28 13:38, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+if (s->sew < 2) {
+return false;
+}
This could just as easily be in amo_check?
Yes, it can be done in amo_check.
+
+if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+#ifdef CONFIG_ATOMIC64
+
So we don't have to compile everything in, or have ifdefs
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
---
include/qemu/module.h | 2 ++
softmmu/vl.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/include/qemu/module.h b/include/qemu/module.h
index 684753d808
201 - 300 of 350 matches
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