On Tue, 25 Feb 2020 at 18:08, Richard Henderson
wrote:
>
> This bit traps EL1 access to cache maintenance insns that operate
> to the point of unification. There are no longer any references to
> plain aa64_cacheop_access, so remove it.
>
> Signed-off-by: Richard Henderson
> ---
> v4: Fix el0 fa
On Tue, 25 Feb 2020 at 18:08, Richard Henderson
wrote:
>
> This bit traps EL1 access to cache maintenance insns that operate
> to the point of coherency or persistence.
>
> Signed-off-by: Richard Henderson
> ---
> v4: Fix el0 fallthru (pmm).
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 25 Feb 2020 at 18:08, Richard Henderson
wrote:
>
> This bit traps EL1 access to tlb maintenance insns.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
From: Gavin Shan
This uses TYPE_PL011 when creating the serial port so that the code
looks cleaner.
Signed-off-by: Gavin Shan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 2020022423.4128-1-gs...@redhat.com
Signed-off-by: Peter Maydell
---
hw/arm/sbsa-ref
From: Sai Pavan Boddu
The GICv2 allows the implementation to implement a variable number
of priority bits; unimplemented bits in the priority registers
are read as zeros, writes ignored. We were previously always
implementing a full 8 bits of priority, which is allowed but not
what the real hardw
ble in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20200228
for you to fetch changes up to 1904f9b5f1d94fe12fe021db6b504c87d684f6db:
hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 (2020-02-28
From: Richard Henderson
We will shortly use these to test for VFPv2 and VFPv3
in different situations.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 18 ++
From: Richard Henderson
We had set this for aarch32-only in arm_max_initfn, but
failed to set the same bit for aarch64.
Signed-off-by: Richard Henderson
Message-id: 20200218190958.745-2-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/cpu64.
From: Richard Henderson
Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 2020022422
From: Philippe Mathieu-Daudé
The Linux kernel displays errors why trying to detect the PL041
audio interface:
Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro
GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TE
From: Richard Henderson
Shuffle the order of the checks so that we test the ISA
before we test anything else, such as the register arguments.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
From: Sai Pavan Boddu
All A9 CPUs have a GIC with 5 bits of priority.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Peter Maydell
Message-id: 1582537164-764-3-git-send-email-sai.pavan.bo...@xilinx.com
Suggested-by: Peter Maydell
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/
From: Richard Henderson
All remaining tests for VFP4 are for fused multiply-add insns.
Since the MVFR1 field is used for both VFP and NEON, move its adjustment
from the !has_neon block to the (!has_vfp && !has_neon) block.
Test for vfp of the appropraite width alongside the test for simdfmac
wi
From: Guenter Roeck
USB ports on Xilinx Zync must be instantiated as TYPE_CHIPIDEA to work.
Linux expects and checks various chipidea registers, which do not exist
with the basic ehci emulation. This patch series fixes the problem.
Without this patch, USB ports fail to instantiate under Linux.
From: Richard Henderson
Sort this check to the start of a trans_* function.
Merge this with any existing test for fpdp_v2.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/t
From: Sai Pavan Boddu
The GIC built into the ARM11MPCore is always implemented with 4
priority bits; set the GIC property accordingly.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Peter Maydell
Message-id: 1582537164-764-4-git-send-email-sai.pavan.bo...@xilinx.com
Suggested-by: Peter Maydell
R
From: Richard Henderson
Use isar feature tests instead of feature bit tests.
Although none of QEMUs current cpus have VFPv3 without D32,
replace the large comment explaining why with one line that
sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions.
Mirror the test sequence used in the linu
From: Richard Henderson
We will eventually remove the early ARM_FEATURE_VFP test,
so add a proper test for each trans_* that does not already
have another ISA test.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-9-richard.hender...@linaro.org
Signe
The v8.4-RCPC extension implements some new instructions:
* LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW
* STLUR, STLURB, STLURH
These are all in a new subgroup of encodings that sits below the
top-level "Loads and Stores" group in the Arm ARM.
The STLUR* instructions have standard store
From: Richard Henderson
The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2. We will introduce another
feature tests for VFPv3.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-3-richard.hender...@linaro.org
From: Richard Henderson
Passing the raw op field from the manual is less instructive
than it might be. Do the full decode and use the existing
helpers to perform the expansion.
Since these are v8 insns, VECLEN+VECSTRIDE are already RES0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Hende
From: Philippe Mathieu-Daudé
As we want to re-use this code, extract it as a new function.
Since we are using the PL011 serial console, add a Avocado tag
to ease filtering of tests.
Reviewed-by: Thomas Huth
Reviewed-by: Wainer dos Santos Moschetta
Signed-off-by: Philippe Mathieu-Daudé
Message
The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers
have a format that uses the full 64 bit width of the register, and
adds a new CCSIDR2 register so AArch32 can get at the high 32 bits.
QEMU doesn't implement caches, so we just treat these ID registers as
opaque values that are s
We missed an instance of using FIELD_EX32 on a 64-bit ID
register, in isar_feature_aa64_pmu_8_4(). Fix it.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20200224172846.13053-2-peter.mayd...@linaro.org
---
target/arm/cpu.h | 4 ++--
From: Richard Henderson
We cannot easily create "any" functions for these, because the
ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero.
Which means that an aarch32-only cpu will return incorrect results
when testing the aarch64 registers.
To use these, we must either have context o
From: Thomas Huth
There is a kernel and initrd available on github which we can use
for testing this machine.
Signed-off-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Wainer dos Santos Moschetta
Signed-off-by: Philippe Mathieu-Daudé
Messa
Define EM_HEXAGON 164
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 8fbfe60..d51e7d4 100644
--- a/include/elf.h
+++ b/include/elf.h
The v8.3-RCPC extension implements three new load instructions
which provide slightly weaker consistency guarantees than the
existing load-acquire operations. For QEMU we choose to simply
implement them with a full LDAQ barrier.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message
From: Richard Henderson
We now have proper ISA checks within each trans_* function.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 4
1 file changed, 4
Define types used in files imported from the Hexagon architecture library
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_arch_types.h | 42 +
1 file changed, 42 insertions(+)
create mode 100644 target/hexagon/hex_arch_types.h
diff --git a/target/he
Certain operand types represent a non-contiguous set of values.
For example, the compound compare-and-jump instruction can only access
registers R0-R7 and R16-23.
This table represents the mapping from the encoding to the actual values.
Signed-off-by: Taylor Simpson
---
target/hexagon/regmap.h |
From: Richard Henderson
Now that we no longer have an early check for ARM_FEATURE_VFP,
we can use the proper ISA check in trans_VLLDM_VLSTM.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 2020022432.13807-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_regs.h | 99 +++
1 file changed, 99 insertions(+)
create mode 100644 target/hexagon/hex_regs.h
diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h
new file mode 100644
index 000..
On Mon, Feb 24, 2020 at 03:55:38PM -0500, Jagannathan Raman wrote:
> From: Elena Ufimtseva
>
> Add support to allow multiple devices to be configured in the
> remote process
This patch allows multiple devices to be addressed over a single UNIX
domain socket. This could be a scalability/performa
Gives a list of all the opcodes
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 12
1 file changed, 12 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index 3f52ef3..107e1e8 100755
--- a/target/hexagon/do_qemu.py
+++ b/target/hexagon/d
Gives an introduction and overview to the Hexagon target
Signed-off-by: Taylor Simpson
---
target/hexagon/README | 296 ++
1 file changed, 296 insertions(+)
create mode 100644 target/hexagon/README
diff --git a/target/hexagon/README b/target/hexa
From: Richard Henderson
Have the calls adjacent as an intermediate step toward
actually merging the decodes.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 2020022432.13807-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/translate.c |
Signed-off-by: Taylor Simpson
---
target/hexagon/printinsn.h | 26 +
target/hexagon/printinsn.c | 91 ++
2 files changed, 117 insertions(+)
create mode 100644 target/hexagon/printinsn.h
create mode 100644 target/hexagon/printinsn.c
diff -
The insn_t and packet_t are the interface between instruction decoding and
TCG code generation
Signed-off-by: Taylor Simpson
---
target/hexagon/insn.h | 133 ++
1 file changed, 133 insertions(+)
create mode 100644 target/hexagon/insn.h
diff --git
Run the C preprocessor across the instruction definition files and macro
definitoin file to expand macros and prepare the semantics_generated.pyinc
file. The
resulting file contains one entry with the semantics for each instruction and
one line with the instruction attributes associated with eac
From: Richard Henderson
We have converted all tests against these features
to ISAR tests.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 3 ---
target/arm/cpu.
Declare bitfields within registers such as user status register (USR)
Signed-off-by: Taylor Simpson
---
target/hexagon/reg_fields.h | 40 +++
target/hexagon/reg_fields_def.h | 109
target/hexagon/reg_fields.c | 28 +++
3 file
Data for printing (disassembling) each instruction (format string + operands)
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 151 ++
1 file changed, 151 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
in
Lists all the attributes associated with each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index 107e1e8..499f0e0 100755
--- a/target/hexagon/do_qem
From: Richard Henderson
Passing the raw o1 and o2 fields from the manual is less
instructive than it might be. Do the full decode and let
the trans_* functions pass in booleans to a helper.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-17-richard
Signed-off-by: Taylor Simpson
---
target/hexagon/attribs.h | 32
target/hexagon/attribs_def.h | 404 +++
2 files changed, 436 insertions(+)
create mode 100644 target/hexagon/attribs.h
create mode 100644 target/hexagon/attribs_def.h
diff --git a
The majority of helpers are generated. Define the helper functions needed
then include the generated file
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 37
target/hexagon/op_helper.c | 434 +
2 files changed, 471 insertions(+)
From: Richard Henderson
Those vfp instructions without extra opcode fields can
share a common @format for brevity.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 2020022432.13807-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/vfp.deco
Python script that emits the decode tree in dectree_generated.h.
Tested-by: Philippe Mathieu-Daudé
---
target/hexagon/dectree.py | 353 ++
1 file changed, 353 insertions(+)
create mode 100755 target/hexagon/dectree.py
diff --git a/target/hexagon/dect
Used to determine legal VLIW slots for each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/iclass.h | 46 +
target/hexagon/iclass.c | 107
2 files changed, 153 insertions(+)
create mode 100644 target/hexagon/icl
Take the words from instruction memory and build a packet_t for TCG code
generation
The following operations are performed
Convert the .new encoded offset to the register number of the producer
Reorder the instructions in the packet so .new producer is before consumer
Apply constant ex
From: Guenter Roeck
Xilinx USB devices are now instantiated through TYPE_CHIPIDEA,
and xlnx support in the EHCI code is no longer needed.
Signed-off-by: Guenter Roeck
Reviewed-by: Gerd Hoffmann
Message-id: 20200215122354.13706-3-li...@roeck-us.net
Signed-off-by: Peter Maydell
---
hw/usb/hcd-
Override memop instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 60 +++
1 file changed, 60 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index a6cbce0..00647cb 100644
--- a/
Imported from the Hexagon architecture library
imported/macros.def Scalar core macro definitions
The macro definition files specify instruction attributes that are applied
to each instruction that reverences the macro.
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/ma
Gives a default definition of fWRAP_ for each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index 6f0e376..3f52ef3 100755
--- a/target/hexagon/do_qe
Various forms of declare, read, write, free
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 363
1 file changed, 363 insertions(+)
create mode 100644 target/hexagon/macros.h
diff --git a/target/hexagon/macros.h b/target/hexagon/macro
From: Thomas Huth
Old kernels from the Meego project can be used to check that Linux
is at least starting on these machines.
Signed-off-by: Thomas Huth
Reviewed-by: Wainer dos Santos Moschetta
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathi
Utility functions called by various instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.h | 62
target/hexagon/conv_emu.h | 50 +++
target/hexagon/fma_emu.h | 30 ++
target/hexagon/arch.c | 663 +
target/hexagon/conv_emu.c | 369 +++
For each instruction we create
DEF_HELPER function prototype
TCG code to generate call to helper
Helper definition
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 769 ++
1 file changed, 769 insertions(+)
create mode 100755 t
Run the C preprocessor across the instruction definition and encoding
files to expand macros and prepare the iset.py file. The resulting
fill contains python data structures used to build the decode tree.
Tested-by: Philippe Mathieu-Daudé
---
target/hexagon/gen_dectree_import.c | 205 ++
From: Philippe Mathieu-Daudé
Add a test that verifies the Tux logo is displayed on the framebuffer.
We simply follow the OpenCV "Template Matching with Multiple Objects"
tutorial, replacing Lionel Messi by Tux:
https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html
When OpenCV
Helpers for load-locked/store-conditional
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 52 +
1 file changed, 52 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index d8d5d95..c0e4c39 1006
Helpers referenced in macros.h
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 67 +
1 file changed, 67 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index 0e2d7b9..9917d72 100644
--- a/ta
Signed-off-by: Taylor Simpson
---
target/hexagon/opcodes.h | 67 +++
target/hexagon/opcodes.c | 217 +++
2 files changed, 284 insertions(+)
create mode 100644 target/hexagon/opcodes.h
create mode 100644 target/hexagon/opcodes.c
diff --gi
In our KVM GICv2 realize function, we try to cope with old kernels
that don't provide the device control API (KVM_CAP_DEVICE_CTRL): we
try to use the device control, and if that fails we fall back to
assuming that the kernel has the old style KVM_CREATE_IRQCHIP and
that it will provide a GICv2.
Th
Override predicated load instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 235 ++
1 file changed, 235 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 6a69fc6..20d8584 10
Helpers for reading and writing registers
Helpers for getting and setting parts of values (e.g., set bit)
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 337
1 file changed, 337 insertions(+)
create mode 100644 target/hexagon/genptr_
Add Taylor Simpson as the Hexagon target maintainer
Signed-off-by: Taylor Simpson
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 36d94c1..85fc0ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -172,6 +172,14 @@ F: include/hw/cris/
F: t
Override dczeroa, allocframe, and return instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 209 ++
1 file changed, 209 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 006
Signed-off-by: Taylor Simpson
---
target/hexagon/gdbstub.c | 62
1 file changed, 62 insertions(+)
diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c
index e678aea..79a4f33 100644
--- a/target/hexagon/gdbstub.c
+++ b/target/hexagon/gd
Override predicated store instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 54 +++
1 file changed, 54 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index fdcc517..a6cbce0 10
GDB register read and write routines
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.c | 3 +++
target/hexagon/gdbstub.c | 49
2 files changed, 52 insertions(+)
create mode 100644 target/hexagon/gdbstub.c
diff --git a/target/hexagon/cp
Include the generated files and set up the data structures
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.h | 25 +
target/hexagon/genptr.c | 59 +
2 files changed, 84 insertions(+)
create mode 100644 target/hexagon/ge
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | +++
1 file changed, insertions(+)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index b8f8d9f..2101a01 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/mac
The Hexagon disassembler calls disassemble_hexagon to decode a packet
and format it for printing
Signed-off-by: Taylor Simpson
---
include/disas/dis-asm.h | 1 +
disas/hexagon.c | 62 +
disas/Makefile.objs | 1 +
3 files changed, 64 i
Read the instruction memory
Create a packet data structure
Generate TCG code for the start of the packet
Invoke the generate function for each instruction
Generate TCG code for the end of the packet
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 82 +
target/hexagon/translat
Override mathematical operations with more than one definition
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 1ac3
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/decode_ext_mmvec.h | 24 ++
target/hexagon/decode.c | 23 +-
target/hexagon/mmvec/decode_ext_mmvec.c | 670
target/hexagon/q6v_decode.c | 14 +
4 files changed, 729 insertions(+)
Imported from the Hexagon architecture library
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/iclass.def | 52 ++
1 file changed, 52 insertions(+)
create mode 100644 target/hexagon/imported/iclass.def
diff --git a/target/hexagon/imported/iclas
Various forms of declare, read, write, free for HVX operands
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h | 262 ++
1 file changed, 262 insertions(+)
create mode 100644 target/hexagon/mmvec/macros.h
diff --git a/target/hexagon/mmvec/ma
Override instructions to speed up qemu
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 97 +++
1 file changed, 97 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index d18aea4..5443a94e 1
Functions to support scatter/gather
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/system_ext_mmvec.h | 38 +
target/hexagon/mmvec/system_ext_mmvec.c | 263
2 files changed, 301 insertions(+)
create mode 100644 target/hexagon/mmvec/system_ext_mmvec.
Add CPU state header, CPU definitions and initialization routines
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu-param.h | 26
target/hexagon/cpu.h | 165 +++
target/hexagon/cpu_bits.h | 37 ++
target/hexagon/internal.h | 52
target/hexagon/
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 1 +
target/hexagon/op_helper.c | 75 ++
2 files changed, 76 insertions(+)
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 8558da8..64e798b 100644
--- a/target/hexagon
Add HVX support to the semantics generator
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_semantics.c | 9 +++
target/hexagon/do_qemu.py | 175 ++---
2 files changed, 171 insertions(+), 13 deletions(-)
diff --git a/target/hexagon/gen_semantics.c
This series adds support for the Hexagon processor with Linux user support
See patch 02/67 Hexagon README for detailed information.
The patches up to and including "Hexagon build infractructure" implement the
base Hexagon core and the remainder add HVX. Once the build infrastructure
patch is app
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h | 436 ++
1 file changed, 436 insertions(+)
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h
index be80bbd..c63a00a 100644
--- a/target/hexagon/mmvec/macros.h
+++ b/t
Override compare, transfer, conditional jump instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 119 ++
1 file changed, 119 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index
Override load instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 404 ++
target/hexagon/genptr.c | 1 +
2 files changed, 405 insertions(+)
create mode 100644 target/hexagon/helper_overrides.h
diff --git a/target/he
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 202
target/hexagon/genptr.c | 1 +
2 files changed, 203 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index e342f29..84479f8 1006
Override compound compare and jump instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 105 ++
1 file changed, 105 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 5443a94e.
> -Original Message-
> From: David Hildenbrand [mailto:da...@redhat.com]
> Sent: 13 February 2020 17:09
> To: Shameerali Kolothum Thodi ;
> Igor Mammedov
> Cc: peter.mayd...@linaro.org; xiaoguangrong.e...@gmail.com;
> m...@redhat.com; shannon.zha...@gmail.com; qemu-devel@nongnu.org;
> xu
Changes to packet semantics to support HVX
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 30
target/hexagon/translate.c | 188 +
2 files changed, 218 insertions(+)
diff --git a/target/hexagon/translate.h b/target/hexagon/tra
Helpers for store instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 77 +
1 file changed, 77 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index c0e4c39..0e2d7b9 100644
--- a/ta
Helpers for instructions overriden for optimization
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 314
1 file changed, 314 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index 9917d72..e
Imported from the Hexagon architecture library
imported/allext_macros.def Top level macro include for all extensions
imported/mmvec/macros.defHVX macro definitions
The macro definition files specify instruction attributes that are applied
to each instruction that reverences th
Override miscellaneous instructions identified during profiling
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 296 ++
1 file changed, 296 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/allextenc.def| 20 +
target/hexagon/imported/encode.def | 1 +
target/hexagon/imported/mmvec/encode_ext.def | 830 +++
3 files changed, 851 insertions(+)
create mode 100644 target/hexagon/impor
Override store instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 241 ++
1 file changed, 241 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 20d8584..fdcc517 100644
--- a
Philippe Mathieu-Daudé writes:
> The error_report API doesn't want trailing newline characters.
> Remove it, to avoid and error when moving the code around:
>
> ERROR: Error messages should not contain newlines
Commit 312fd5f2909 has a Coccinelle script. It should be committed and
re-run.
>
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