Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv",
define and use an any_predinv isar_feature test function.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
Message-id: 20200214175116.9164-5-peter.mayd...@linaro.org
---
ta
We're going to want to read the DBGDIDR register from KVM in
a subsequent commit, which means it needs to be in the
ARMISARegisters sub-struct. Move it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200214175116.9164-12-peter.mayd...@linaro.org
---
target/arm/cpu.h
We already define FIELD macros for ID_DFR0, so use them in the
one place where we're doing direct bit value manipulation.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
Message-id: 20200214175116.9164-8-peter.mayd...@linaro.org
---
target/arm/cp
From: Richard Henderson
These instructions shift left or right depending on the sign
of the input, and 7 bits are significant to the shift. This
requires several masks and selects in addition to the actual
shifts to form the complete answer.
That said, the operation is still a small improvement
The ARMv8.4-PMU extension adds:
* one new required event, STALL
* one new system register PMMIR_EL1
(There are also some more L1-cache related events, but since
we don't implement any cache we don't provide these, in the
same way we don't provide the base-PMUv3 cache events.)
The STALL event "c
The ARMv8.1-PMU extension requires:
* the evtCount field in PMETYPER_EL0 is 16 bits, not 10
* MDCR_EL2.HPMD allows event counting to be disabled at EL2
* two new required events, STALL_FRONTEND and STALL_BACKEND
* ID register bits in ID_AA64DFR0_EL1 and ID_DFR0
We already implement the 16-bit
From: Guenter Roeck
Booting the r2d machine from flash fails because flash is not discovered.
Looking at the flattened memory tree, we see the following.
FlatView #1
AS "memory", root: system
AS "cpu-memory-0", root: system
AS "sh_pci_host", root: bus master container
Root memory region: sys
Add the 64-bit version of the "is this a v8.1 PMUv3?"
ID register check function, and the _any_ version that
checks for either AArch32 or AArch64 support. We'll use
this in a later commit.
We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1,
but we move id_aa64dfr1 into the ARMISARegister
Now we have moved ID_MMFR4 into the ARMISARegisters struct, we
can define and use an isar_feature for the presence of the
ARMv8.2-AA32HPD feature, rather than open-coding the test.
While we're here, correct a comment typo which missed an 'A'
from the feature name.
Signed-off-by: Peter Maydell
Re
Set the ID register bits to provide ARMv8.4-PMU (and implicitly
also ARMv8.1-PMU) in the 'max' CPU.
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
Message-id: 20200214175116.9164-16-peter.mayd...@linaro.org
---
target/arm/cpu64.c | 8
1 file changed, 8 insertions(+)
diff
The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'.
Correct our #define of PMCRDP and add the missing PMCRX.
We do have the correct behaviour for handling the DP bit being
set, so this fixes a guest-visible bug.
Fixes: 033614c47de
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by:
On 21/02/20 13:44, Peter Maydell wrote:
> On Fri, 21 Feb 2020 at 11:44, Paolo Bonzini wrote:
>>
>> On 21/02/20 11:21, Peter Maydell wrote:
>>> Before you do that, I would suggest investigating:
>>> * is this a problem we've already had on x86 and that there is a
>>>standard solution for
>> Di
Now we have isar_feature test functions that look at fields in the
ID_AA64DFR0_EL1 and ID_DFR0 ID registers, add the code that reads
these register values from KVM so that the checks behave correctly
when we're using KVM.
No isar_feature function tests ID_AA64DFR1_EL1 or DBGDIDR yet, but we
add it
The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
error meant we were looking at MVFR0 instead.
Fix the functions to look at the right register; this requires
us to move at least id_mmfr3 to the ARMISARegisters struc
From: Guenter Roeck
We need to be able to use OHCISysBusState outside hcd-ohci.c, so move it
to its include file.
Reviewed-by: Gerd Hoffmann
Signed-off-by: Guenter Roeck
Tested-by: Niek Linnenbank
Message-id: 20200217204812.9857-2-li...@roeck-us.net
Signed-off-by: Peter Maydell
---
hw/usb/h
On Fri, 21 Feb 2020 at 13:09, Paolo Bonzini wrote:
>
> On 21/02/20 13:44, Peter Maydell wrote:
> > On Fri, 21 Feb 2020 at 11:44, Paolo Bonzini wrote:
> >>
> >> On 21/02/20 11:21, Peter Maydell wrote:
> >>> Before you do that, I would suggest investigating:
> >>> * is this a problem we've already
The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7
or the original ARMv8. They were later added as optional registers,
whose presence is signaled by the ID_MMFR4.AC2 field. From ARMv8.2
they are mandatory (ie ID_MMFR4.AC2 must be non-zero).
We implemented HACTLR2 in commit 0e0
Cut-and-paste errors mean we're using FIELD_EX64() to extract fields from
some 32-bit ID register fields. Use FIELD_EX32() instead. (This makes
no difference in behaviour, it's just more consistent.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20200214175116.9164-21-p
From: Richard Henderson
Many uses of ARM_FEATURE_VFP3 are testing for the number of simd
registers implemented. Use the proper test vs MVFR0.SIMDReg.
Signed-off-by: Richard Henderson
Message-id: 20200214181547.21408-4-richard.hender...@linaro.org
[PMM: fix typo in commit message]
Reviewed-by:
From: Richard Henderson
The gvec form will be needed for implementing SVE2.
Extend the implementation to operate on uint64_t instead of uint32_t.
Use a counted inner loop instead of terminating when op1 goes to zero,
looking toward the required implementation for ARMv8.4-DIT.
Tested-by: Alex Be
From: Guenter Roeck
We'll use this property in a follow-up patch to insantiate an EHCI
bus with companion support.
Reviewed-by: Gerd Hoffmann
Signed-off-by: Guenter Roeck
Tested-by: Niek Linnenbank
Message-id: 20200217204812.9857-3-li...@roeck-us.net
Signed-off-by: Peter Maydell
---
hw/usb/
From: Richard Henderson
We are going to convert FEATURE tests to ISAR tests,
so FPSP needs to be set for these cpus, like we have
already for FPDP.
Signed-off-by: Richard Henderson
Message-id: 20200214181547.21408-5-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter M
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/passthrough_ll.o
tools/virtiofsd/passthrough_ll.c:1083:5: warning: Value stored to 'saverr' is
never read
saverr = ENOMEM;
^~~
Fixes: 7c6b66027
Reported-by: Cl
From: Guenter Roeck
Instantiate EHCI and OHCI controllers on Allwinner A10. OHCI ports are
modeled as companions of the respective EHCI ports.
With this patch applied, USB controllers are discovered and instantiated
when booting the cubieboard machine with a recent Linux kernel.
ehci-platform 1
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/fuse_lowlevel.o
tools/virtiofsd/fuse_lowlevel.c:195:9: warning: Value stored to 'error' is
never read
error = -ERANGE;
^ ~~~
Fixes: 3db2876
Reported-by:
No code use the espdma_memory_[read/write] functions outside
of hw/dma/sparc32_dma.c, make them static.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sparc/sparc32_dma.h | 2 --
hw/dma/sparc32_dma.c | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/include
From: Richard Henderson
The gvec form will be needed for implementing SVE2.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200216214232.4230-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 4 +---
From: Richard Henderson
Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.
Signed-off-by: Richard Henderson
Message-id: 20200214181547.21408-6-richard.hender.
From: Richard Henderson
Sort this check to the start of a trans_* function.
Merge this with any existing test for fpdp_v2.
Signed-off-by: Richard Henderson
Message-id: 20200214181547.21408-10-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/
Both PCNetState::phys_mem_read/write handlers end calling
dma_memory_read/write, which both take void pointers (since
introduced in commit d86a77f8). The PCNetState phys_mem_read/write
handlers can take a void pointer too.
As the length is always a sizeof(), use a size_t type.
The 'do_bswap' is use
From: Francisco Iglesias
Correct the number of dummy cycles required by the FAST_READ_4 command (to
be eight, one dummy byte).
Fixes: ef06ca3946 ("xilinx_spips: Add support for RX discard and RX drain")
Suggested-by: Cédric Le Goater
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Igle
From: Xiao Yang
All code in fuse.h and struct fuse_module are not used by virtiofsd
so removing them is safe.
Signed-off-by: Xiao Yang
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Dr. David Alan Gilbert
---
tools/virtiofsd/fuse.h | 1229 -
From: Richard Henderson
We still need two different helpers, since NEON and SVE2 get the
inputs from different locations within the source vector. However,
we can convert both to the same internal form for computation.
The sve2 helper is not used yet, but adding it with this patch
helps illustr
From: "Dr. David Alan Gilbert"
second should be seconds.
Reported-by: Christophe de Dinechin
Signed-off-by: Dr. David Alan Gilbert
---
tools/virtiofsd/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/virtiofsd/helper.c b/tools/virtiofsd/helper.c
index 0801cf7
On Fri, 21 Feb 2020 at 13:25, Philippe Mathieu-Daudé wrote:
>
> No code use the espdma_memory_[read/write] functions outside
> of hw/dma/sparc32_dma.c, make them static.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
thanks
-- PMM
From: Richard Henderson
The old name, isar_feature_aa32_fp_d32, does not reflect
the MVFR0 field name, SIMDReg.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20200214181547.21408-3-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
[PMM: wrapped one lon
From: Philippe Mathieu-Daudé
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/passthrough_ll.o
tools/virtiofsd/passthrough_ll.c:925:9: warning: Value stored to 'newfd' is
never read
newfd = -1;
^ ~~
tools/virtiofsd/passthrough_ll.c:94
Following up "global exec/memory/dma APIs cleanup"
https://www.mail-archive.com/qemu-devel@nongnu.org/msg681475.html
Few more cleanups in PCNET & SCSI ESP devices.
Philippe Mathieu-Daudé (3):
hw/dma/sparc32_dma: Make espdma_memory_[read/write] static
hw/scsi/esp: Let ESPDMAMemoryReadWriteFunc
From: Richard Henderson
We will shortly use these to test for VFPv2 and VFPv3
in different situations.
Signed-off-by: Richard Henderson
Message-id: 20200214181547.21408-8-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 18 ++
On Tue, Feb 18, 2020 at 06:27:08PM +, Stefan Hajnoczi wrote:
> The first rcu_read_lock/unlock() is expensive. Nested calls are cheap.
>
> This optimization increases IOPS from 73k to 162k with a Linux guest
> that has 2 virtio-blk,num-queues=1 and 99 virtio-blk,num-queues=32
> devices.
>
> S
The ESPDMAMemoryReadWriteFunc handlers end calling
dma_memory_read/write, which both take void pointers (since
introduced in commit d86a77f8). The ESPDMAMemoryReadWriteFunc
handlers can take a void pointer too.
All calls to these handlers in hw/scsi/esp.c use an unsigned
length. Use size_t type.
From: Richard Henderson
The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2. We will introduce further
feature tests for VFPv3.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20200214181547.21408-7-richard.hender...@linaro.org
On 22.12.19 12:36, Alberto Garcia wrote:
> If an image has subclusters then there are more copy-on-write
> scenarios that we need to consider. Let's say we have a write request
> from the middle of subcluster #3 until the end of the cluster:
>
>- If the cluster is new, then subclusters #0 to #
From: Richard Henderson
Shuffle the order of the checks so that we test the ISA
before we test anything else, such as the register arguments.
Signed-off-by: Richard Henderson
Message-id: 20200214181547.21408-9-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
On Wed, 19 Feb 2020 at 22:07, Laurent Vivier wrote:
>
> This series copies the files syscall.tbl from linux v5.5 and generates
> the file syscall_nr.h from them.
>
> This is done for all the QEMU targets that have a syscall.tbl
> in the linux source tree: mips, mips64, i386, x86_64, sparc, s390x,
From: Richard Henderson
We will eventually remove the early ARM_FEATURE_VFP test,
so add a proper test for each trans_* that does not already
have another ISA test.
Signed-off-by: Richard Henderson
Message-id: 20200214181547.21408-11-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Sign
On Tue, Feb 18, 2020 at 03:48:11PM -0700, Andrzej Jakowski wrote:
> This patch introduces support for PMR that has been defined as part of NVMe
> 1.4
> spec. User can now specify a pmr_file which will be mmap'ed into qemu address
> space and subsequently in PCI BAR 2. Guest OS can perform mmio rea
On Wed, Feb 19, 2020 at 08:05:12PM +0100, Paolo Bonzini wrote:
> Il mer 19 feb 2020, 18:58 Stefan Hajnoczi ha scritto:
>
> > On Wed, Feb 19, 2020 at 12:09:48PM +0100, Paolo Bonzini wrote:
> > > Really a great idea, though I have some remarks on the implementation
> > below.
> > >
> > > On 19/02/2
On Thu 20 Feb 2020 05:48:25 PM CET, Eric Blake wrote:
>>> The qcow2 spec changes earlier in the series made it sound like your
>>> choices are exactly 1 or 32,
>>
+#define QCOW_MAX_SUBCLUSTERS_PER_CLUSTER 32
+
>>>
>>> ...but this name sounds like other values (2, 4, 8, 16) might be
>>> p
Check you have selected the french keymap in virt-manager (see attached
picture)
** Attachment added: "keymap.png"
https://bugs.launchpad.net/qemu/+bug/1863601/+attachment/5330070/+files/keymap.png
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You received this bug notification because you are a member of qemu-
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21.02.2020 15:35, dovgaluk wrote:
Vladimir Sementsov-Ogievskiy писал 2020-02-21 13:09:
21.02.2020 12:49, dovgaluk wrote:
Vladimir Sementsov-Ogievskiy писал 2020-02-20 12:36:
1 or 2 are ok, and 4 or 8 lead to the failures.
That is strange. I could think, that it was caused by the bugs in
dete
ository at:
https://gitlab.com/dagrh/qemu.git tags/pull-virtiofs-20200221
for you to fetch changes up to 5bb8e8beedb47fc0d0a44957a154918c4f4afc80:
docs: Fix virtiofsd.1 location (2020-02-21 13:05:27 +)
----
virtiofs pull 20200221
M
On Thu, Feb 20, 2020 at 11:38:28AM +0100, Paolo Bonzini wrote:
> QSLIST is the only family of lists for which we do not have RCU-friendly
> accessors,
> add them.
>
> Signed-off-by: Paolo Bonzini
> ---
> include/qemu/queue.h | 15 +++--
> include/qemu/rcu_queue.h | 47 ++
From: Miroslav Rezanina
Patch 6a7e2bbee5 docs: add virtiofsd(1) man page introduced new man
page virtiofsd.1. Unfortunately, wrong file location is used as
source for install command. This cause installation of docs fail.
Fixing wrong location so installation is successful.
Signed-off-by: Miros
On Thu, Feb 20, 2020 at 05:55:56PM +0100, Julia Suvorova wrote:
> Device unplug can be done asynchronously. Thus, sending the second
> device_del before the previous unplug is complete may lead to
> unexpected results. On PCIe devices, this cancels the hot-unplug
> process.
>
> Signed-off-by: Juli
On Fri, Feb 21, 2020 at 09:39:51AM +, Stefan Hajnoczi wrote:
> The ctx->first_bh list contains all created BHs, including those that
> are not scheduled. The list is iterated by the event loop and therefore
> has O(n) time complexity with respected to the number of created BHs.
>
> Rewrite BH
On Wed, Feb 19, 2020 at 11:10:57PM -0500, Alexander Bulekov wrote:
> Move vl.c to a separate directory, similar to linux-user/
> Update the chechpatch and get_maintainer scripts, since they relied on
> /vl.c for top_of_tree checks.
>
> Signed-off-by: Alexander Bulekov
> ---
> MAINTAINERS
On Fri, 21 Feb 2020 at 13:45, Peter Maydell wrote:
>
> On Wed, 19 Feb 2020 at 22:07, Laurent Vivier wrote:
> >
> > This series copies the files syscall.tbl from linux v5.5 and generates
> > the file syscall_nr.h from them.
> >
> > This is done for all the QEMU targets that have a syscall.tbl
> >
On Wed, Feb 19, 2020 at 11:11:17PM -0500, Alexander Bulekov wrote:
> The virtio-scsi fuzz target sets up and fuzzes the available virtio-scsi
> queues. After an element is placed on a queue, the fuzzer can select
> whether to perform a kick, or continue adding elements.
>
> Signed-off-by: Alexande
On Thu 20 Feb 2020 05:27:28 PM CET, Max Reitz wrote:
>> +static inline uint64_t get_l2_bitmap(BDRVQcow2State *s, uint64_t *l2_slice,
>> + int idx)
>> +{
>> +if (has_subclusters(s)) {
>> +idx *= l2_entry_size(s) / sizeof(uint64_t);
>> +return b
On 21/02/20 14:53, Stefan Hajnoczi wrote:
> On Thu, Feb 20, 2020 at 05:55:56PM +0100, Julia Suvorova wrote:
>> Device unplug can be done asynchronously. Thus, sending the second
>> device_del before the previous unplug is complete may lead to
>> unexpected results. On PCIe devices, this cancels the
On Mon, 17 Feb 2020 at 13:10, Dongjiu Geng wrote:
>
> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
> translates the host VA delivered by host to guest PA, then fills this PA
> to guest APEI GHES memory, then notifies guest according to the SIGBUS
> type.
>
> When guest
On Mon, 17 Feb 2020 at 13:10, Dongjiu Geng wrote:
>
> The little end UUID is used in many places, so make
> NVDIMM_UUID_LE to a common macro to convert the UUID
> to a little end array.
>
> Signed-off-by: Dongjiu Geng
> Reviewed-by: Xiang Zheng
> ---
> hw/acpi/nvdimm.c| 8 ++--
> includ
On 2020/2/21 下午4:58, Paolo Bonzini wrote:
> On 21/02/20 04:45, cheng...@emindsoft.com.cn wrote:
>> static inline void fpush(CPUX86State *env)
>> {
>> -env->fpstt = (env->fpstt - 1) & 7;
>> -env->fptags[env->fpstt] = 0; /* validate stack entry */
>> +set_fpstt(env, env->fpstt - 1, fals
On Mon, 17 Feb 2020 at 13:10, Dongjiu Geng wrote:
>
> In the ARMv8 platform, the CPU error types includes synchronous external
> abort(SEA) and SError Interrupt (SEI). If exception happens in guest, host
> does not know the detailed information of guest, so it is expected that guest
> can do th
Actually you explicitly do *NOT* want to select any keymap in virt-
manager in general. Picking a keymap disables the VNC protocol extension
for raw scancodes. This means that QEMU has to do keymap <-> scancode
conversion. In such a setup the host OS desktop keymap, the QEMU keymap
and the guest OS
Patchew URL:
https://patchew.org/QEMU/20200221130740.7583-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PULL 00/52] target-arm queue
Message-id: 20200221130740.7583-1-peter.mayd...@linaro.org
Type: series
On Thu, 20 Feb 2020 at 16:07, Max Reitz wrote:
>
> The following changes since commit 672f9d0df10a68a5c5f2b32cbc8284abf9f5ee18:
>
> Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
> (2020-02-18 14:23:43 +)
>
> are available in the Git repository at:
>
> https:/
On 22.12.19 12:36, Alberto Garcia wrote:
> The logic of this function remains pretty much the same, except that
> it uses count_contiguous_subclusters(), which combines the logic of
> count_contiguous_clusters() / count_contiguous_clusters_unallocated()
> and checks individual subclusters.
>
> Sig
Yes, it works without selecting a keyboard on my machine with a french
keyboard.
But perhaps Aditya has explicitly selected another keyboard than "fr" or
"Auto"?
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On Fri, 14 Feb 2020 at 13:29, Eric Auger wrote:
>
> Adds the "virtio,pci-iommu" node in the host bridge node and
> the RID mapping, excluding the IOMMU RID.
>
> This is done in the virtio-iommu-pci hotplug handler which
> gets called only if no firmware is loaded or if -no-acpi is
> passed on the
On Fri, 14 Feb 2020 at 13:29, Eric Auger wrote:
>
> Add a new "virtio-iommu" section with the new files
> related to this device.
>
> Signed-off-by: Eric Auger
> ---
> MAINTAINERS | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c7717df720..b7a7a18
On Fri, 14 Feb 2020 at 13:28, Eric Auger wrote:
>
> This series implements the QEMU virtio-iommu device.
>
> This matches the v0.12 spec (voted) and the corresponding
> virtio-iommu driver upstreamed in 5.3. All kernel dependencies
> are resolved for DT integration. The virtio-iommu can be
> insta
Le 21/02/2020 à 14:45, Peter Maydell a écrit :
> On Wed, 19 Feb 2020 at 22:07, Laurent Vivier wrote:
>>
>> This series copies the files syscall.tbl from linux v5.5 and generates
>> the file syscall_nr.h from them.
>>
>> This is done for all the QEMU targets that have a syscall.tbl
>> in the linux
On 22.12.19 12:36, Alberto Garcia wrote:
> Setting the QCOW_OFLAG_ZERO bit of the L2 entry is forbidden if an
> image has subclusters. Instead, the individual 'all zeroes' bits must
> be used.
>
> Signed-off-by: Alberto Garcia
> ---
> block/qcow2-cluster.c | 14 ++
> 1 file changed,
Le 21/02/2020 à 14:56, Peter Maydell a écrit :
> On Fri, 21 Feb 2020 at 13:45, Peter Maydell wrote:
>>
>> On Wed, 19 Feb 2020 at 22:07, Laurent Vivier wrote:
>>>
>>> This series copies the files syscall.tbl from linux v5.5 and generates
>>> the file syscall_nr.h from them.
>>>
>>> This is done fo
On Fri, Feb 21, 2020 at 02:06:26PM +0100, Paolo Bonzini wrote:
> On 21/02/20 13:59, Stefan Hajnoczi wrote:
> > 1. It doesn't crash if the node is currently not on a list.
> > 2. It clears the node's linked list pointers so that future linked
> >list operations (like QLIST_SAFE_REMOVE()) aren't
On 22.12.19 12:36, Alberto Garcia wrote:
> Setting the QCOW_OFLAG_ZERO bit of the L2 entry is forbidden if an
> image has subclusters. Instead, the individual 'all zeroes' bits must
> be used.
>
> Signed-off-by: Alberto Garcia
> ---
> block/qcow2-cluster.c | 6 +-
> 1 file changed, 5 inserti
On Fri, Feb 21, 2020 at 02:06:26PM +0100, Paolo Bonzini wrote:
> On 21/02/20 13:59, Stefan Hajnoczi wrote:
> > /* Add a handler to a ready list */
> > static void add_ready_handler(AioHandlerList *ready_list,
> > AioHandler *node,
> >
On 22.12.19 12:36, Alberto Garcia wrote:
> Setting the QCOW_OFLAG_ZERO bit of the L2 entry is forbidden if an
> image has subclusters. Instead, the individual 'all zeroes' bits must
> be used.
>
> Signed-off-by: Alberto Garcia
> ---
> block/qcow2-refcount.c | 9 +++--
> 1 file changed, 7 ins
On 22.12.19 12:37, Alberto Garcia wrote:
> Two changes are needed in order to add subcluster support to this
> function: deallocated clusters must have their bitmaps cleared, and
> expanded clusters must have all the "subcluster allocated" bits set.
Not really, to have real subcluster support it w
On 22.12.19 12:37, Alberto Garcia wrote:
> l2meta_cow_start() and l2meta_cow_end() are not necessarily
> cluster-aligned if the image has subclusters, so update the
> calculation of old_start and old_end to guarantee that no two requests
> try to write on the same cluster.
>
> Signed-off-by: Alber
On 21/02/20 15:47, Stefan Hajnoczi wrote:
>>> QLIST_SAFE_REMOVE(node, node_ready); /* remove from nested parent's
>>> list */
>>> ^ would cause corruption if node->node_ready was stale!
>>>
>>> Would you like me to add a comment?
>> No, it's okay.
> Are you happy with this series?
On Fri 21 Feb 2020 12:35:55 PM CET, Max Reitz wrote:
>> @@ -2223,22 +2227,23 @@ static coroutine_fn int
>> qcow2_co_preadv_part(BlockDriverState *bs,
>> }
>>
>> qemu_co_mutex_lock(&s->lock);
>> -ret = qcow2_get_cluster_offset(bs, offset, &cur_bytes,
>> &cluster_offset)
* David Hildenbrand (da...@redhat.com) wrote:
> Resizing while migrating is dangerous and does not work as expected.
> The whole migration code works on the usable_length of ram blocks and does
> not expect this to change at random points in time.
>
> In the case of precopy, the ram block size mus
On Thu, 20 Feb 2020 at 14:20, Kashyap Chamarthy wrote:
>
> This doc was originally written by Daniel P. Berrangé
> , introduced via commit[1]: 2544e9e4aa (docs: add
> guidance on configuring CPU models for x86, 2018-06-27).
>
> In this patch:
>
> - 1-1 conversion of Texinfo to rST, besides a cou
On Wed, Feb 19, 2020 at 11:10:56PM -0500, Alexander Bulekov wrote:
> Hello,
>
> This series adds a framework for coverage-guided fuzzing of
> virtual-devices. Fuzzing targets are based on qtest and can make use of
> libqos. Fuzzing can help discover device bugs, such as
> assertion-failures, timeo
On 21.02.20 16:14, Dr. David Alan Gilbert wrote:
> * David Hildenbrand (da...@redhat.com) wrote:
>> Resizing while migrating is dangerous and does not work as expected.
>> The whole migration code works on the usable_length of ram blocks and does
>> not expect this to change at random points in tim
>
> are available in the Git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-5.0-20200221
>
> for you to fetch changes up to 438bafcac55308eef4f9029c94dbadd2c7ac3bb7:
>
> hw/ppc/virtex_ml507:fix lea
On Fri, Feb 14, 2020 at 05:17:07PM +, Stefan Hajnoczi wrote:
> This patch series makes AioHandler deletion and dispatch O(1) with respect to
> the total number of registered handlers. The event loop has scalability
> problems when many AioHandlers are registered because it is O(n). Linux
> ep
On Fri, Feb 21, 2020 at 04:04:10PM +0100, Paolo Bonzini wrote:
> On 21/02/20 15:47, Stefan Hajnoczi wrote:
> >>> QLIST_SAFE_REMOVE(node, node_ready); /* remove from nested parent's
> >>> list */
> >>> ^ would cause corruption if node->node_ready was stale!
> >>>
> >>> Would you lik
On Fri, 21 Feb 2020 at 07:46, Sai Pavan Boddu
wrote:
>
> Priority bits implemented in arm-gic can be 8 to 4, un-implemented bits
> are read as zeros(RAZ).
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/intc/arm_gic.c| 26 --
> hw/intc/arm_gic_common.c
On Fri, 21 Feb 2020 at 07:46, Sai Pavan Boddu
wrote:
>
> All A9 CPUs have a GIC with 5 bits of priority.
>
> Signed-off-by: Sai Pavan Boddu
> Suggested-by: Peter Maydell
> ---
> hw/cpu/a9mpcore.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
On Fri, Feb 21, 2020 at 03:16:29PM +, Peter Maydell wrote:
> On Thu, 20 Feb 2020 at 14:20, Kashyap Chamarthy wrote:
> >
> > This doc was originally written by Daniel P. Berrangé
> > , introduced via commit[1]: 2544e9e4aa (docs: add
> > guidance on configuring CPU models for x86, 2018-06-27).
>
On Fri, Feb 21, 2020 at 12:04 PM Michael Rolnik wrote:
>
> Hi all.
>
> How is it going?
>
> Regards,
> Michael.
>
Michael,
I think we are very close to merging.
There is absolutely no need to support ALL AVR mcus or AVR core types
in the first version that will be merged.
But this issue (recen
On Fri, 21 Feb 2020 at 07:46, Sai Pavan Boddu
wrote:
>
> ARM11MPCore GIC is implemented with 4 priority bits.
>
> Signed-off-by: Sai Pavan Boddu
> Suggested-by: Peter Maydell
> ---
> hw/cpu/arm11mpcore.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu
On Fri, 21 Feb 2020 at 15:31, Daniel P. Berrangé wrote:
>
> On Fri, Feb 21, 2020 at 03:16:29PM +, Peter Maydell wrote:
> > On Thu, 20 Feb 2020 at 14:20, Kashyap Chamarthy wrote:
> > > diff --git a/docs/system/conf.py b/docs/system/conf.py
> > > index 7ca115f5e0..7cc9da9508 100644
> > > --- a/
On 2/21/20 6:45 AM, Stefan Hajnoczi wrote:
> Why is msync(2) done on memory loads instead of stores?
This is my interpretation of NVMe spec wording with regards to PMRWBM field
which says:
"The completion of a memory read from any Persistent
Memory Region address ensures that all prior writes to
On 21/02/20 16:29, Stefan Hajnoczi wrote:
>> Yes. Let's keep the Q*_REMOVE cleanup on the todo list. I'd keep
>> Q*_SAFE_REMOVE, but clear the pointer unconditionally in Q*_REMOVE so
>> that we can have something like Q*_IN_LIST too.
> QLIST_IS_INSERTED() is part of this patch series, although I
* David Hildenbrand (da...@redhat.com) wrote:
> On 21.02.20 16:14, Dr. David Alan Gilbert wrote:
> > * David Hildenbrand (da...@redhat.com) wrote:
> >> Resizing while migrating is dangerous and does not work as expected.
> >> The whole migration code works on the usable_length of ram blocks and doe
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