Hello,
This is an RFC series to start exploring the possibility of enabling
hardfloat for PPC target that haven't progressed in the last two years.
Hopefully we can work out something now. Previously I've explored this
here:
https://lists.nongnu.org/archive/html/qemu-ppc/2018-07/msg00261.html
wh
Add a property to allow setting a flag in cpu env that will be used to
control if hardfloat is used for floating point ops (i.e. speed is
preferred over accuracy).
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h| 2 ++
target/ppc/translate_init.inc.c | 2 ++
2 files changed, 4
While other targets take advantage of using host FPU to do floating
point computations, this was disabled for PPC target because always
clearing exception flags before every FP op made it slightly slower
than emulating everyting with softfloat. To emulate some FPSCR bits,
clearing of fp_status may
Hi Marc,
On 2/16/20 11:34 PM, Marc Zyngier wrote:
On 2020-02-14 05:59, Gavin Shan wrote:
This supports SError injection, which will be used by "virt" board to
simulating the behavior of NMI injection in next patch. As Peter Maydell
suggested, this adds a new interrupt (ARM_CPU_SERROR), which is
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace DO_CMP0 with its scalar expansion, a simple negation.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime-gvec.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-r
The comment in tcg-runtime-gvec.c about CONFIG_VECTOR16 says that
tcg-op-gvec.c has eliminated size 8 vectors, and only passes on
multiples of 16. This may have been true of the first few operations,
but is not true of all operations.
In particular, multiply, shift by scalar, and compare of 8
The comment in tcg-runtime-gvec.c about CONFIG_VECTOR16 says that
tcg-op-gvec.c has eliminated size 8 vectors, and only passes on
multiples of 16. This may have been true of the first few operations,
but is not true of all operations.
In particular, multiply, shift by scalar, and compare of 8- an
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace the vec* types with their scalar expansions.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime-gvec.c | 270 +--
1 file changed, 130 insertions(+), 140 deletions(-)
diff --git a/accel/tcg/tcg-runt
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace the DUP* expansions with the scalar argument.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime-gvec.c | 50 +++-
1 file changed, 15 insertions(+), 35 deletions(-)
diff --git a/accel/tcg/tcg-runti
Patchew URL:
https://patchew.org/QEMU/20200217025957.12031-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/4] tcg: Fix for Bug 1863508
Message-id: 20200217025957.12031-1-richard.hender...@linaro
Fix posted:
http://patchwork.ozlabs.org/patch/1238946/
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1863508
Title:
qemu-system-arm stops with SIGSEGV in helper_gvec_eq16
Status in QEMU:
In Prog
From: Pan Nengyuan
v1:
- Delay timer_new() from init() to realize() to fix memleaks.
v2:
- Similarly to other cleanups, move timer_new into realize in
target/s390x/cpu.c (Suggested by Philippe Mathieu-Daudé).
- Send these two patches as a series instead of sending each as a single
patc
From: Pan Nengyuan
There are some memleaks when we call 'device_list_properties'. This patch move
timer_new from init into realize to fix it.
Meanwhile, do the null check in mos6522_reset() to avoid null deref if we move
timer_new into realize().
Reported-by: Euler Robot
Signed-off-by: Pan Ne
From: Pan Nengyuan
This patch fix memleaks when we call tests/qtest/cpu-plug-test on s390x. The
leak stack is as follow:
Direct leak of 48 byte(s) in 1 object(s) allocated from:
#0 0x7fb43c7cd970 in __interceptor_calloc (/lib64/libasan.so.5+0xef970)
#1 0x7fb43be2149d in g_malloc0 (/lib6
On 2/15/2020 11:35 AM, Daniel Cho wrote:
Hi Dave,
Yes, I agree with you, it does need a timeout.
Hi Daniel and Dave,
Current colo-compare already have the timeout mechanism.
Named packet_check_timer, It will scan primary packet queue to make
sure all the primary packet not stay too long
Hello,
Philippe Mathieu-Daudé, le lun. 17 févr. 2020 01:44:35 +0100, a ecrit:
> On Sat, Feb 15, 2020 at 10:01 PM Aleksandar Markovic
> wrote:
> > 9:56 PM Sub, 15.02.2020. Philippe Mathieu-Daudé
> > је написао/ла:
> > > On Fri, Feb 14, 2020 at 12:04 AM Aleksandar Markovic
> > > wrote:
> > > >
>
Maxim Levitsky writes:
> On Sat, 2020-02-15 at 15:51 +0100, Markus Armbruster wrote:
>> Review of this patch led to a lengthy QAPI schema design discussion.
>> Let me try to condense it into a concrete proposal.
>>
>> This is about the QAPI schema, and therefore about QMP. The
>> human-friendly
Kevin Wolf writes:
> This patch adds a new 'coroutine' flag to QMP command definitions that
> tells the QMP dispatcher that the command handler is safe to be run in a
> coroutine.
>
> The documentation of the new flag pretends that this flag is already
> used as intended, which it isn't yet after
Hi Howard, could you test out this patch for me on Fedora 31? It is to be
> applied over the v3 patch.
>
> Thank you.
>
> ---
> hw/audio/screamer.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/hw/audio/screamer.c b/hw/audio/screamer.c
> index ad4aba12eb..7d
EL3 extension is not always needed.
Signed-off-by: Xu Yandong
---
hw/arm/virt.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index afaf143888..087616190e 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -627,6 +627,14 @@ static v
Move smp_cpus member from VirtMachineState to ArmMachineState.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/virt-acpi-build.c | 4 ++--
hw/arm/virt.c| 12 ++--
include/hw/arm/arm.h | 1 +
include/hw/arm/virt.h| 3
EL2 extension is not always needed.
Signed-off-by: Xu Yandong
---
hw/arm/virt.c | 116 +-
1 file changed, 77 insertions(+), 39 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 32c3977e32..afaf143888 100644
--- a/hw/arm/virt.c
+++ b/hw
GICv2m and GICits is not always needed.
Signed-off-by: Xu Yandong
---
hw/arm/virt.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9031fd6757..32c3977e32 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -605,6 +605,15 @@
Move psci_enable member from VirtMachineState to ArmMachineState.
Move claim_edge_triggered_timers member from VirtMachineClass to
ArmMachineClass.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/virt-acpi-build.c | 7 ---
hw/arm/virt.c
Split sharable GIC qdev create and sysbus initiatea codes as independent
function.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 106 +++
hw/arm/virt.c| 93 +
include/hw/arm/arm.h | 4 ++
3 files chang
Move irqmap member from VirtMachineState to ArmMachineState.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/virt-acpi-build.c | 8
hw/arm/virt.c| 25 +
include/hw/arm/arm.h | 1 +
include/hw/arm
Implement Microvm for aarch64 architecture
This series attempts to implement microvm for aarch64
architecture.
Just like how Sergio Lopez does for implementing microvm
for x86 architecture. We remove parts of emulate devices which
are not needed in microvm, compared with normal VM,
We only keep P
Move cpu related functions that will be shared between VIRT and
non-VIRT machine types to arm.c.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 89 ++
hw/arm/virt.c | 91 +--
include/hw/arm/arm.h | 3
Move device related functions to arm.c, include RTC(pl031), UART(pl011),
virtio devices.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 137 +
hw/arm/virt.c | 156 +++---
include/hw/arm/arm.h | 8 +++
inclu
Move bootinfo member from VirtMachineState to ArmMachineState.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 9 +
hw/arm/virt.c | 28 +---
include/hw/arm/arm.h | 3 +++
include/hw/arm/virt.h | 1 -
4 files changed, 21 insertions(+), 20 deletion
Move gic member from VirtMachineState to ArmMachineState.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 35 ++
hw/arm/virt-acpi-build.c | 8 +--
hw/arm/virt.c| 139 +++--
Move fdt related functions that will be shared between VIRT and
non-VIRT machine types to arm.c.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 226
hw/arm/virt.c| 238 +--
include/hw/arm/arm.h | 8 +
Move memmap member from VirtMachineState to ArmMachineState.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/virt-acpi-build.c | 21 +++--
hw/arm/virt.c| 178 ---
include/hw/arm/arm.h | 1 +
In the following patches, VirtMachineState and VirtMachineClass will
splited to and deriving ArmMachineState and ArmMachineClass.
This allows sharing code with other arm machine types.
Signed-off-by: Xu Yandong
---
hw/arm/Makefile.objs | 2 +-
hw/arm/arm.c | 77 +
Move fdt and fdt_size member from VirtMachineState to ArmMachineState.
Signed-off-by: Xu Yandong
---
hw/arm/virt.c | 303 ++
include/hw/arm/arm.h | 2 +
include/hw/arm/virt.h | 2 -
3 files changed, 163 insertions(+), 144 deletions(-)
diff --
It's a minimalist machine type without PCI nor ACPI support, designed
for short-lived guests. microvm also establishes a baseline for
benchmarking and optimizing both QEMU and guest operating systems,
since it is optimized for both boot time and footprint.
Signed-off-by: Xu Yandong
---
default-c
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