On Sat, 2020-02-15 at 15:51 +0100, Markus Armbruster wrote:
> Review of this patch led to a lengthy QAPI schema design discussion.
> Let me try to condense it into a concrete proposal.
>
> This is about the QAPI schema, and therefore about QMP. The
> human-friendly interface is out of scope. Not
** Changed in: qemu
Status: Incomplete => Fix Released
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https://bugs.launchpad.net/bugs/1863445
Title:
assertion failed at translate-all.c:2523 with version 3.1.1
Status in QEM
On 2/13/20 2:51 PM, Alex Bennée wrote:
> From: Richard Henderson
>
> While do_gen_mem_cb does copy (via extu_tl_i64) vaddr into a new temp
> this won't help if the vaddr temp gets clobbered by the actual
> load/store op. To avoid this clobbering we explicitly copy vaddr
> before the op to ensure
On 2/13/20 2:51 PM, Alex Bennée wrote:
> Although most people use the docker images this can trip up on
> developer systems with actual valid cross-compilers!
>
> Signed-off-by: Alex Bennée
> ---
> tests/tcg/configure.sh | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richa
On 2/13/20 2:51 PM, Alex Bennée wrote:
> Pointer authentication isn't perfect so measure the percentage of
> failed checks. As we want to vary the pointer that is authenticated we
> recurse down the stack.
>
You're no longer recursing.
> Signed-off-by: Alex Bennée
> ---
> tests/tcg/aarch64/pau
On 2/14/20 12:46 AM, Mark Cave-Ayland wrote:
> Remove the call to pci_cmd646_ide_init() since global device init functions
> are deprecated in preference of using qdev directly.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/alpha/dp264.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deleti
On 2/14/20 12:46 AM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/ide/cmd646.c | 12
> include/hw/ide.h | 2 --
> 2 files changed, 14 deletions(-)
Reviewed-by: Richard Henderson
r~
From: Richard Henderson
It is, after all, just two instructions.
Profiling on a cortex-a15, using -d nochain to increase the number
of exit_tb that are executed, shows a minor improvement of 0.5%.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 12 ++--
1 file changed,
From: Richard Henderson
v1: http://patchwork.ozlabs.org/patch/1176721/
v2 splits the patch in half, as requested by Phil.
r~
Richard Henderson (2):
tcg/arm: Split out tcg_out_epilogue
tcg/arm: Expand epilogue inline
tcg/arm/tcg-target.inc.c | 29 -
1 file cha
From: Richard Henderson
We will shortly use this function from tcg_out_op as well.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index ff
Yes to both.
** Changed in: qemu
Status: New => In Progress
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
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T
RAS Virtualization feature is not supported now, so add a RAS machine
option and disable it by default.
Reviewed-by: Peter Maydell
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Jonathan Cameron
---
hw/arm/virt.c | 23 +++
include/hw/arm/virt.h
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
When guest accesses the poisoned memory, it will generate a Synchronous
Ext
kvm_hwpoison_page_add() and kvm_unpoison_all() will both
be used by X86 and ARM platforms, so moving them into
"accel/kvm/kvm-all.c" to avoid duplicate code.
For architectures that don't use the poison-list functionality
the reset handler will harmlessly do nothing, so let's register
the kvm_unpoi
The little end UUID is used in many places, so make
NVDIMM_UUID_LE to a common macro to convert the UUID
to a little end array.
Signed-off-by: Dongjiu Geng
Reviewed-by: Xiang Zheng
---
hw/acpi/nvdimm.c| 8 ++--
include/qemu/uuid.h | 5 +
2 files changed, 7 insertions(+), 6 deletions
Record the GHEB address via fw_cfg file, when recording
a error to CPER, it will use this address to find out
Generic Error Data Entries and write the error.
In order to avoid migration failure, make hardware
error table address to a part of GED device instead
of global variable, then this address
Add APEI/GHES detailed design document
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Igor Mammedov
---
docs/specs/acpi_hest_ghes.rst | 110 ++
docs/specs/index.rst | 1 +
2 files changed,
This patch builds Hardware Error Source Table(HEST) via fw_cfg blobs.
Now it only supports ARMv8 SEA, a type of Generic Hardware Error
Source version 2(GHESv2) error source. Afterwards, we can extend
the supported types if needed. For the CPER section, currently it
is memory section because kernel
This patch builds error_block_address and read_ack_register fields
in hardware errors table , the error_block_address points to Generic
Error Status Block(GESB) via bios_linker. The max size for one GESB
is 1kb in bytes, For more detailed information, please refer to
document: docs/specs/acpi_hest_
In the ARMv8 platform, the CPU error types includes synchronous external
abort(SEA)
and SError Interrupt (SEI). If exception happens in guest, host does not know
the
detailed information of guest, so it is expected that guest can do the recovery.
For example, if an exception happens in a guest us
I and Xiang are willing to review the APEI-related patches and
volunteer as the reviewers for the HEST/GHES part.
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S. Tsirkin
---
MAINTAINERS | 9 +
1 file changed, 9 insertions
kvm_arch_on_sigbus_vcpu() error injection uses source_id as
index in etc/hardware_errors to find out Error Status Data
Block entry corresponding to error source. So supported source_id
values should be assigned here and not be changed afterwards to
make sure that guest will write error into expecte
Hi Gavin,
On 2020-02-14 05:59, Gavin Shan wrote:
This supports SError injection, which will be used by "virt" board to
simulating the behavior of NMI injection in next patch. As Peter
Maydell
suggested, this adds a new interrupt (ARM_CPU_SERROR), which is
parallel
to CPU_INTERRUPT_HARD. The b
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same su
Signed-off-by: John Arbuckle
---
v3 changes:
- Updated the location of patched code in hw/ppc/kconfig.
- Removed setting the props variable in screamer.c.
- Removed the screamer_properties variable in screamer.c.
v2 changes:
- Fixed a bug that prevented the sampling rate from being changed.
hw/
On Sunday, February 16, 2020, Paolo Bonzini wrote:
> On 16/02/20 07:57, James Hogan wrote:
> >> We are in the process of handling this within the company, and this
> >> patch should go via MIPS tree, not trivial tree - will be updated when
> >> the opinions are crystallized, and all consultations
Public bug reported:
Based on commit b29c3e23f64938784c42ef9fca896829e3c19120,
QEMU configured with --enable-debug --extra-cflags=-ggdb.
Download Raspberry Pi 3 UEFI Firmware v1.15 from:
https://github.com/pbatard/RPi3/releases/tag/v1.15
(unzip RPi3_UEFI_Firmware_v1.15.zip)
Run QEMU with:
$ qem
On Fri, 14 Feb 2020 at 19:37, Eric Auger wrote:
>
> This series adds the capability to instantiate an MMIO TPM TIS
> in ARM virt.
>
> The existing TPM TIS code is reshuffled into a generic part,
> the ISA device and the sysbus device. The last patch allows
> the instantiation of the TPM TIS sysbus
This test runs Trusted Firmware-A on the Raspberry Pi 3.
We deliberately stop the boot process when the EDK2 UEFI version
is displayed.
The binary is build on AppVeyor CI using Pete Batard repository [1].
ATF v2.1 binary are used (see [2]).
It is very simple and fast:
$ avocado --show=app,cons
Maybe the same problem we had with U-boot, the SoC starts with only 1
core enabled.
I'm now trying with `-global bcm2836.enabled-cpus=1`.
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Title:
On 2/14/20 1:36 PM, Eric Auger wrote:
As we plan to introduce a sysbus TPM_TIS, let's rename
TPM_TIS into TPM_TIS_ISA.
Reviewed-by: Stefan Berger
Signed-off-by: Eric Auger
---
hw/i386/acpi-build.c | 6 +++---
hw/tpm/tpm_tis.c | 4 ++--
include/sysemu/tpm.h | 6 +++---
3 files change
On 2/14/20 1:37 PM, Eric Auger wrote:
As we plan to introdce a SysBus TPM TIS device, let's
make the TPMState a common struct usable by both the
ISADevice and the SysBusDevice. TPMStateISA embeds the
struct and inherits from the ISADevice.
The prototype of functions bound to be used by both
the
On 2/14/20 1:37 PM, Eric Auger wrote:
Move the device agnostic code into tpm_tis_common.c and
put the ISA device specific code into tpm_tis_isa.c
Signed-off-by: Eric Auger
Reviewed-by: Stefan Berger
---
hw/tpm/Makefile.objs | 2 +-
hw/tpm/tpm_tis.h
On 2/14/20 1:37 PM, Eric Auger wrote:
Introduce the tpm-tis-device which is a sysbus device
and is bound to be used on ARM.
Signed-off-by: Eric Auger
---
hw/tpm/Kconfig | 5 ++
hw/tpm/Makefile.objs| 1 +
hw/tpm/tpm_tis_sysbus.c | 159
On 2/14/20 1:37 PM, Eric Auger wrote:
Let the TPM TIS SYSBUS device be dynamically instantiable
in ARM virt. A device tree node is dynamically created
(TPM via MMIO).
The TPM Physical Presence interface (PPI) is not supported.
To run with the swtmp TPM emulator, the qemu command line must
be a
5:23 PM Sub, 15.02.2020. Philippe Mathieu-Daudé је
написао/ла:
>
> User-mode does not need the sytem tools. Do not build them by
> default if user specified --disable-system.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> configure | 11 ++-
> 1 file changed, 10 insertions(+), 1 delet
Public bug reported:
Segmentation fault when trying to start FreeBSD-arm system with qemu-
system-arm (version 4.1.1 on Fedora 31)
Commandline:
gdb -q --args /bin/qemu-system-arm \
-name FreeBSD12,debug-threads=on \
-m 1536 -machine virt -smp 2 \
-M virt,highmem=off -serial mon:stdio -monitor
On Sat, Feb 15, 2020 at 04:47:05PM +0100, Philippe Mathieu-Daudé wrote:
> In commit f3a508eb4e the Euler Robot reported calling timer_new()
> in instance_init() can leak heap memory. The easier fix is to
> delay the timer creation at instance realize(). Similarly move
> timer_del() into a new insta
The psuedocode in aarch64/functions/pac/auth/Auth and
aarch64/functions/pac/strip/Strip always uses bit 55 for
extfield and do not consider if the current regime has 2 ranges.
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/pauth_helper.c | 3 ++-
1 file changed, 2 i
For the purpose of rebuild_hflags_a64, we do not need to compute
all of the va parameters, only tbi. Moreover, we can compute them
in a form that is more useful to storing in hflags.
This eliminates the need for aa64_va_parameter_both, so fold that
in to aa64_va_parameter. The remaining calls to
Something I noticed while developing and testing VHE.
For v2, fix select as a separate patch.
For v3, adjust pauth to use bit 55 explicitly, and remove a
now duplicate test within get_phys_addr_lpae.
r~
Richard Henderson (4):
target/arm: Use bit 55 explicitly for pauth
target/arm: Fix sele
Now that aa64_va_parameters_both sets select based on the number
of ranges in the regime, the ttbr1_valid check is redundant.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.
Select should always be 0 for a regime with one range.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 46 +++--
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.
On Sun, Feb 16, 2020 at 5:32 PM John Arbuckle
wrote:
> Signed-off-by: John Arbuckle
> ---
> v3 changes:
> - Updated the location of patched code in hw/ppc/kconfig.
> - Removed setting the props variable in screamer.c.
> - Removed the screamer_properties variable in screamer.c.
>
> v2 changes:
>
On Sun, 16 Feb 2020 at 19:43, Richard Henderson
wrote:
>
> The psuedocode in aarch64/functions/pac/auth/Auth and
> aarch64/functions/pac/strip/Strip always uses bit 55 for
> extfield and do not consider if the current regime has 2 ranges.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Richard H
On Sat, Feb 15, 2020 at 05:15:55PM +0100, Philippe Mathieu-Daudé wrote:
Fix warning reported by Clang static code analyzer:
CC block/qcow2-bitmap.o
block/qcow2-bitmap.c:650:5: warning: Value stored to 'ret' is never read
ret = -EINVAL;
^ ~~~
Reported-by: Clang Static
On Wed, 12 Feb 2020 at 17:30, Palmer Dabbelt wrote:
>
> The following changes since commit 81a23caf47956778c5a5056ad656d1ef92bf9659:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2020-02-10 17:08:51 +)
>
> are available in the Git repository at:
On Sat, Feb 15, 2020 at 05:07:14PM +0100, Philippe Mathieu-Daudé wrote:
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/passthrough_ll.o
tools/virtiofsd/passthrough_ll.c:1083:5: warning: Value stored to 'saverr' is
never read
saverr = ENOMEM;
^~
On Sat, Feb 15, 2020 at 05:07:15PM +0100, Philippe Mathieu-Daudé wrote:
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/passthrough_ll.o
tools/virtiofsd/passthrough_ll.c:925:9: warning: Value stored to 'newfd' is
never read
newfd = -1;
^ ~
On Sat, Feb 15, 2020 at 05:07:16PM +0100, Philippe Mathieu-Daudé wrote:
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/fuse_lowlevel.o
tools/virtiofsd/fuse_lowlevel.c:195:9: warning: Value stored to 'error' is
never read
error = -ERANGE;
^
The cpu env struct is quite complex but comments supposed to explain
it in its definition just make it harder to read. Reformat and reword
some comments to make it clearer and more readable.
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h | 145 ++-
Move fp_status and fpscr closer to other floating point and vector
related members in cpu env definition so they are in one group.
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
i
Just some small clean ups to improve readability of struct CPUPPCState.
BALATON Zoltan (2):
target/ppc/cpu.h: Move fpu related members closer in cpu env
target/ppc/cpu.h: Clean up comments in the struct CPUPPCState
definition
target/ppc/cpu.h | 146 ++-
The gvec form will be needed for implementing SVE2.
Extend the implementation to operate on uint64_t instead of uint32_t.
Use a counted inner loop instead of terminating when op1 goes to zero,
looking toward the required implementation for ARMv8.4-DIT.
Tested-by: Alex Bennée
Reviewed-by: Alex Be
Changes for v2:
* Rename function arguments as requested by ajb.
* Minor optimization in helper_gvec_pmul_b.
Original blurb:
The first patch has been seen before.
https://patchwork.ozlabs.org/patch/1115039/
It had a bug and I didn't fix it right away and then forgot.
Fixed now; I had mixed u
The gvec form will be needed for implementing SVE2.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 4 +---
target/arm/neon_helper.c | 30 --
target/arm/translate-a64.c | 28 +++
These instructions shift left or right depending on the sign
of the input, and 7 bits are significant to the shift. This
requires several masks and selects in addition to the actual
shifts to form the complete answer.
That said, the operation is still a small improvement even for
two 64-bit eleme
We still need two different helpers, since NEON and SVE2 get the
inputs from different locations within the source vector. However,
we can convert both to the same internal form for computation.
The sve2 helper is not used yet, but adding it with this patch
helps illustrate why the neon changes a
On Fri, Feb 14, 2020 at 09:08:07PM +0100, Kevin Wolf wrote:
The bytes_written variable is only ever written to, it serves no
purpose. This has actually been the case since the commit job was first
introduced in commit 747ff602636.
Signed-off-by: Kevin Wolf
---
block/commit.c | 2 --
1 file chang
On Fri, Feb 14, 2020 at 09:08:08PM +0100, Kevin Wolf wrote:
The block_job_error_action() error call in the commit job gives the
on_err and is_read arguments in the wrong order. Fix this.
(Of course, hard-coded is_read = false is wrong, too, but that's a
separate problem for a separate patch.)
S
On Fri, Feb 14, 2020 at 09:08:06PM +0100, Kevin Wolf wrote:
It is not obvious what 'ignore' actually means for block jobs: It could
be continuing the job and returning success in the end despite the error
(no block job does this). It could also mean continuing and returning
failure in the end (th
On Fri, Feb 14, 2020 at 09:08:10PM +0100, Kevin Wolf wrote:
block_job_error_action() needs to know if reading from the top node or
writing to the base node failed so that it can set the right 'operation'
in the BLOCK_JOB_ERROR QMP event.
Signed-off-by: Kevin Wolf
---
block/commit.c | 7 ++-
On Fri, Feb 14, 2020 at 09:08:11PM +0100, Kevin Wolf wrote:
Now that the error handling in the common block job is fixed, we can
expose the on-error option in QMP instead of hard-coding it as 'report'
in qmp_block_commit().
This fulfills the promise that the old comment in that function made,
ev
On Fri, Feb 14, 2020 at 09:08:09PM +0100, Kevin Wolf wrote:
commit_populate() is a very short function and only called in a single
place. Its return value doesn't tell us whether an error happened while
reading or writing, which would be necessary for sending the right data
in the BLOCK_JOB_ERROR
On Sun, 16 Feb 2020, Howard Spoelstra wrote:
On Sun, Feb 16, 2020 at 5:32 PM John Arbuckle
wrote:
diff --git a/hw/audio/screamer.c b/hw/audio/screamer.c
new file mode 100644
index 00..ad4aba12eb
--- /dev/null
+++ b/hw/audio/screamer.c
@@ -0,0 +1,983 @@
+/*
+ * File: Screamer.c
+ * Descr
Patchew URL:
https://patchew.org/QEMU/20200216214232.4230-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v2 0/4] target/arm vector improvements
Message-id: 20200216214232.4230-1-richard.hender...
On Sun, Feb 16, 2020 at 10:33:54PM +0100, BALATON Zoltan wrote:
> Just some small clean ups to improve readability of struct CPUPPCState.
Applied to ppc-for-5.0, thanks.
> BALATON Zoltan (2):
> target/ppc/cpu.h: Move fpu related members closer in cpu env
> target/ppc/cpu.h: Clean up comments
On Sun, Feb 16, 2020 at 05:33:44PM +0100, Aleksandar Markovic wrote:
> OK, I will add the patch in the next MIPS queue, since I think its
> significance is more than trivial. It will be sent no later than two weeks
> from now.
Thanks Aleksandar.
> I just wanted the patch to be in the same queue w
Public bug reported:
Head at commit b29c3e23f64938.
Running with '-d unimp,guest_errors -trace nvic\*' I get:
8871@1581892794.295746:nvic_sysreg_read NVIC sysreg read addr 0xd88 data
0xf0 size 4
8871@1581892794.295752:nvic_sysreg_write NVIC sysreg write addr 0xd88 data
0xf0 size 4
8871
I am not sure this register can not be accessed differently than 32-bit.
Still I used this patch as a kludge, but it doesn't seem a clean fix:
-- >8 --
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2160,6 +2161,10 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr
addr,
On 2/16/20 2:41 PM, Richard Henderson wrote:
On 2/13/20 9:59 PM, Gavin Shan wrote:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b0762a76c4..180e29fb83 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -78,7 +78,7 @@ static bool arm_cpu_has_work(CPUState *cs)
&& cs->inte
** Changed in: qemu
Status: New => Incomplete
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Title:
qemu-system-arm stops with SIGSEGV in helper_gvec_eq16
Status in QEMU:
In Progre
I infer from the traceback that your host does not support AVX1.
** Changed in: qemu
Status: Incomplete => In Progress
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
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On Sat, Feb 15, 2020 at 09:30:56AM +0800, Pan Nengyuan wrote:
>
>
> On 2/14/2020 11:48 PM, Greg Kurz wrote:
> > On Fri, 14 Feb 2020 11:32:06 +0800
> > wrote:
> >
> >> From: Pan Nengyuan
> >>
> >> 'fdt' forgot to clean both e500 and pnv when we call 'system_reset' on ppc,
> >> this patch fix it
On Fri, Feb 14, 2020 at 04:01:16PM +0100, Greg Kurz wrote:
> While working on getting rid of CAS reboot, I realized that we currently
> don't handle device hot unplug properly in the following situations:
>
> 1) if the device is unplugged between boot and CAS, SLOF doesn't handle
>the even, wh
On Sun, Feb 16, 2020 at 8:27 PM Aleksandar Markovic
wrote:
>
> 5:23 PM Sub, 15.02.2020. Philippe Mathieu-Daudé је
> написао/ла:
> >
> > User-mode does not need the sytem tools. Do not build them by
> > default if user specified --disable-system.
> >
> > Signed-off-by: Philippe Mathieu-Daudé
> >
On Sat, Feb 15, 2020 at 10:01 PM Aleksandar Markovic
wrote:
> 9:56 PM Sub, 15.02.2020. Philippe Mathieu-Daudé
> је написао/ла:
> > On Fri, Feb 14, 2020 at 12:04 AM Aleksandar Markovic
> > wrote:
> > >
> > > 6:59 PM Čet, 13.02.2020. Peter Maydell је
> > > написао/ла:
> > > >
> > > > The ascii-
> On Feb 16, 2020, at 4:59 PM, BALATON Zoltan wrote:
>
> On Sun, 16 Feb 2020, Howard Spoelstra wrote:
>> On Sun, Feb 16, 2020 at 5:32 PM John Arbuckle
>> wrote:
>>> diff --git a/hw/audio/screamer.c b/hw/audio/screamer.c
>>> new file mode 100644
>>> index 00..ad4aba12eb
>>> --- /dev/nul
> On Feb 16, 2020, at 2:57 PM, Howard Spoelstra wrote:
>
>
>
>
> On Sun, Feb 16, 2020 at 5:32 PM John Arbuckle
> wrote:
> Signed-off-by: John Arbuckle
> ---
> v3 changes:
> - Updated the location of patched code in hw/ppc/kconfig.
> - Removed setting the props variable in screamer.c.
> -
Split checkpoint incoming process into a helper.
Signed-off-by: Hailiang Zhang
---
migration/colo.c | 260 ---
1 file changed, 133 insertions(+), 127 deletions(-)
diff --git a/migration/colo.c b/migration/colo.c
index 2c88aa57a2..93c5a452fb 100644
---
Hi,
This is an untested serial that tries to reduce VM's pause time
while do checkpoint in COLO state.
The second patch tries to reduce the total number of dirty pages
while do checkpoint with VM been paused, instead of sending all
dirty pages while VM been pause, it sends part of dirty pages dur
This patch will reduce the downtime of VM for the initial process,
Privously, we copied all these memory in preparing stage of COLO
while we need to stop VM, which is a time-consuming process.
Here we optimize it by a trick, back-up every page while in migration
process while COLO is enabled, thoug
We can migrate some dirty pages during the gap of checkpointing,
by this way, we can reduce the amount of ram migrated during checkpointing.
Signed-off-by: Hailiang Zhang
---
migration/colo.c | 69 +++---
migration/migration.h | 1 +
migration/trace-ev
kvm_hwpoison_page_add() and kvm_unpoison_all() will both
be used by X86 and ARM platforms, so moving them into
"accel/kvm/kvm-all.c" to avoid duplicate code.
For architectures that don't use the poison-list functionality
the reset handler will harmlessly do nothing, so let's register
the kvm_unpoi
In the ARMv8 platform, the CPU error types includes synchronous external
abort(SEA)
and SError Interrupt (SEI). If exception happens in guest, host does not know
the
detailed information of guest, so it is expected that guest can do the recovery.
For example, if an exception happens in a guest us
The little end UUID is used in many places, so make
NVDIMM_UUID_LE to a common macro to convert the UUID
to a little end array.
Signed-off-by: Dongjiu Geng
Reviewed-by: Xiang Zheng
---
hw/acpi/nvdimm.c| 8 ++--
include/qemu/uuid.h | 5 +
2 files changed, 7 insertions(+), 6 deletions
RAS Virtualization feature is not supported now, so add a RAS machine
option and disable it by default.
Reviewed-by: Peter Maydell
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Jonathan Cameron
---
hw/arm/virt.c | 23 +++
include/hw/arm/virt.h
This patch builds error_block_address and read_ack_register fields
in hardware errors table , the error_block_address points to Generic
Error Status Block(GESB) via bios_linker. The max size for one GESB
is 1kb in bytes, For more detailed information, please refer to
document: docs/specs/acpi_hest_
Add APEI/GHES detailed design document
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Igor Mammedov
---
docs/specs/acpi_hest_ghes.rst | 110 ++
docs/specs/index.rst | 1 +
2 files changed,
Record the GHEB address via fw_cfg file, when recording
a error to CPER, it will use this address to find out
Generic Error Data Entries and write the error.
In order to avoid migration failure, make hardware
error table address to a part of GED device instead
of global variable, then this address
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
When guest accesses the poisoned memory, it will generate a Synchronous
Ext
This patch builds Hardware Error Source Table(HEST) via fw_cfg blobs.
Now it only supports ARMv8 SEA, a type of Generic Hardware Error
Source version 2(GHESv2) error source. Afterwards, we can extend
the supported types if needed. For the CPER section, currently it
is memory section because kernel
I and Xiang are willing to review the APEI-related patches and
volunteer as the reviewers for the HEST/GHES part.
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S. Tsirkin
---
MAINTAINERS | 9 +
1 file changed, 9 insertions
kvm_arch_on_sigbus_vcpu() error injection uses source_id as
index in etc/hardware_errors to find out Error Status Data
Block entry corresponding to error source. So supported source_id
values should be assigned here and not be changed afterwards to
make sure that guest will write error into expecte
Hi Daniel,
I have rebased these patches with newest upstream version, this series
“Optimize VM's downtime while do checkpoint in COLO”,
It is not been tested, please let me known if there are any problems.
Thanks,
Hailiang
From: Daniel Cho [mailto:daniel...@qnap.com]
Sent: Saturday, February 15
Hi!
We have a SLOF repo mirrored at git.qemu.org. Once I push an update to
my github repo, it gets mirrored soon, it works fine.
Now to the problems :)
1. by accident I pushed a branch with a lot of debug stuff on top. When
I noticed, I force-pushed the correct one but it was too late - the
inco
On 17/02/2020 12:27, Alexey Kardashevskiy wrote:
> Hi!
>
> We have a SLOF repo mirrored at git.qemu.org. Once I push an update to
> my github repo, it gets mirrored soon, it works fine.
>
> Now to the problems :)
>
> 1. by accident I pushed a branch with a lot of debug stuff on top. When
> I
Patchew URL:
https://patchew.org/QEMU/20200217012737.30231-1-gengdong...@huawei.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
The following changes since commit 05943fb4ca41f626078014c0327781815c6584c5:
ppc: free 'fdt' after reset the machine (2020-02-17 11:27:23 +1100)
are available in the Git repository at:
g...@github.com:aik/qemu.git tags/qemu-slof-20200217
for you to fetch changes up to ea9a03e5aa023c5391bab5
On Mon, Feb 17, 2020 at 01:12:17PM +1100, Alexey Kardashevskiy wrote:
> The following changes since commit 05943fb4ca41f626078014c0327781815c6584c5:
>
> ppc: free 'fdt' after reset the machine (2020-02-17 11:27:23 +1100)
>
> are available in the Git repository at:
>
> g...@github.com:aik/qem
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