On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
>
> The board revision encode the board version. Add a helper
> to extract the version, and use it.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/raspi.c | 31 +++
> 1 file changed, 27 insertions(+)
On Wed, 12 Feb 2020 at 16:18, Gerd Hoffmann wrote:
>
> The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
>
> Merge remote-tracking branch
> 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging
> (2020-02-10 18:09:14 +)
>
> are available in the Git r
On Tue, Feb 11, 2020 at 03:35:09PM -0500, Alexander Bulekov wrote:
> diff --git a/tests/qtest/fuzz/virtio_scsi_fuzz.c
> b/tests/qtest/fuzz/virtio_scsi_fuzz.c
> new file mode 100644
> index 00..f62f512a26
> --- /dev/null
> +++ b/tests/qtest/fuzz/virtio_scsi_fuzz.c
> @@ -0,0 +1,214 @@
> +/*
From: miaoyubo
Currently pxb-pcie is not supported by arm and only one
main host bridge is described in acpi tables, which means
it is not impossible to present different io numas for different
devices. This series of patches make arm to support PXB-PCIE.
Users can configure pxb-pcie with certai
** Tags added: ikeradar
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1805256
Title:
qemu-img hangs on rcu_call_ready_event logic in Aarch64 when
converting images
Status in kunpeng920:
Incomp
From: miaoyubo
Since devices could not directly plugged into pxb-pcie, under arm, one
pcie-root port is plugged into pxb-pcie. Due to the bus for each pxb-pcie
is defined as 2 in acpi dsdt tables(one for pxb-pcie, one for pcie-root-port),
only one device could be plugged into one pxb-pcie.
Signe
From: miaoyubo
Currently virt machine is not supported by pxb-pcie,
and only one main host bridge described in ACPI tables.
Under this circumstance, different io numas for differnt devices
is not possible, in order to present io numas to the guest,
especially for host pssthrough devices. PXB-PCIE
On Wed, Feb 12, 2020 at 11:31:00PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/12/20 4:34 PM, Stefan Hajnoczi wrote:
> > On Tue, Feb 11, 2020 at 11:10:54AM +, Alex Bennée wrote:
> > > Otherwise any -D settings the user may have made get ignored.
> > >
> > > Signed-off-by: Alex Bennée
> > > --
Hi Peter, Michael,
On 2/11/20 6:31 PM, Auger Eric wrote:
> Hi Peter,
>
> On 2/11/20 4:00 PM, Peter Maydell wrote:
>> On Sat, 8 Feb 2020 at 12:01, Eric Auger wrote:
>>>
>>> Adds the "virtio,pci-iommu" node in the host bridge node and
>>> the RID mapping, excluding the IOMMU RID.
>>>
>>> This is d
On Tue, 14 Jan 2020 at 10:20 Stefan Hajnoczi
wrote:
> On Fri, Jan 10, 2020 at 10:34 AM Marc-André Lureau
> wrote:
> > On Wed, Jan 8, 2020 at 5:57 AM V. wrote:
>
> Hi V.,
> I think I remember you from Etherboot/gPXE days :).
>
> > > 3.
> > > Now if Cross Cable is actually a new and (after a code
On Thu, Feb 13, 2020 at 03:49:52PM +0800, Yubo Miao wrote:
> From: miaoyubo
>
> Since devices could not directly plugged into pxb-pcie, under arm, one
> pcie-root port is plugged into pxb-pcie. Due to the bus for each pxb-pcie
> is defined as 2 in acpi dsdt tables(one for pxb-pcie, one for pcie-r
On 2/13/20 2:40 PM, Peter Maydell wrote:
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
The board revision encode the board version. Add a helper
to extract the version, and use it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 31 +++
On Thu, Feb 13, 2020 at 06:47:10AM -0600, Eric Blake wrote:
> On 2/13/20 2:01 AM, Roman Kagan wrote:
> > On Wed, Feb 12, 2020 at 03:44:19PM -0600, Eric Blake wrote:
> > > On 2/11/20 5:54 AM, Roman Kagan wrote:
> > > > Devices (virtio-blk, scsi, etc.) and the block layer are happy to use
> > > > 32-
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
>
> With the exception of the ignore_memory_transaction_failures
> flag set for the raspi2, both machine_class_init() methods
> are now identical. Merge them to keep a unique method.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/a
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
>
> Hi,
>
> This series is a preparatory to easily add the raspi0/raspi1/raspi4
> boards (see [1]).
>
> Igor has been working in his "refactor main RAM allocation to use
> hostmem backend" series, and now v4 [2] is almost reviewed.
>
> His
"Dr. David Alan Gilbert" writes:
> * Juan Quintela (quint...@redhat.com) wrote:
>> Signed-off-by: Juan Quintela
>> ---
>> migration/migration.c | 15 +++
>> monitor/hmp-cmds.c| 4
>> qapi/migration.json | 29 ++---
>> 3 files changed, 45 insertion
On 2/13/20 2:59 PM, Peter Maydell wrote:
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
With the exception of the ignore_memory_transaction_failures
flag set for the raspi2, both machine_class_init() methods
are now identical. Merge them to keep a unique method.
Signed-off-by: Phi
QEMU has a funny new build error message when I use the upstream kernel headers:
CC block/file-posix.o
In file included from /home/cborntra/REPOS/qemu/include/qemu/timer.h:4,
from /home/cborntra/REPOS/qemu/include/qemu/timed-average.h:29,
from /home/cborntr
This patch adds tests for following 14 implemented alsa timer ioctls:
* SNDRV_TIMER_IOCTL_PVERSION* SNDRV_TIMER_IOCTL_INFO
* SNDRV_TIMER_IOCTL_NEXT_DEVICE * SNDRV_TIMER_IOCTL_PARAMS
* SNDRV_TIMER_IOCTL_TREAD * SNDRV_TIMER_IOCTL_STATUS
* SNDRV_TIMER_IOCTL_GINFO * SND
This series covers tests for implemented rtc and alsa timer ioctls. The names
of ioctls that are covered by these tests can be found in patch descriptions.
The functionalities of each ioctl that is tested can be found in patches that
implement them.
Some of the features that are accessible through
This patch adds tests for following 22 implemented rtc ioctls:
* RTC_AIE_ON * RTC_ALM_SET * RTC_WKALM_SET
* RTC_AIE_OFF* RTC_ALM_READ * RTC_WKALM_RD
* RTC_UIE_ON * RTC_RD_TIME * RTC_PLL_GET
* RTC_UIE_OFF* RTC_SET_TIME * RTC_PLL_SET
* RTC_PIE_ON * RTC_IRQP_READ
On 2/13/20 1:51 AM, Paolo Bonzini wrote:
On 13/02/20 08:40, Alexey Kardashevskiy wrote:
memory-region: system
- (prio 0, i/o): system
-01ff (prio 0, romd): omap_sx1.flash0-1
-01ff (prio 0, ro
* Markus Armbruster (arm...@redhat.com) wrote:
> "Dr. David Alan Gilbert" writes:
>
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> Signed-off-by: Juan Quintela
> >> ---
> >> migration/migration.c | 15 +++
> >> monitor/hmp-cmds.c| 4
> >> qapi/migration.json | 29
Eduardo Habkost writes:
> On Wed, Feb 12, 2020 at 08:39:55AM +0100, Philippe Mathieu-Daudé wrote:
>> Cc'ing Eduardo & Markus.
>>
>> On 2/12/20 7:44 AM, Chenqun (kuhn) wrote:
>> > > -Original Message-
>> > > From: Philippe Mathieu-Daudé [mailto:phi...@redhat.com]
>> > > Sent: Wednesday, F
On Thu, Feb 13, 2020 at 02:40:45AM +, Liu, Yi L wrote:
> > From: Peter Xu
> > Sent: Wednesday, February 12, 2020 5:57 AM
> > To: Liu, Yi L
> > Subject: Re: [RFC v3 14/25] intel_iommu: add virtual command capability
> > support
> >
> > On Wed, Jan 29, 2020 at 04:16:45AM -0800, Liu, Yi L wrot
On Thu, 13 Feb 2020 at 14:16, Philippe Mathieu-Daudé wrote:
> On 2/13/20 2:59 PM, Peter Maydell wrote:
> > The natural way to implement this is to have the .class_data
> > be a pointer to a struct which is in an array and defines
> > relevant per-class stuff, the same way we do in
> > bcm2836_regi
On Thu, 13 Feb 2020 11:58:36 +1100
David Gibson wrote:
> PAPR specifies a kind of odd, paravirtualized PCI bus, which looks to
> the guess mostly like classic PCI, even if some of the individual
> devices on the bus are PCI Express. One consequence of that is that
> virtio-pci devices still defa
On 2020/2/13 16:18, Andrew Jones wrote:
On Thu, Feb 13, 2020 at 03:36:26PM +0800, Ying Fang wrote:
On ARM64 platform, cpu frequency is retrieved via ACPI CPPC.
A virtual cpufreq device based on ACPI CPPC is created to
present cpu frequency info to the guest.
The default frequency is set to h
On Thu, 13 Feb 2020 at 14:26, Guenter Roeck wrote:
> What really puzzles me is that there is no trace output for
> flash data accesses (trace_pflash_data_read and trace_pflash_data_write),
> meaning the actual flash data access must be handled elsewhere.
> Can someone give me a hint where that mig
From: Roman Kapl
Documentation says for WDA '0: Assert WDOG output.' and for SRS
'0: Assert system reset signal.'.
Signed-off-by: Roman Kapl
Message-id: 20200207095409.11227-1-...@sysgo.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/misc/imx2_wdt.c | 2 +-
1 file changed,
tracking branch 'remotes/kraxel/tags/ui-20200212-pull-request'
into staging (2020-02-13 11:06:32 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20200213
for you to fetch changes up to dc7a88d0810ad272bdcd2e0869
From: Richard Henderson
The J bit signals Jazelle mode, and so of course is RES0
when the feature is not enabled.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20200208125816.14954-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/internals.
From: Heyi Guo
We are going to change ARM virt ACPI DSDT table, which will cause make
check to fail, so temporarily add related golden masters to ignore
list.
Signed-off-by: Heyi Guo
Reviewed-by: Michael S. Tsirkin
Message-id: 20200204014325.16279-2-guoh...@huawei.com
Signed-off-by: Peter Mayd
From: Heyi Guo
Using _UID of 0 for all PCI interrupt link devices absolutely violates
the spec. Simply increase one by one.
Signed-off-by: Heyi Guo
Reviewed-by: Michael S. Tsirkin
Message-id: 20200204014325.16279-6-guoh...@huawei.com
Signed-off-by: Peter Maydell
---
hw/arm/virt-acpi-build.c
From: Richard Henderson
CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED.
The function also takes into account bits that the cpu
does not support.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-8-richard.hender...@linaro.org
Signed-off-by: Pe
From: Heyi Guo
The sub device "RP0" under PCI0 in ACPI/DSDT does not contain any
method or property other than "_ADR", so it is safe to remove it.
Signed-off-by: Heyi Guo
Acked-by: "Michael S. Tsirkin"
Reviewed-by: Michael S. Tsirkin
Message-id: 20200204014325.16279-3-guoh...@huawei.com
Signe
From: Richard Henderson
Use a common predicate for querying stage1-ness.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/internals.h | 18
From: Heyi Guo
Differences between disassembled ASL files:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of DSDT, Thu Jan 23 16:00:04 2020
+ * Disassembly of DSDT.new, Thu Jan 23 16:47:12 2020
*
* Original Table Header:
* Signature"DSDT"
From: Roman Kapl
Uses the i.MX2 rudimentary watchdog driver.
Signed-off-by: Roman Kapl
Message-id: 20200207095529.11309-1-...@sysgo.com
Reviewed-by: Peter Maydell
[PMM: removed accidental duplicate #include line]
Signed-off-by: Peter Maydell
---
include/hw/arm/fsl-imx6.h | 3 +++
hw/arm/fsl
From: Richard Henderson
Using ~0 as the mask on the aarch64->aarch32 exception return
was not even as correct as the CPSR_ERET_MASK that we had used
on the aarch32->aarch32 exception return.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-9-richard.
From: Richard Henderson
Include definitions for all of the bits in ID_MMFR3.
We already have a definition for ID_AA64MMFR1.PAN.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-4-richard.hender...@linaro.org
Signed-off-by: P
From: Heyi Guo
The address field in each _PRT mapping package should be constructed
with high word for device# and low word for function#, so it is wrong
to use bus_no as the high word. The existing code adds a bunch useless
entries with device #s above 31. Enumerate all possible slots
(i.e. PCI_
From: Richard Henderson
Examine the PAN bit for EL1, EL2, and Secure EL1 to
determine if it applies.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/
From: Richard Henderson
Use this along the exception return path, where we previously
accepted any values.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/internals.h | 1
From: Richard Henderson
This includes enablement of ARMv8.1-PAN.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.c | 4
target/arm/cpu64.c | 5 +
2 files ch
From: Richard Henderson
If we have a PAN-enforcing mmu_idx, set prot == 0 if user_rw != 0.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/intern
From: Heyi Guo
According to ACPI spec, _ADR should be used for device on a bus that
has a standard enumeration algorithm, but not for device which is on
system bus and must be enumerated by OSPM. And it is not recommended
to contain both _HID and _ADR in a single device.
See ACPI 6.3, section 6.
From: Richard Henderson
For aarch64, there's a dedicated msr (imm, reg) insn.
For aarch32, this is done via msr to cpsr. Writes from el0
are ignored, which is already handled by the CPSR_USER mask.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-12
From: Richard Henderson
We need only override the current condition under which
TBFLAG_A64.UNPRIV is set.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-20-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 41 +++
From: Heyi Guo
The original code defines a named object for the resource template but
then returns the resource template object itself; the resulted output
is like below:
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordB
From: Richard Henderson
This is a minor enhancement over ARMv8.1-PAN.
The *_PAN mmu_idx are used with the existing do_ats_write.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
targe
From: Chen Qun
It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-properties",
"arguments":{"typename":"exynos4210.uart"}}'
ASAN shows memory leak stack:
#1 0xfffd896d71cb in g_malloc0 (/lib64/libglib-2.0.so.0+0x571cb)
#2 0xaaad270beee3 in tim
From: Richard Henderson
Add definitions for all of the fields, up to ARMv8.5.
Convert the existing RESERVED register to a full register.
Query KVM for the value of the register for the host.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-18-richard
From: Richard Henderson
The PAN bit is preserved, or set as per SCTLR_ELx.SPAN,
plus several other conditions listed in the ARM ARM.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20200208125816.14954-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
t
From: Richard Henderson
For static const regdefs, file scope is preferred.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 57 +++--
From: Guenter Roeck
Initialize EHCI controllers on AST2600 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2600-evb
into Linux successfully instantiates a USB interface after
the necessary changes are made to its devicetree files.
ehci_hcd: USB 2.0 'Enhanced' Host Controller
From: Philippe Mathieu-Daudé
There is no point in creating the SoC object before allocating the RAM.
Move the call to keep all the SoC-related calls together.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Igor Mammedov
Message-id: 20200208165645.15657-7-f4...@amsat.org
Reviewed-by: Peter May
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-21-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu64.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu6
From: Richard Henderson
Split this helper out of msr_mask in translate.c. At the same time,
transform the negative reductive logic to positive accumulative logic.
It will be usable along the exception paths.
While touching msr_mask, fix up formatting.
Signed-off-by: Richard Henderson
Reviewed
From: Philippe Mathieu-Daudé
We want to have a common class_init(). The only value that
matters (and changes) is the board revision.
Pass the board_rev as class_data to class_init().
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200208165645.15657-9-f4...@amsat.org
Reviewed-by: Peter Mayd
From: Philippe Mathieu-Daudé
The count of ARM cores is encoded in the board revision. Add a
helper to extract the number of cores, and use it. This will be
helpful when we add the Raspi0/1 that have a single core.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200208165645.15657-14-f4...
From: Philippe Mathieu-Daudé
When booting without device tree, the Linux kernels uses the $R1
register to determine the machine type. The list of values is
registered at [1].
There are two entries for the Raspberry Pi:
- https://www.arm.linux.org.uk/developer/machines/list.php?mid=3138
name:
From: Richard Henderson
To implement PAN, we will want to swap, for short periods
of time, to a different privileged mmu_idx. In addition,
we cannot do this with flushing alone, because the AT*
instructions have both PAN and PAN-less versions.
Add the ARMMMUIdx*_PAN constants where necessary ne
From: Philippe Mathieu-Daudé
QOM'ify RaspiMachineState. Now machines inherit of RaspiMachineClass.
Cc: Igor Mammedov
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Igor Mammedov
Message-id: 20200208165645.15657-8-f4...@amsat.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
From: Philippe Mathieu-Daudé
We hardcode the board revision as 0xa21041 for the raspi2, and
0xa02082 for the raspi3:
166 static void raspi_init(MachineState *machine, int version)
167 {
...
194 int board_rev = version == 3 ? 0xa02082 : 0xa21041;
These revision codes are for the 2B a
From: Richard Henderson
The only remaining use was in op_helper.c. Use PSTATE_SS
directly, and move the commentary so that it is more obvious
what is going on.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20200208125816.14954-10-richard.hender...@linaro.org
Signed-o
The ARMv8.1-VMID16 extension extends the VMID from 8 bits to 16 bits:
* the ID_AA64MMFR1_EL1.VMIDBits field specifies whether the VMID is
8 or 16 bits
* the VMID field in VTTBR_EL2 is extended to 16 bits
* VTCR_EL2.VS lets the guest specify whether to use the full 16 bits,
or use the back
From: Philippe Mathieu-Daudé
The board revision encode the processor type. Add a helper
to extract the type, and use it.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200208165645.15657-6-f4...@amsat.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/raspi.c | 18 ++
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-19-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 6 ++
target/arm/internals.h | 3 +++
target/arm/helper.c| 21 ++
On Wed, 12 Feb 2020 at 16:42, Paolo Bonzini wrote:
>
> The following changes since commit 7bd9d0a9e26c7a3c67c0f174f0009ba19969b158:
>
> Merge remote-tracking branch
> 'remotes/huth-gitlab/tags/pull-request-2020-02-04' into staging (2020-02-04
> 16:12:31 +)
>
> are available in the Git repo
From: Philippe Mathieu-Daudé
The board revision encode the board version. Add a helper
to extract the version, and use it.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200208165645.15657-4-f4...@amsat.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/raspi.c | 31
From: Guenter Roeck
Initialize EHCI controllers on AST2400 and AST2500 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
successfully instantiates a USB interface.
ehci-platform 1e6a3000.usb: EHCI Host Controller
ehci-platform 1e6a3000.usb: new USB bus regi
From: Philippe Mathieu-Daudé
The board revision encode the amount of RAM. Add a helper
to extract the RAM size, and use it.
Since the amount of RAM is fixed (it is impossible to physically
modify to have more or less RAM), do not allow sizes different
than the one anounced by the manufacturer.
A
From: Philippe Mathieu-Daudé
We added a helper to extract the RAM size from the board
revision, and made board_rev a field of RaspiMachineClass.
The class_init() can now use the helper to extract from the
board revision the board-specific amount of RAM.
Signed-off-by: Philippe Mathieu-Daudé
Mes
From: Philippe Mathieu-Daudé
raspi_machine_init() access to board_rev via RaspiMachineClass.
raspi2_init() and raspi3_init() do nothing. Call raspi_machine_init
directly.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Message-id: 20200208165645.15657-10-f4...@amsat.org
Signed
v1:
* seg_max default value changing removed
---
The goal is to reduce the amount of requests issued by a guest on
1M reads/writes. This rises the performance up to 4% on that kind of
disk access pattern.
The maximum chunk size to be used for the guest disk accessing is
limited with seg_max par
From: Philippe Mathieu-Daudé
With the exception of the ignore_memory_transaction_failures
flag set for the raspi2, both machine_class_init() methods
are now identical. Merge them to keep a unique method.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Message-id: 2020020816564
From: Philippe Mathieu-Daudé
The board revision encode the model type. Add a helper
to extract the model, and use it.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200208165645.15657-12-f4...@amsat.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/raspi.c | 18
On Thu, Feb 13, 2020 at 09:31:10AM -0500, Peter Xu wrote:
[...]
> > > Apart of this: also I just noticed (when reading the latter part of
> > > the series) that the time that a pasid table walk can consume will
> > > depend on this value too. I'd suggest to make this as small as we
> > > can, as
On Wed, Jan 08, 2020 at 02:54:30AM +0100, V. wrote:
> Hi List,
>
> For my VM setup I tend to use a lot of VM to VM single network links to do
> routing, switching and bridging in VM's instead of the host.
> Also stemming from a silly fetish to sometimes use some OpenBSD VMs as
> firewall, but th
Thank you for your kind advice. I'll try it.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1862167
Title:
Variation of SVE register size (qemu-user-aarch64)
Status in QEMU:
Invalid
Bug descript
On Thu, Feb 13, 2020 at 02:59:37AM +, Liu, Yi L wrote:
> > - Remove the vtd_pasid_as check right below because it's not needed.
> >
> > >
> > >
> > > > > +if (vtd_pasid_as &&
> >
>
> yes, it is. In current series vtd_add_find_pasid_as() doesn’t check th
On 2/13/20 3:39 PM, Peter Maydell wrote:
On Thu, 13 Feb 2020 at 14:26, Guenter Roeck wrote:
What really puzzles me is that there is no trace output for
flash data accesses (trace_pflash_data_read and trace_pflash_data_write),
meaning the actual flash data access must be handled elsewhere.
Can s
Ping ?
This series fixes actual bugs. Also, I have another patch on top of
that to cold plug (or remove) devices pending hot plug (or unplug)
before CAS, hence removing the need for CAS reboot in these cases.
This requires SLOF to correctly parse the FDT it gets at CAS. Patches
have been sent for
On 2020/1/17 0:44, Peter Maydell wrote:
> On Wed, 8 Jan 2020 at 11:33, Dongjiu Geng wrote:
>>
>> Record the GHEB address via fw_cfg file, when recording
>> a error to CPER, it will use this address to find out
>> Generic Error Data Entries and write the error.
>>
>> Make the HEST GHES to a GED dev
Markus Armbruster wrote:
> "Dr. David Alan Gilbert" writes:
>
>> * Juan Quintela (quint...@redhat.com) wrote:
>>> Signed-off-by: Juan Quintela
>>> ---
>>> migration/migration.c | 15 +++
>>> monitor/hmp-cmds.c| 4
>>> qapi/migration.json | 29 ++--
On 2/13/20 3:32 PM, Peter Maydell wrote:
On Thu, 13 Feb 2020 at 14:16, Philippe Mathieu-Daudé wrote:
On 2/13/20 2:59 PM, Peter Maydell wrote:
The natural way to implement this is to have the .class_data
be a pointer to a struct which is in an array and defines
relevant per-class stuff, the sam
Until the CAS negotiation is over, an HPT can be allocated on three
different paths:
1) during machine reset if the host doesn't support radix,
2) during CAS if the guest wants hash and doesn't support HPT resizing,
in which case we pre-emptively resize the HPT to accomodate maxram,
3) during
Typo 'virtuqueue' in subject.
On 2/13/20 3:59 PM, Denis Plotnikov wrote:
v1:
* seg_max default value changing removed
^^^ This part ...
---
The goal is to reduce the amount of requests issued by a guest on
1M reads/writes. This rises the performance up to 4% on that kind of
disk access p
Its only users are in spapr.c.
Signed-off-by: Greg Kurz
---
I realized just after posting that spapr_reallocate_hpt() didn't need to
be extern anymore. Maybe worth squashing this into the "spapr: Rework
hash<->radix transitions at CAS" patch ?
---
hw/ppc/spapr.c |4 ++--
include/hw/
Patchew URL: https://patchew.org/QEMU/20200213074952.544-1-miaoy...@huawei.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#
On Fri, 7 Feb 2020 at 08:33, Markus Armbruster wrote:
>
> Peter Maydell writes:
>
> > rST format requires a blank line before the start of a bulleted
> > or enumerated list. Two places in qapi-schema.json were missing
> > this blank line.
> >
> > Some places were using an indented line as a sort
On Thu, Feb 13, 2020 at 04:24:24PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/13/20 3:39 PM, Peter Maydell wrote:
> > On Thu, 13 Feb 2020 at 14:26, Guenter Roeck wrote:
> > > What really puzzles me is that there is no trace output for
> > > flash data accesses (trace_pflash_data_read and trace_pf
https://qemu.readthedocs.io/en/latest/index.html collects various
documents from the QEMU docs/ subdirectory; however, none of the
s390 files are currently included. Therefore, I set out to convert
the existing files to rst and hook them up.
s390-dasd-ipl was straightforward enough; I also found a
While at it, also fix the numbering in 'What QEMU does'.
Reviewed-by: Thomas Huth
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 2 +-
docs/devel/index.rst | 1 +
.../{s390-dasd-ipl.txt => s390-dasd-ipl.rst} | 119 +
Move to system/, as this is mostly about configuring vfio-ap.
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 2 +-
docs/system/index.rst| 1 +
docs/{vfio-ap.txt => system/vfio-ap.rst} | 796 ---
3 files changed, 420 inserti
On 2/13/20 3:28 PM, Markus Armbruster wrote:
Eduardo Habkost writes:
On Wed, Feb 12, 2020 at 08:39:55AM +0100, Philippe Mathieu-Daudé wrote:
Cc'ing Eduardo & Markus.
On 2/12/20 7:44 AM, Chenqun (kuhn) wrote:
-Original Message-
From: Philippe Mathieu-Daudé [mailto:phi...@redhat.com]
Daniel P. Berrangé wrote:
> On Thu, Jan 30, 2020 at 09:03:00AM +0100, Markus Armbruster wrote:
>> Juan Quintela writes:
>>
>> > It will indicate which level use for compression.
>> >
>> > Signed-off-by: Juan Quintela
>>
>> This is slightly confusing (there is no zlib compression), unless you
>
On Thu, 13 Feb 2020 at 16:33, Philippe Mathieu-Daudé wrote:
> > * unrealize() must clean up everything realize() creates.
>
> Hmm I guess remember someone once said "only for hot-pluggable objects,
> else don't bother". But then we make a non-hot-pluggable object as
> hot-pluggable and have to fix
> -Original Message-
> From: David Hildenbrand [mailto:da...@redhat.com]
> Sent: 12 February 2020 18:21
> To: Shameerali Kolothum Thodi ;
> Igor Mammedov
> Cc: peter.mayd...@linaro.org; xiaoguangrong.e...@gmail.com;
> m...@redhat.com; shannon.zha...@gmail.com; qemu-devel@nongnu.org;
> xu
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