From: Thomas Huth
Since we can now use a s390x host on Travis, we can also build and
test the s390-ccw bios images there. For this we have to make sure
that roms/SLOF is checked out, too, and then move the generated *.img
files to the right location before running the tests.
Signed-off-by: Thoma
Robert Foley writes:
> Change Makefile.include to use $(PYTHON) so for vm-boot-ssh to be
> consistent with other cases like vm-build.
>
> Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
> ---
> tests/vm/Makefile.include | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
So far we've been converting docs to Sphinx and assigning them
to manuals according to the division originally set out by
Paolo on the wiki: https://wiki.qemu.org/Features/Documentation
* QEMU User-mode Emulation User's Guide (docs/user)
* QEMU System Emulation User's Guide (docs/system)
* QEMU
On Thu, 6 Feb 2020 at 21:21, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> I prepared this series on behalf of Eduardo and
> Cleber (one of them will ack this cover).
>
> Regards,
>
> Phil.
>
> The following changes since commit 418fa86dd465b4fd8394373cf83db8fa65d7611c:
>
> Merge remote-tracki
On Thu, 6 Feb 2020 at 10:54, Richard Henderson
wrote:
>
> Version 7 has one more tweak to the vhe tlb flushing
> that Peter asked for. All patches have reviews.
>
>
Applied to target-arm.next, thanks.
-- PMM
On 1/29/20 7:23 PM, Philippe Mathieu-Daudé wrote:
We don't need the default options to run this test.
This fixes errors when running a binary built with
--without-default-devices such:
ERROR: qemu-system-arm: Unsupported NIC model: virtio-net-pci
If you look at all the other acceptance
> -Original Message-
> From: Richard Henderson
> Sent: Friday, February 7, 2020 2:53 AM
> To: Taylor Simpson ; Richard Henderson
> ; qemu-devel@nongnu.org
> Cc: Paolo Bonzini
> Subject: Re: [PATCH] Add support for a helper with 7 arguments
>
> On 2/7/20 4:46 AM, Taylor Simpson wrote:
>
On Mon, 3 Feb 2020 at 15:41, Rene Stange wrote:
>
> Hi Philippe,
>
> this v2 patch splits the initial fix into two commits as suggested.
>
> Regards,
>
> Rene
>
>
> Rene Stange (2):
> bcm2835_dma: Fix the ylen loop in TD mode
> bcm2835_dma: Re-initialize xlen in TD mode
>
> hw/dma/bcm2835_dma
On Fri, Feb 07, 2020 at 11:50:37AM +, Peter Maydell wrote:
> So far we've been converting docs to Sphinx and assigning them
> to manuals according to the division originally set out by
> Paolo on the wiki: https://wiki.qemu.org/Features/Documentation
>
> * QEMU User-mode Emulation User's Guid
On Fri, Feb 07, 2020 at 11:51:55AM +0100, Auger Eric wrote:
> Hi,
>
> On 2/7/20 11:23 AM, Michael S. Tsirkin wrote:
> > On Fri, Feb 07, 2020 at 10:32:00AM +0100, Eric Auger wrote:
> >> At the moment, the kernel only supports device tree
> >> integration of the virtio-iommu. DT bindings between the
Robert Foley writes:
> Allow wait_ssh to wait for root user to be ready.
> This solves the issue where we perform a wait_ssh()
> successfully, but the root user is not yet ready
> to be logged in.
>
> Signed-off-by: Robert Foley
> ---
> tests/vm/basevm.py | 8 +---
> 1 file changed, 5 ins
Robert Foley writes:
> Add change to increase timeout waiting for VM to boot.
> Needed for some emulation cases where it can take longer
> than 5 minutes to boot.
>
> Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
> ---
> tests/vm/basevm.py | 7 +++
> 1 file changed, 7 insertions
On Tue, 28 Jan 2020 at 19:36, Cornelia Huck wrote:
>
> While at it, also fix the numbering in 'What QEMU does'.
>
> Signed-off-by: Cornelia Huck
> ---
> diff --git a/docs/devel/s390-dasd-ipl.txt b/docs/devel/s390-dasd-ipl.rst
> similarity index 77%
> rename from docs/devel/s390-dasd-ipl.txt
> re
On 1/29/20 7:23 PM, Philippe Mathieu-Daudé wrote:
We don't need the default options to run this test.
This fixes errors when running a binary built with
--without-default-devices such:
ERROR: qemu-system-arm: Unsupported NIC model: virtio-net-pci
Signed-off-by: Philippe Mathieu-Daudé
---
Peter Maydell writes:
> A JSON block comment like this:
> Returns: nothing on success
> If @node is not a valid block device, DeviceNotFound
> If @name is not found, GenericError with an explanation
>
> renders in the HTML and manpage like this:
>
> Returns: nothing on succe
07.02.2020 13:33, Max Reitz wrote:
On 04.02.20 15:23, Eric Blake wrote:
On 2/4/20 7:59 AM, Vladimir Sementsov-Ogievskiy wrote:
I understand that it is safer to have restrictions now and lift them
later, than to allow use of the option at any time and leave room for
the user to shoot themselves
On Tue, Jan 28, 2020 at 11:34:51AM +0100, Eric Auger wrote:
> Allocate the LPI configuration and per re-distributor pending table.
> Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled
> by default in the config table.
>
> Also introduce a helper routine that allows to set the pendin
On 2/5/20 10:41 PM, Taylor Simpson wrote:
> Currently, helpers can only take up to 6 arguments. This patch adds the
> capability for up to 7 arguments. I have tested it with the Hexagon port
> that I am preparing for submission.
>
> Signed-off-by: Taylor Simpson
> ---
> include/exec/helper-gen
On Tue, Jan 28, 2020 at 11:34:52AM +0100, Eric Auger wrote:
> This helper function controls the signaling of LPIs at
> redistributor level.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - move the helper in lib/arm/gic-v3.c
> - rename the function with gicv3_lpi_ prefix
> - s/report_abo
On Fri, Feb 07, 2020 at 01:14:37PM +0100, Andrew Jones wrote:
> On Tue, Jan 28, 2020 at 11:34:52AM +0100, Eric Auger wrote:
> > This helper function controls the signaling of LPIs at
> > redistributor level.
> >
> > Signed-off-by: Eric Auger
> >
> > ---
> >
> > v2 -> v3:
> > - move the helper i
Robert Foley writes:
> This method was located in both centos and ubuntu.i386.
>
> Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
> ---
> tests/vm/basevm.py | 40
> tests/vm/centos | 33 +
> tests/vm/ubun
The following changes since commit 5b7686f3fa2092d2b3be92df67b5966ee1b0142a:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-02-06' into
staging (2020-02-06 18:59:12 +)
are available in the Git repository at:
https://github.com/berrange/qemu tags/misc-fixes-pull-request
From: Jafar Abdi
Clean up wrong usage of FALSE and TRUE in places that use "bool" from stdbool.h.
FALSE and TRUE (with capital letters) are the constants defined by glib for
being used with the "gboolean" type of glib. But some parts of the code also use
TRUE and FALSE for variables that are dec
The default NIC model for QEMU varies per machine type, and is liable to
change across machine type versions. Documenting e1000 NIC as the
default for PC/i386 is thus misleading to users at best. In particular
the PC q35 machine type switched to use e1000e, but only in machine
type versions after 2
From: Yu-Chen Lin
noVNC doesn't use 'binary' protocol by default after
commit c912230309806aacbae4295faf7ad6406da97617.
It will cause qemu return 400 when handshaking.
To overcome this problem and remain compatibility of
older noVNC client.
We treat 'binary' and no sub-protocol as the same
so
On 2/7/20 11:27 AM, Philippe Mathieu-Daudé wrote:
> +default_count += !!mc->is_default;
I'd prefer we simply change mc->is_default to bool.
There's no good reason for it to be type int, afaics.
In the meantime, there are no settings of is_default outside {0,1}, so you
could just drop
Sure. However I would keep qemu-ga in interop/.
Paolo
Il ven 7 feb 2020, 12:50 Peter Maydell ha
scritto:
> So far we've been converting docs to Sphinx and assigning them
> to manuals according to the division originally set out by
> Paolo on the wiki: https://wiki.qemu.org/Features/Documentatio
On 2/7/20 12:51 PM, Peter Maydell wrote:
On Thu, 6 Feb 2020 at 21:21, Philippe Mathieu-Daudé wrote:
Hi Peter,
I prepared this series on behalf of Eduardo and
Cleber (one of them will ack this cover).
Regards,
Phil.
The following changes since commit 418fa86dd465b4fd8394373cf83db8fa65d7611c
On Tue, Jan 28, 2020 at 11:34:53AM +0100, Eric Auger wrote:
> its_enable_defaults() is the top init function that allocates the
> command queue and all the requested tables (device, collection,
> lpi config and pending tables), enable LPIs at distributor level
> and ITS level.
>
> gicv3_enable_def
On Tue, 28 Jan 2020 at 19:39, Cornelia Huck wrote:
>
> Move to system/, as this is mostly about configuring vfio-ap.
>
> Signed-off-by: Cornelia Huck
> diff --git a/docs/vfio-ap.txt b/docs/system/vfio-ap.rst
> similarity index 56%
> rename from docs/vfio-ap.txt
> rename to docs/system/vfio-ap.rs
> -Original Message-
> From: Richard Henderson
>
> But I encourage you to re-think your purely mechanical approach to the
> hexagon
> port. It seems to me that you should be doing much more during the
> translation
> phase so that you can minimize the number of helpers that you require.
On Tue, Jan 28, 2020 at 11:34:54AM +0100, Eric Auger wrote:
> Introduce an helper functions to register
> - a new device, characterized by its device id and the
> max number of event IDs that dimension its ITT (Interrupt
> Translation Table). The function allocates the ITT.
>
> - a new collec
On 2/6/20 3:17 PM, Philippe Mathieu-Daudé wrote:
This test fails on various CI:
What CI(s) you mean?
Afaik the acceptance tests are executed only on Travis
- Using QEMU 4.0:
tests/acceptance/x86_cpu_model_versions.py:X86CPUModelAliases.test_none_alias:
ERROR: 'alias-of' (0.45 s)
On 2/7/20 12:16 AM, Cédric Le Goater wrote:
On 2/6/20 7:34 PM, Guenter Roeck wrote:
Initialize EHCI controllers on AST2400 and AST2500 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
successfully instantiates a USB interface.
ehci-platform 1e6a3000.usb:
Cleanup after reviewing "ppc: function to setup latest class options":
https://www.mail-archive.com/qemu-devel@nongnu.org/msg677709.html
Philippe Mathieu-Daudé (3):
hw: Do not initialize MachineClass::is_default to 0
hw: Make MachineClass::is_default a boolean type
vl: Abort if multiple mach
On 2/7/20 1:58 PM, Guenter Roeck wrote:
> On 2/7/20 12:16 AM, Cédric Le Goater wrote:
>> On 2/6/20 7:34 PM, Guenter Roeck wrote:
>>> Initialize EHCI controllers on AST2400 and AST2500 using the existing
>>> TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
>>> successfully insta
It would be confusing to have multiple default machines.
Abort if this ever occurs.
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Use assert() instead of human friendly message (Marc-André)
Cc: Marc-André Lureau
Cc: Laurent Vivier
---
vl.c | 4
1 file changed, 4 insertions(+)
diff --git
The MachineClass is already zeroed on creation.
Note: The code setting is_default=0 in hw/i386/pc_piix.c is
different (related to compat options). When adding a
new versioned machine, we want it to be the new default,
so we have to mark the previous one as not default.
Signed-of
There's no good reason for it to be type int, change it to bool.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
v3: new patch
---
include/hw/boards.h | 2 +-
hw/alpha/dp264.c | 2 +-
hw/cris/axis_dev88.c
On Fri, 7 Feb 2020 at 12:58, Guenter Roeck wrote:
>
> On 2/7/20 12:16 AM, Cédric Le Goater wrote:
> > On 2/6/20 7:34 PM, Guenter Roeck wrote:
> >> Initialize EHCI controllers on AST2400 and AST2500 using the existing
> >> TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
> >> s
On Tue, Jan 28, 2020 at 11:34:56AM +0100, Eric Auger wrote:
> Triggers LPIs through the INT command.
>
> the test checks the LPI hits the right CPU and triggers
> the right LPI intid, ie. the translation is correct.
>
> Updates to the config table also are tested, along with inv
> and invall comm
On 2020/2/7 1:30, Marc Zyngier wrote:
On 2020-02-06 01:20, Heyi Guo wrote:
Hi Marc,
On 2020/2/5 21:15, Marc Zyngier wrote:
Hi Heyi,
On 2020-02-04 08:26, Heyi Guo wrote:
Update Marc's email address.
+cc Gavin as he is posting a RFC for ARM NMI.
Hi Marc,
Really sorry for missing to update
Cc'ing qemu-block@
On 2/7/20 12:51 PM, Peter Maydell wrote:
On Thu, 6 Feb 2020 at 21:21, Philippe Mathieu-Daudé wrote:
Hi Peter,
I prepared this series on behalf of Eduardo and
Cleber (one of them will ack this cover).
Regards,
Phil.
The following changes since commit 418fa86dd465b4fd8394
On Fri, Feb 7, 2020 at 2:30 PM Philippe Mathieu-Daudé wrote:
>
> Cc'ing qemu-block@
>
> On 2/7/20 12:51 PM, Peter Maydell wrote:
> > On Thu, 6 Feb 2020 at 21:21, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Hi Peter,
> >>
> >> I prepared this series on behalf of Eduardo and
> >> Cleber (one of th
On Fri, 7 Feb 2020 at 08:26, Andrew Jones wrote:
>
> On Thu, Feb 06, 2020 at 11:51:48PM +0100, Philippe Mathieu-Daudé wrote:
> > The bold text sounds like 'knock knock'. Only bolding the
>
> Who's there?
>
> > second 'not' makes it easier to read.
> >
> > Fixes: dea101a1ae
> > Signed-off-by: Phili
Hi Jean,
On 2/7/20 12:15 PM, Jean-Philippe Brucker wrote:
> On Fri, Feb 07, 2020 at 11:51:55AM +0100, Auger Eric wrote:
>> Hi,
>>
>> On 2/7/20 11:23 AM, Michael S. Tsirkin wrote:
>>> On Fri, Feb 07, 2020 at 10:32:00AM +0100, Eric Auger wrote:
At the moment, the kernel only supports device tre
On Tue, Jan 28, 2020 at 11:34:55AM +0100, Eric Auger wrote:
> Implement main ITS commands. The code is largely inherited from
> the ITS driver.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - do not use report() anymore
> - assert if cmd_write exceeds the queue capacity
>
> v1 -> v2:
>
Hi Michael,
On 2/7/20 1:00 PM, Michael S. Tsirkin wrote:
> On Fri, Feb 07, 2020 at 11:51:55AM +0100, Auger Eric wrote:
>> Hi,
>>
>> On 2/7/20 11:23 AM, Michael S. Tsirkin wrote:
>>> On Fri, Feb 07, 2020 at 10:32:00AM +0100, Eric Auger wrote:
At the moment, the kernel only supports device tree
On 2/6/20 7:34 PM, Guenter Roeck wrote:
Initialize EHCI controllers on AST2400 and AST2500 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
successfully instantiates a USB interface.
ehci-platform 1e6a3000.usb: EHCI Host Controller
ehci-platform 1e6a3000.u
On Thu, 6 Feb 2020 at 23:57, Alex Williamson wrote:
>
> The following changes since commit 2021b7c9716cd579e20b4993ed75842f4e0deb34:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2020-02-06
> 12:57:54 +)
>
> are available in the Git rep
On Wed, 5 Feb 2020 at 07:07, wrote:
>
> From: Pan Nengyuan
>
> This series delay timer_new into realize() to fix some memleaks when we call
> 'device-list-properties'.
>
> Pan Nengyuan (3):
> armv7m_systick: delay timer_new to avoid memleaks
> stm32f2xx_timer: delay timer_new to avoid memlea
On 2020/2/7 18:52, James Morse wrote:
Hi guys,
On 06/02/2020 17:30, Marc Zyngier wrote:
On 2020-02-06 01:20, Heyi Guo wrote:
On 2020/2/5 21:15, Marc Zyngier wrote:
My concern is that SDEI implies having EL3. EL3 not being virtualizable
with KVM, you end-up baking SDEI in *hardware*. Of cour
On Tue, Jan 28, 2020 at 11:34:58AM +0100, Eric Auger wrote:
> This test maps LPIs (populates the device table, the collection table,
> interrupt translation tables, configuration table), migrates and make
> sure the translation is correct on the destination.
>
> Signed-off-by: Eric Auger
> ---
>
On 2/7/20 1:45 AM, Gerd Hoffmann wrote:
From: Kővágó, Zoltán
This adds proper support for float samples in mixeng by adding a new
audio format for it.
Limitations: only native endianness is supported. None of the virtual
sound cards support float samples (it looks like most of them only
suppo
When initializing the LUKS header the size with default encryption
parameters will currently be 2068480 bytes. This is rounded up to
a multiple of the cluster size, 2081792, with 64k sectors. If the
end of the header is not the same as the end of the cluster we fill
the extra space with zeros. This
Gerd Hoffmann writes:
> When enabled, this forces showing the mouse cursor,
> i.e. do not hide the pointer on mouse grabs.
> Defaults to off.
>
> Signed-off-by: Gerd Hoffmann
> ---
> qapi/ui.json | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/qapi/ui.json b/qapi/ui.json
> index e04
On Thu, 6 Feb 2020 at 13:08, Richard Henderson
wrote:
>
> For the purpose of rebuild_hflags_a64, we do not need to compute
> all of the va parameters, only tbi. Moreover, we can compute them
> in a form that is more useful to storing in hflags.
>
> This eliminates the need for aa64_va_parameter_b
On 2/7/20 1:39 PM, Philippe Mathieu-Daudé wrote:
On 2/7/20 12:51 PM, Peter Maydell wrote:
On Thu, 6 Feb 2020 at 21:21, Philippe Mathieu-Daudé
wrote:
Hi Peter,
I prepared this series on behalf of Eduardo and
Cleber (one of them will ack this cover).
Regards,
Phil.
The following changes sin
On 2/7/20 6:28 AM, Christian Borntraeger wrote:
Jason,
can you run objdump -Sdr on jump2ipl.o on a broken variant?
To keep the volume lower, I've only pasted the output that I think you're interested in.
If you want to see the entire thing just let me know.
static void jump_to_IPL_2(void)
{
Philippe Mathieu-Daudé writes:
> List this file in the proper section, so maintainers get
> notified when it is modified.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Cc: Kevin Wolf
> Cc: Max Reitz
> Cc: qemu-bl...@nongnu.org
> ---
> MAINTAINERS | 2 ++
> 1 file changed, 2 insertions(+)
On Tue, Jan 28, 2020 at 11:34:59AM +0100, Eric Auger wrote:
> Add two new migration tests. One testing the migration of
> a topology where collection were unmapped. The second test
> checks the migration of the pending table.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v2 -> v3:
> - tests belong
On 2/7/20 1:53 PM, Wainer dos Santos Moschetta wrote:
On 2/6/20 3:17 PM, Philippe Mathieu-Daudé wrote:
This test fails on various CI:
What CI(s) you mean?
Afaik the acceptance tests are executed only on Travis
AFAIK maintainers doesn't have to have all their tests public, but are
encoura
On Fri, Feb 07, 2020 at 02:04:52PM +0100, Philippe Mathieu-Daudé wrote:
> There's no good reason for it to be type int, change it to bool.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
> ---
> v3: new patch
> ---
> include/hw/boar
On Fri, Feb 07, 2020 at 02:04:53PM +0100, Philippe Mathieu-Daudé wrote:
> It would be confusing to have multiple default machines.
> Abort if this ever occurs.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> v2: Use assert() instead of human friendly message (Marc-André)
>
> Cc: Marc-André Lur
Am 07.02.2020 um 15:01 hat Markus Armbruster geschrieben:
> Philippe Mathieu-Daudé writes:
>
> > List this file in the proper section, so maintainers get
> > notified when it is modified.
> >
> > Signed-off-by: Philippe Mathieu-Daudé
> > ---
> > Cc: Kevin Wolf
> > Cc: Max Reitz
> > Cc: qemu-bl
On 2/7/20 5:09 AM, Joel Stanley wrote:
On Fri, 7 Feb 2020 at 12:58, Guenter Roeck wrote:
On 2/7/20 12:16 AM, Cédric Le Goater wrote:
On 2/6/20 7:34 PM, Guenter Roeck wrote:
Initialize EHCI controllers on AST2400 and AST2500 using the existing
TYPE_PLATFORM_EHCI. After this change, booting as
Le 07/02/2020 à 15:11, Michael S. Tsirkin a écrit :
> On Fri, Feb 07, 2020 at 02:04:52PM +0100, Philippe Mathieu-Daudé wrote:
>> There's no good reason for it to be type int, change it to bool.
>>
>> Suggested-by: Richard Henderson
>> Signed-off-by: Philippe Mathieu-Daudé
>
> Reviewed-by: Michae
On 2/7/20 4:06 AM, Markus Armbruster wrote:
Peter Maydell writes:
A handful of QAPI doc comments include lines like
"ppcemb: dropped in 3.1". The doc comment parser will just
put these into whatever the preceding section was; sometimes
that's "Notes", and sometimes it's some random other secti
On Fri, Feb 07, 2020 at 03:22:19PM +0100, Laurent Vivier wrote:
> Le 07/02/2020 à 15:11, Michael S. Tsirkin a écrit :
> > On Fri, Feb 07, 2020 at 02:04:52PM +0100, Philippe Mathieu-Daudé wrote:
> >> There's no good reason for it to be type int, change it to bool.
> >>
> >> Suggested-by: Richard Hen
On Fri, Feb 07, 2020 at 12:12:09PM +0100, Greg Kurz wrote:
> On Fri, 7 Feb 2020 11:35:47 +0100
> Philippe Mathieu-Daudé wrote:
>
> > On 2/7/20 7:48 AM, Michael S. Tsirkin wrote:
> > > We are going to add more init for the latest machine, so move the setup
> > > to a function so we don't have to c
On 29/01/2020 21:23, Philippe Mathieu-Daudé wrote:
Since QEMU binaries can be built with various configurations,
the list of QOM objects linked can vary.
Add a helper to query the list of all QOM types implementing a
particular interface.
Signed-off-by: Philippe Mathieu-Daudé
---
python/qemu/
On 2/7/20 2:00 PM, Peter Maydell wrote:
>>
>> +/* Present TBI as a composite with TBID. */
>> +tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
>> +if (!data) {
>> +tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
>> +}
>> +tbi = (tbi >> select) & 1;
>
> ...but aa64_va_paramete
On 2/7/20 3:21 PM, Guenter Roeck wrote:
> On 2/7/20 5:09 AM, Joel Stanley wrote:
>> On Fri, 7 Feb 2020 at 12:58, Guenter Roeck wrote:
>>>
>>> On 2/7/20 12:16 AM, Cédric Le Goater wrote:
On 2/6/20 7:34 PM, Guenter Roeck wrote:
> Initialize EHCI controllers on AST2400 and AST2500 using the
On 2/7/20 3:22 PM, Laurent Vivier wrote:
Le 07/02/2020 à 15:11, Michael S. Tsirkin a écrit :
On Fri, Feb 07, 2020 at 02:04:52PM +0100, Philippe Mathieu-Daudé wrote:
There's no good reason for it to be type int, change it to bool.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu
On 2/7/20 5:50 AM, Peter Maydell wrote:
So far we've been converting docs to Sphinx and assigning them
to manuals according to the division originally set out by
Paolo on the wiki: https://wiki.qemu.org/Features/Documentation
* QEMU User-mode Emulation User's Guide (docs/user)
* QEMU System
On 2/7/20 3:28 PM, Liam Merwick wrote:
On 29/01/2020 21:23, Philippe Mathieu-Daudé wrote:
Since QEMU binaries can be built with various configurations,
the list of QOM objects linked can vary.
Add a helper to query the list of all QOM types implementing a
particular interface.
Signed-off-by: Ph
From: Richard Henderson
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the Secure EL1&0 regime.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-13-richard.hender...@linaro.org
Signed-o
From: Richard Henderson
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.h
From: Richard Henderson
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 7 ---
target/arm/helper.c | 6 +-
2 files changed, 5 inserti
6.0'
into staging (2020-02-07 11:52:15 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20200207
for you to fetch changes up to af6c91b490e9b1bce7a168f8a9c848f3e60f616e:
stellaris: delay timer_new to avoid memleaks (2
From: Richard Henderson
This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message
From: Liang Yan
Commit e19afd566781 mentioned that target-arm only supports queryable
cpu models 'max', 'host', and the current type when KVM is in use.
The logic works well until using machine type none.
For machine type none, cpu_type will be null if cpu option is not
set by command line, strl
From: Richard Henderson
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.
The ultimate goal is
-- Non-secure regimes:
ARMMMUIdx_E10_0,
ARMMMUIdx_E20_0,
ARMMMUIdx_E10_1,
ARMMMUIdx_E2,
ARMMMUIdx_E20_2,
-- Secure reg
From: Richard Henderson
Not all of the breakpoint types are supported, but those that
only examine contextidr are extended to support the new register.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-4-richard.hender...@linaro.o
From: Richard Henderson
Prepare for, but do not yet implement, the EL2&0 regime.
This involves adding the new MMUIdx enumerators and adjusting
some of the MMUIdx related predicates to match.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 202002061
From: Richard Henderson
No functional change, but unify code sequences.
Tested-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
targe
From: Richard Henderson
We are about to expand the number of mmuidx to 10, and so need 4 bits.
For the benefit of reading the number out of -d exec, align it to the
penultimate nibble.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.
From: Richard Henderson
At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-5-richard.hender...@linaro.org
Signed-off-by: Peter Mayd
From: Richard Henderson
No functional change, but unify code sequences.
Tested-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
targe
From: Richard Henderson
Create a predicate to indicate whether the regime has
both positive and negative addresses.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-21-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
--
From: Richard Henderson
Since we only support a single ASID, flush the tlb when it changes.
Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between
the two TTBR* registers for the location of the ASID.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Hende
From: Richard Henderson
The virtual offset may be 0 depending on EL, E2H and TGE.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 40 +++
From: Richard Henderson
This is part of a reorganization to the set of mmu_idx.
The EL1&0 regime is the only one that uses 2-stage translation.
Spelling out Stage avoids confusion with Secure.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 2020020
From: Richard Henderson
Apart from the wholesale redirection that HCR_EL2.E2H performs
for EL2, there's a separate redirection specific to the timers
that happens for EL0 when running in the EL2&0 regime.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Messa
From: Richard Henderson
Rather than call to a separate function and re-compute any
parameters for the flush, simply use the correct flush
function directly.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-9-richard.hender...@lin
From: Richard Henderson
Update to include checks against HCR_EL2.TID2.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-25-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 26 +
From: Richard Henderson
The TGE bit routes all asynchronous exceptions to EL2.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-33-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 6 ++
From: Richard Henderson
For ARMv8.1, op1 == 5 is reserved for EL2 aliases of
EL1 and EL0 registers.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-28-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/
From: Richard Henderson
The EL1&0 regime is the only one that uses 2-stage translation.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200206105448.4726-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h
From: Richard Henderson
Define via macro expansion, so that renumbering of the base ARMMMUIdx
symbols is automatically reflected in the bit definitions.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 2020020610
101 - 200 of 378 matches
Mail list logo
