[kvm-unit-tests PATCH 05/10] arm: pmu: Basic event counter Tests

Adds the following tests: - event-counter-config: test event counter configuration - basic-event-count: - programs counters #0 and #1 to count 2 required events (resp. CPU_CYCLES and INST_RETIRED). Counter #0 is preset to a value close enough to the 32b overflow limit so that we check the o

[PATCH v10 Kernel 1/5] vfio: KABI for migration interface for device state

- Defined MIGRATION region type and sub-type. - Defined vfio_device_migration_info structure which will be placed at 0th offset of migration region to get/set VFIO device related information. Defined members of structure and usage on read/write access. - Defined device states and added state

[PATCH v10 Kernel 4/5] vfio iommu: Implementation of ioctl to for dirty pages tracking.

VFIO_IOMMU_DIRTY_PAGES ioctl performs three operations: - Start unpinned pages dirty pages tracking while migration is active and device is running, i.e. during pre-copy phase. - Stop unpinned pages dirty pages tracking. This is required to stop unpinned dirty pages tracking if migration failed

[PATCH v10 Kernel 2/5] vfio iommu: Adds flag to indicate dirty pages tracking capability support

Flag VFIO_IOMMU_INFO_DIRTY_PGS in VFIO_IOMMU_GET_INFO indicates that driver support dirty pages tracking. Signed-off-by: Kirti Wankhede Reviewed-by: Neo Jia --- drivers/vfio/vfio_iommu_type1.c | 3 ++- include/uapi/linux/vfio.h | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-)

[PATCH v10 Kernel 3/5] vfio iommu: Add ioctl defination for dirty pages tracking.

IOMMU container maintains a list of all pages pinned by vfio_pin_pages API. All pages pinned by vendor driver through this API should be considered as dirty during migration. When container consists of IOMMU capable device and all pages are pinned and mapped, then all pages are marked dirty. Added

Re: [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller

Le lun. 16 déc. 2019 20:46, Niek Linnenbank a écrit : > > > On Mon, Dec 16, 2019 at 1:14 AM Philippe Mathieu-Daudé > wrote: > >> On 12/16/19 12:07 AM, Niek Linnenbank wrote: >> > >> > >> > On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daudé >> > mailto:phi...@redhat.com>> wrote: >> > >> >

[PATCH v2 01/28] target/xtensa: Use probe_access for itlb_hit_test

We don't actually need the result of the read, only to probe that the memory mapping exists. This is exactly what probe_access does. This is also the only user of any cpu_ld*_code_ra function. Removing this allows the interface to be removed shortly. Acked-by: Max Filippov Signed-off-by: Richar

[PATCH v2 02/28] cputlb: Use trace_mem_get_info instead of trace_mem_build_info

In the cpu_ldst templates, we already require a MemOp, and it is cleaner and clearer to pass that instead of 3 separate arguments describing the memory operation. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst_template.h | 22 +++--- include/exec/cpu_ldst_use

[PATCH v2 03/28] trace: Remove trace_mem_build_info_no_se_[bl]e

It is easy for the atomic helpers to use trace_mem_build_info directly, without resorting to symbol pasting. For this usage, we cannot use trace_mem_get_info, because the MemOp does not support 16-byte accesses. Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 67 +

[PATCH v2 07/28] cputlb: Provide cpu_(ld, st}*_mmuidx_ra for user-only

This finishes the new interface began with the previous patch. Document the interface and deprecate MMU_MODE_SUFFIX. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 80 +- docs/devel/loads-stores.rst | 211 ++-- 2 files changed, 230

[PATCH v2 00/28] cputlb: Remove support for MMU_MODE*_SUFFIX

This is part of a project to raise the limit on NB_MMU_MODES. One of those is in cpu_ldst.h, in support of MMU_MODE*_SUFFIX. While this could be extended, it's not the best interface for such things. Better is a single interface that allows a variable mmu_idx. The best exemplars of that is the u

[PATCH v2 06/28] cputlb: Rename helper_ret_ld*_cmmu to cpu_ld*_code

There are no uses of the *_cmmu names other than the bare wrapping within the *_code inlines. Therefore rename the functions so we can drop the inlines. Use abi_ptr instead of target_ulong in preparation for user-only; the two types are identical for softmmu. Reviewed-by: Aleksandar Markovic Si

[PATCH v2 04/28] cputlb: Move body of cpu_ldst_template.h out of line

With the tracing hooks, the inline functions are no longer so simple. Once out-of-line, the current tlb_entry lookup is redundant with the one in the main load/store_helper. This also begins the introduction of a new target facing interface, with suffix *_mmuidx_ra. This is not yet official beca

[PATCH v2 14/28] cputlb: Expand cpu_ldst_useronly_template.h in user-exec.c

With the tracing hooks, the inline functions are no longer so simple. Reduce the amount of preprocessor obfuscation by expanding the text of each of the functions generated. The result is only slightly larger than the original. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h

[PATCH v2 10/28] target/arm: Include tcg.h in sve_helper.c

Code movement in an upcoming patch will show that this file was implicitly depending on tcg.h being included indirectly. Cc: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/sve_helper.c b/target/arm/sve_he

[PATCH v2 05/28] translator: Use cpu_ld*_code instead of open-coding

The DO_LOAD macros replicate the distinction already performed by the cpu_ldst.h functions. Use them. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 11 - include/exec/translator.h | 48 +++ 2 files changed, 13 insertions(+), 46 dele

[PATCH v2 08/28] target/i386: Use cpu_*_mmuidx_ra instead of templates

Do not use exec/cpu_ldst_{,useronly_}template.h directly, but instead use the functional interface. Cc: Eduardo Habkost Acked-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target/i386/seg_helper.c | 56 1 file changed, 28 insertions(+), 28 dele

[PATCH v2 22/28] target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX

The functions generated by these macros are unused. Acked-by: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 4 1 file changed, 4 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b363ffcf10..f5a7ea48bb 100644 --- a/target/xtensa/cpu.h +++

[PATCH v2 09/28] target/s390x: Include tcg.h in mem_helper.c

Code movement in an upcoming patch will show that this file was implicitly depending on tcg.h being included indirectly. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/mem_helper.c b/

[PATCH v2 13/28] linux-user: Include trace-root.h in syscall-trace.h

Code movement in an upcoming patch will show that this file was implicitly depending on trace-root.h being included beforehand. Signed-off-by: Richard Henderson --- include/user/syscall-trace.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/user/syscall-trace.h b/include/user/sysc

[PATCH v2 11/28] accel/tcg: Include tcg.h in tcg-runtime.c

Code movement in an upcoming patch will show that this file was implicitly depending on tcg.h being included indirectly. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/

[PATCH v2 24/28] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX

The separate suffixed functions were used to construct some do_##insn function switched on mmu_idx. The interface is exactly identical to the *_mmuidx_ra functions. Replace them directly and remove the constructions. Cc: Aurelien Jarno Cc: Aleksandar Rikalo Reviewed-by: Aleksandar Markovic Si

[PATCH v2 25/28] target/s390x: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX

The generated functions aside from *_real are unused. The *_real functions have a couple of users in mem_helper.c; use *_mmuidx_ra instead, with MMU_REAL_IDX. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Use *_mmuidx_ra directly, without intermediate macros. --- targe

[PATCH v2 12/28] linux-user: Include tcg.h in syscall.c

Code movement in an upcoming patch will show that this file was implicitly depending on tcg.h being included indirectly. Signed-off-by: Richard Henderson --- linux-user/syscall.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 171c0caef3..348

[PATCH v2 15/28] target/nios2: Remove MMU_MODE{0,1}_SUFFIX

The functions generated by these macros are unused. Cc: Chris Wulff Cc: Marek Vasut Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 361b06ffeb..78f633f970 100644 --- a/target/nios2/cpu.h

[PATCH v2 18/28] target/i386: Remove MMU_MODE{0,1,2}_SUFFIX

The functions generated by these macros are unused. Cc: Eduardo Habkost Acked-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target/i386/cpu.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cde2a16b94..6a8228df4f 100644 --- a/target/i3

[PATCH v2 28/28] cputlb: Expand cpu_ldst_template.h in cputlb.c

Reduce the amount of preprocessor obfuscation by expanding the text of each of the functions generated. The result is only slightly smaller than the original. Reviewed-by: Aleksandar Markovic Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 67 +++--- includ

[PATCH v2 16/28] target/alpha: Remove MMU_MODE{0,1}_SUFFIX

The functions generated by these macros are unused. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index a530249a5b..3f782c0efe 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -193,8

[PATCH v2 21/28] target/unicore32: Remove MMU_MODE{0,1}_SUFFIX

The functions generated by these macros are unused. Cc: Guan Xuetao Signed-off-by: Richard Henderson --- target/unicore32/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 50ed9dd99c..7a32e086ed 100644 --- a/target/unicore32/cpu.h +

[PATCH v2 17/28] target/cris: Remove MMU_MODE{0,1}_SUFFIX

The functions generated by these macros are unused. Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/cris/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index aba0a66474..bc43bc23a1 100644 --- a/target/cris/cpu.h +++ b/target/cr

[PATCH v2 23/28] target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0, 1}_SUFFIX

The generated *_user functions are unused. The *_kernel functions have a couple of users in op_helper.c; use *_mmuidx_ra instead, with MMU_KERNEL_IDX. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- v2: Use *_mmuidx_ra directly, without intermediate macros. --- target/m68k/cpu

[PATCH v2 19/28] target/microblaze: Remove MMU_MODE{0,1,2}_SUFFIX

The functions generated by these macros are unused. Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 95773089aa..32522f606b 100644 --- a/target/microbl

[PATCH v2 20/28] target/sh4: Remove MMU_MODE{0,1}_SUFFIX

The functions generated by these macros are unused. Cc: Aurelien Jarno Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index ecaa7a18a9..452a596e67 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h

[PATCH v2 27/28] cputlb: Remove support for MMU_MODE*_SUFFIX

All users have now been converted to cpu_*_mmuidx_ra. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 230 1 file changed, 230 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 0f3c49a005..cf4652bf48 100644

[PATCH v2 26/28] target/ppc: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX

There are only two uses. Within dcbz_common, the local variable mmu_idx already contains the epid computation, and we can avoid repeating it for the store. Within helper_icbiep, the usage is trivially expanded using PPC_TLB_EPID_LOAD. Acked-by: David Gibson Signed-off-by: Richard Henderson ---

Re: [PATCH v10 Kernel 1/5] vfio: KABI for migration interface for device state

On Tue, 17 Dec 2019 01:51:36 +0530 Kirti Wankhede wrote: > - Defined MIGRATION region type and sub-type. > > - Defined vfio_device_migration_info structure which will be placed at 0th > offset of migration region to get/set VFIO device related information. > Defined members of structure and

Re: [PATCH v10 Kernel 2/5] vfio iommu: Adds flag to indicate dirty pages tracking capability support

On Tue, 17 Dec 2019 01:51:37 +0530 Kirti Wankhede wrote: > Flag VFIO_IOMMU_INFO_DIRTY_PGS in VFIO_IOMMU_GET_INFO indicates that driver > support dirty pages tracking. > > Signed-off-by: Kirti Wankhede > Reviewed-by: Neo Jia > --- > drivers/vfio/vfio_iommu_type1.c | 3 ++- > include/uapi/linux

Re: [PATCH v4 2/5] python/qemu: accel: Add list_accel() method

On Mon, Dec 16, 2019 at 04:14:35PM -0300, Wainer dos Santos Moschetta wrote: > Since commit cbe6d6365a48 the command `qemu -accel help` returns > the list of accelerators enabled in the QEMU binary. This adds > the list_accel() method which return that same list. > > Signed-off-by: Wainer dos Sant

[PATCH v2 01/10] hw: arm: add Allwinner H3 System-on-Chip

The Allwinner H3 is a System on Chip containing four ARM Cortex A7 processor cores. Features and specifications include DDR2/DDR3 memory, SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and various I/O modules. This commit adds support for the Allwinner H3 System on Chip. Signed-off-

[PATCH v2 05/10] arm: allwinner-h3: add System Control module

The Allwinner H3 System on Chip has an System Control module that provides system wide generic controls and device information. This commit adds support for the Allwinner H3 System Control module. Signed-off-by: Niek Linnenbank --- include/hw/arm/allwinner-h3.h | 2 + include/hw/misc/a

[PATCH v2 02/10] hw: arm: add Xunlong Orange Pi PC machine

The Xunlong Orange Pi PC is an Allwinner H3 System on Chip based embedded computer with mainline support in both U-Boot and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, 512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and various other I/O. This commit add support for the Xunlong

[PATCH v2 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine

Dear QEMU developers, Hereby I would like to contribute the following set of patches to QEMU which add support for the Allwinner H3 System on Chip and the Orange Pi PC machine. The following features and devices are supported: * SMP (Quad Core Cortex A7) * Generic Interrupt Controller configura

[PATCH v2 04/10] arm: allwinner-h3: add USB host controller

The Allwinner H3 System on Chip contains multiple USB 2.0 bus connections which provide software access using the Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI) interfaces. This commit adds support for both interfaces in the Allwinner H3 System on Chip. Signed-

[PATCH v2 08/10] arm: allwinner-h3: add Security Identifier device

The Security Identifier device in Allwinner H3 System on Chip gives applications a per-board unique identifier. This commit adds support for the Allwinner H3 Security Identifier using a 128-bit UUID value as input. Signed-off-by: Niek Linnenbank --- include/hw/arm/allwinner-h3.h | 2 + in

[PATCH v2 10/10] arm: allwinner-h3: add EMAC ethernet device

The Allwinner H3 System on Chip includes an Ethernet MAC (EMAC) which provides 10M/100M/1000M Ethernet connectivity. This commit adds support for the Allwinner H3 EMAC, including emulation for the following functionality: * DMA transfers * MII interface * Transmit CRC calculation Signed-off-by

[PATCH v2 07/10] arm: allwinner-h3: add CPU Configuration module

The Allwinner H3 System on Chip design contains four ARM Cortex A7 processors that can be configured and reset using the CPU Configuration module interface. This commit adds support for the CPU configuration interface which emulates the following features: * CPU reset * Shared 64-bit timer Sign

[PATCH v2 06/10] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on()

After setting CP15 bits in arm_set_cpu_on() the cached hflags must be rebuild to reflect the changed processor state. Without rebuilding, the cached hflags would be inconsistent until the next call to arm_rebuild_hflags(). When QEMU is compiled with debugging enabled (--enable-debug), this problem

[PATCH v2 03/10] arm: allwinner-h3: add Clock Control Unit

The Clock Control Unit is responsible for clock signal generation, configuration and distribution in the Allwinner H3 System on Chip. This commit adds support for the Clock Control Unit which emulates a simple read/write register interface. Signed-off-by: Niek Linnenbank --- include/hw/arm/allwi

[PATCH v2 09/10] arm: allwinner-h3: add SD/MMC host controller

The Allwinner H3 System on Chip contains an integrated storage controller for Secure Digital (SD) and Multi Media Card (MMC) interfaces. This commit adds support for the Allwinner H3 SD/MMC storage controller with the following emulated features: * DMA transfers * Direct FIFO I/O * Short/Long f

Re: [PATCH v2 06/10] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on()

Hello Peter, In the previous version of this patch series I included the fix for setting CP10,CP11 bits in arm_set_cpu_on(), which is now in master (0c7f8c43daf65560). While that worked, I did not realize that setting those bits require rebuilding the flags. Philippe reported this [1] initially, l

Re: [PATCH v4 0/5] python/qemu: New accel module and improvements

On Mon, Dec 16, 2019 at 04:14:33PM -0300, Wainer dos Santos Moschetta wrote: > On commit abf0bf998dcb John Snow moved some code out of __init__.py > to machine.py. kvm_available() remained in though. So on patch 01 > I continue his work by creating a home for that method (the new > 'accel' module).

Re: [PATCH 04/13] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat

On Mon, Dec 16, 2019 at 07:07:43PM +0100, Greg Kurz wrote: > On Fri, 13 Dec 2019 13:44:48 +0100 > Cédric Le Goater wrote: > > > On 13/12/2019 12:59, Greg Kurz wrote: > > > The pnv_dt_create() function generates different contents for the > > > "compatible" property of the root node in the DT, dep

Re: [PATCH v5 1/5] tpm_spapr: Support TPM for ppc64 using CRQ based interface

On Fri, Dec 13, 2019 at 08:03:36AM -0500, Stefan Berger wrote: > On 12/13/19 12:34 AM, David Gibson wrote: > > On Thu, Dec 12, 2019 at 03:24:26PM -0500, Stefan Berger wrote: > > > Implement support for TPM on ppc64 by implementing the vTPM CRQ interface > > > as a frontend. It can use the tpm_emula

[PULL SUBSYSTEM qemu-pseries] pseries: Update SLOF firmware image

The following changes since commit 5084c8b76365f4570520e2cb549089ad523dc953: ppc/pnv: Drop PnvChipClass::type (2019-12-17 10:59:11 +1100) are available in the Git repository at: g...@github.com:aik/qemu.git tags/qemu-slof-20191217 for you to fetch changes up to 37d7f4242316380fb58566f6b667a

Re: [PATCH] ppc: remove excessive logging

On Sun, Dec 15, 2019 at 11:59:22AM +0100, BALATON Zoltan wrote: > On Sun, 15 Dec 2019, Philippe Mathieu-Daudé wrote: > > Hi Joakim, > > > > I'm cc'ing the PPC maintainers for you, so they won't miss your patch > > (see > > https://wiki.qemu.org/Contribute/SubmitAPatch#CC_the_relevant_maintainer >

Re: [PATCH v5 3/5] tpm_spapr: Support suspend and resume

On Fri, Dec 13, 2019 at 07:46:44AM -0500, Stefan Berger wrote: > On 12/13/19 12:39 AM, David Gibson wrote: > > On Thu, Dec 12, 2019 at 03:24:28PM -0500, Stefan Berger wrote: > > > Extend the tpm_spapr frontend with VM suspend and resume support. > > > > > > Signed-off-by: Stefan Berger > > > > >

Re: [PATCH v2 0/4] Add extra information to versioned CPU models

Ping for comments. On 12/9/2019 3:12 PM, Tao Xu wrote: This series of patches will remove MPX from Denverton, remove Remove monitor from some CPU models. Add additional information for -cpu help to indicate the changes in this version of CPU model. The output is as follows: ./x86_64-softmmu/qem

[RFC PATCH 0/3] vhost-user: Lift Max Ram Slots Limitation

In QEMU today, a VM with a vhost-user device can hot add memory a maximum of 8 times. See these threads, among others: [1] https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg01046.html https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg01236.html [2] https://lists.gnu.org/archive/

[RFC PATCH 1/3] Fixed Error Handling in vhost_user_set_mem_table_postcopy

The current vhost_user_set_mem_table_postcopy() implementation populates each region of the VHOST_USER_SET_MEM_TABLE message without first checking if there are more than VHOST_MEMORY_MAX_NREGIONS already populated. This can cause memory corruption and potentially a crash if too many regions are ad

[RFC PATCH 3/3] Introduce Configurable Number of Memory Slots Exposed by vhost-user:

The current vhost-user implementation in Qemu imposes a limit on the maximum number of memory slots exposed to a VM using a vhost-user device. This change provides a new protocol feature VHOST_USER_F_CONFIGURE_SLOTS which, when enabled, lifts this limit and allows a VM with a vhost-user device to e

[RFC PATCH 2/3] vhost-user: Refactor vhost_user_set_mem_table Functions

vhost_user_set_mem_table() and vhost_user_set_mem_table_postcopy() have gotten convoluted, and have some identical code. This change moves the logic populating the VhostUserMemory struct and fds array from vhost_user_set_mem_table() and vhost_user_set_mem_table_postcopy() to a new function, vhost_

[Bug 1805256] Re: qemu-img hangs on rcu_call_ready_event logic in Aarch64 when converting images

include/block/aio.h | 3 +++ qemu-img.c | 4 util/async.c| 5 + 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/block/aio.h b/include/block/aio.h index e9bc04c..9153d87 100644 --- a/include/block/aio.h +++ b/include/block/aio.h @@ -89,6 +89,9 @@ stru

Re: [PULL 3/4] i386: Add new CPU model Cooperlake

On 12/17/2019 3:38 AM, Eduardo Habkost wrote: From: Cathy Zhang Cooper Lake is intel's successor to Cascade Lake, the new CPU model inherits features from Cascadelake-Server, while add one platform associated new feature: AVX512_BF16. Meanwhile, add STIBP for speculative execution. Signed-off-

Re: [PATCH v2 01/28] target/xtensa: Use probe_access for itlb_hit_test

On 12/16/19 11:11 PM, Richard Henderson wrote: We don't actually need the result of the read, only to probe that the memory mapping exists. This is exactly what probe_access does. This is also the only user of any cpu_ld*_code_ra function. Removing this allows the interface to be removed shortl

Re: [PATCH v2 02/28] cputlb: Use trace_mem_get_info instead of trace_mem_build_info

On 12/16/19 11:11 PM, Richard Henderson wrote: In the cpu_ldst templates, we already require a MemOp, and it is cleaner and clearer to pass that instead of 3 separate arguments describing the memory operation. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst_template.h | 22

Re: [PATCH 5/7] target/ppc: Add privileged message send facilities

On Thu, Nov 28, 2019 at 02:46:58PM +0100, Cédric Le Goater wrote: > From: Suraj Jitindar Singh > > Privileged message send facilities exist on POWER8 processors and > later and include a register and instructions which can be used to > generate, observe/modify the state of and clear privileged do

[PULL 02/88] ppc/pnv: Add a "/qemu" device tree node

From: Cédric Le Goater It helps skiboot identifying that is running on a QEMU platform. The compatible string will define the POWERPC processor version. Signed-off-by: Cédric Le Goater Message-Id: <20191106142129.4908-1-...@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 3 +++ 1 fil

[PULL 03/88] ppc/pnv: Drop "chip" link from POWER9 PSI object

From: Greg Kurz It has no apparent user. Signed-off-by: Greg Kurz Message-Id: <157383383118.166856.2588933416368211047.st...@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 416caab6f6..4e9ddc05ad 10

[PULL 04/88] xive: Link "cpu" property to XiveTCTX::cs pointer

From: Greg Kurz The TCTX object has both a pointer and a "cpu" property pointing to the vCPU object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383332669.165747.248405

[PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer

From: Greg Kurz The LPC object has both a pointer and a "psi" property pointing to the PSI object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383334342.165747.31593149

[PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer

From: Greg Kurz The END source object has both a pointer and a "xive" property pointing to the router object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. The property isn't optional : not being able to set the l

[PULL 01/88] ppc/pnv: Add a PNOR model

From: Cédric Le Goater On a POWERPC PowerNV system, the host firmware is stored in a PNOR flash chip which contents is mapped on the LPC bus. This model adds a simple dummy device to map the contents of a block device in the host address space. Signed-off-by: Cédric Le Goater Message-Id: <20191

[PULL 00/88] ppc-for-5.0 queue 20191217

The following changes since commit cb88904a54903ef6ba21a68a61d9cd51e2166304: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' into staging (2019-12-16 14:07:56 +) are available in the Git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-5.0-20191

[PULL 05/88] xive: Link "xive" property to XiveSource::xive pointer

From: Greg Kurz The source object has both a pointer and a "xive" property pointing to the notifier object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. The property isn't optional : not being able to set the lin

[PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer

From: Greg Kurz The XIVE object has both a pointer and a "chip" property pointing to the chip object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383336564.165747.10250

[PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer

From: Greg Kurz The homer object has both a pointer and a "chip" property pointing to the chip object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383335451.165747.3230

[PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer

From: Greg Kurz The OCC object has both a pointer and a "psi" property pointing to the PSI object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383334894.165747.76170907

[PULL 12/88] xics: Link ICS_PROP_XICS property to ICSState::xics pointer

From: Greg Kurz The ICS object has both a pointer and an ICS_PROP_XICS property pointing to the XICS fabric. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. The property isn't optional : not being able to set the li

[PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer

From: Greg Kurz The ICP object has both a pointer and an ICP_PROP_XICS property pointing to the XICS fabric. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the lin

[PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer

From: Greg Kurz The ICP object has both a pointer and an ICP_PROP_CPU property pointing to the cpu. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bu

[PULL 28/88] ppc/xive: Implement the XivePresenter interface

From: Cédric Le Goater Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt' handler of the XivePresenter QOM interface. This is simply moving code and taking into account the new API. To be noted that the xive_router_get_tctx() helper is not used anymore when doing CAM match

[PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer

From: Greg Kurz The core object has both a pointer and a "chip" property pointing to the chip object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383336007.165747.15241

[PULL 16/88] ppc/pnv: Add a LPC "ranges" property

From: Cédric Le Goater And fix a typo in the MEM address space definition. Signed-off-by: Cédric Le Goater Message-Id: <20191118091908.15044-1-...@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv_lpc.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/p

[PULL 27/88] ppc/xive: Introduce a XivePresenter interface

From: Cédric Le Goater When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification Virtual Target (NVT) to notify, it broadcasts a message on the PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT dispatched on one of its HW threads, and then forwards the notification if an

[PULL 34/88] ppc/xive: Introduce a XiveFabric interface

From: Cédric Le Goater The XiveFabric QOM interface acts as the PowerBUS interface between the interrupt controller and the system and should be implemented by the QEMU machine. On HW, the XIVE sub-engine is responsible for the communication with the other chip is the Common Queue (CQ) bridge uni

[PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized

From: Greg Kurz Failing to set any of the ICS property should really never happen: - object_property_add_child() always succeed unless the child object already has a parent, which isn't the case here obviously since the ICS has just been created with object_new() - the ICS has an "nr-irqs" pr

[PULL 18/88] ppc/xive: Introduce helpers for the NVT id

From: Cédric Le Goater Each vCPU in the system is identified with an NVT identifier which is pushed in the OS CAM line (QW1W2) of the HW thread interrupt context register when the vCPU is dispatched on a HW thread. This identifier is used by the presenter subengine to find a matching target to no

[PULL 26/88] ppc/pnv: Create BMC devices at machine init

From: Cédric Le Goater The BMC of the OpenPOWER systems monitors the machine state using sensors, controls the power and controls the access to the PNOR flash device containing the firmware image required to boot the host. QEMU models the power cycle process, access to the sensors and access to

[PULL 35/88] ppc/pnv: Implement the XiveFabric interface

From: Cédric Le Goater The CAM line matching on the PowerNV machine now scans all chips of the system and all CPUs of a chip to find a dispatched NVT in the thread contexts. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-10-...@kaod.org> Signed-off-by: D

[PULL 17/88] ppc/xive: Record the IPB in the associated NVT

From: Cédric Le Goater When an interrupt can not be presented to a vCPU, because it is not running on any of the HW treads, the XIVE presenter updates the Interrupt Pending Buffer register of the associated XIVE NVT structure. This is only done if backlog is activated in the END but this is gener

[PULL 20/88] xive/kvm: Trigger interrupts from userspace

From: Greg Kurz When using the XIVE KVM device, the trigger page is directly accessible in QEMU. Unlike with XICS, no need to ask KVM to fire the interrupt. A simple store on the trigger page does the job. Just call xive_esb_trigger(). This may improve performance of emulated devices that go th

[PULL 24/88] ipmi: Add support to customize OEM functions

From: Cédric Le Goater The routine ipmi_register_oem_netfn() lets external modules register command handlers for OEM functions. Required for the PowerNV machine. Cc: Corey Minyard Reviewed-by: Corey Minyard Signed-off-by: Cédric Le Goater Message-Id: <20191028070027.22752-2-...@kaod.org> Acke

[PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine

From: Cédric Le Goater pnv_xive_vst_size() tries to compute the size of a VSD table from the information given by FW. The number of entries of the table are deduced from the result and the MMIO regions of the ESBs and the END ESBs are then resized accordingly with the computed value. This reduces

[PULL 42/88] spapr/xive: Configure number of servers in KVM

From: Greg Kurz The XIVE KVM devices now has an attribute to configure the number of interrupt servers. This allows to greatly optimize the usage of the VP space in the XIVE HW, and thus to start a lot more VMs. Only set this attribute if available in order to support older POWER9 KVM. The XIVE

[PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT

From: Cédric Le Goater CPU_FOREACH() loops on all the CPUs of the machine which is incorrect. Each XIVE Presenter should scan only the HW threads of the chip it belongs to. Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-5

[PULL 33/88] ppc/pnv: Fix TIMA indirect access

From: Cédric Le Goater When the TIMA of a CPU needs to be accessed from the indirect page, the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0 register. This thread id is relative to the chip and not to the system. Introduce a helper routine to look for a CPU of a given PIR an

[PULL 41/88] spapr/xics: Configure number of servers in KVM

From: Greg Kurz The XICS-on-XIVE KVM devices now has an attribute to configure the number of interrupt servers. This allows to greatly optimize the usage of the VP space in the XIVE HW, and thus to start a lot more VMs. Only set this attribute if available in order to support older POWER9 KVM an

[PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX

From: Cédric Le Goater A context should be 'valid' when pulled from the thread interrupt context registers. Signed-off-by: Cédric Le Goater Message-Id: <20191115162436.30548-8-...@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 5 + 1 file changed, 5 insertions(+) diff --git a

[PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper

From: Cédric Le Goater When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field overrides the hardwired chip ID in the Powerbus operations and for CAM compares. This is typically used in the one block-per-chip configuration to associate a unique block id number to each IC of the sys

[PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces

From: Cédric Le Goater Now that the machines have handlers implementing the XiveFabric and XivePresenter interfaces, remove xive_presenter_match() and make use of the 'match_nvt' handler of the machine. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-12-.

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