On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the allwinner-a10-pit code away from bottom-half based ptimers to
> the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() funct
On Thu, Sep 26, 2019 at 07:34:11PM +0200, Philippe Mathieu-Daudé wrote:
> Various address spaces from the BCM2835 are reported as
> 'anonymous' in memory tree:
>
> (qemu) info mtree
>
> address-space: anonymous
> -008f (prio 0, i/o): bcm2835-mbox
> 00
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the imx_epit.c code away from bottom-half based ptimers to
> the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() function to
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the arm_mptimer.c code away from bottom-half based ptimers to
> the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() function
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the exynos41210_rtc 1Hz ptimer over to the transaction-based
> API. (We will switch the other ptimer used by this device in a
> separate commit.)
>
> Signed-off-by: Peter Maydell
> ---
> hw/timer/exynos4210_rtc.c | 10 --
> 1 file changed
On Wed, Oct 9, 2019 at 7:41 AM Alistair Francis
wrote:
>
> Add a property that when set to true QEMU will jump from the ROM code to
> the start of flash memory instead of DRAM which is the default
> behaviour.
>
> Signed-off-by: Alistair Francis
> ---
> v3:
> - Use the start_addr variable instea
Philippe Mathieu-Daudé 于2019年10月8日周二 下午10:47写道：
> Since v1:
> - Removed the pci-host devices
>
Hello I want to know why remove this?
Thanks,
Li Qiang
> - Removed the vmcoreinfo conversion (elmarco) but add a comment.
> - Added Igor's R-b tag.
>
> Following the thread discussion between Pete
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the mss-timer code away from bottom-half based ptimers to
> the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() function to c
On 10/8/19 9:56 PM, Richard Henderson wrote:
> On 10/8/19 1:17 PM, Peter Maydell wrote:
>> @@ -945,7 +977,7 @@ static void
>> exynos4210_mct_update_freq(Exynos4210MCTState *s)
>> DPRINTF("freq=%dHz\n", s->freq);
>>
>> /* global timer */
>> -ptimer_set_freq(s->g_timer.pt
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the exynos41210_rtc main ptimer over to the transaction-based
> API, completing the transition for this device.
>
> Signed-off-by: Peter Maydell
> ---
> hw/timer/exynos4210_rtc.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the digic-timer.c code away from bottom-half based ptimers to
> the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() function
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the cmsdk-apb-watchdog code away from bottom-half based
> ptimers to the new transaction-based ptimer API. This just requires
> adding begin/commit calls around the various places that modify the
> ptimer state, and using the new ptimer_init() func
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the exynos4210_pwm code away from bottom-half based ptimers to
> the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() function
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the imx_epit.c code away from bottom-half based ptimers to
> the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() function to
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the ltick ptimer over to the ptimer transaction API.
>
> Signed-off-by: Peter Maydell
> ---
> hw/timer/exynos4210_mct.c | 31 +--
> 1 file changed, 25 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
On 10/8/19 1:17 PM, Peter Maydell wrote:
> @@ -945,7 +977,7 @@ static void exynos4210_mct_update_freq(Exynos4210MCTState
> *s)
> DPRINTF("freq=%dHz\n", s->freq);
>
> /* global timer */
> -ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
> +tx_ptimer_set_freq(s->
On 10/8/19 1:17 PM, Peter Maydell wrote:
> We want to switch the exynos MCT code away from bottom-half based ptimers to
> the new transaction-based ptimer API. The MCT is complicated
> and uses multiple different ptimers, so it's clearer to switch
> it a piece at a time. Here we change over only th
On Wed, Oct 09, 2019 at 12:12:25PM +0800, Peter Xu wrote:
>On Wed, Oct 09, 2019 at 09:02:04AM +0800, Wei Yang wrote:
>> On Tue, Oct 08, 2019 at 05:40:46PM +0100, Dr. David Alan Gilbert wrote:
>> >* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> >> Currently, we set PostcopyState blindly to RUNN
spapr now has the mechanism of constructing both XICS and XIVE instances of
the SpaprInterruptController interface. However, only one of the interrupt
controllers will actually be active at any given time, depending on feature
negotiation with the guest. This is handled in the current code via
sp
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the cmsdk-apb-timer code away from bottom-half based ptimers
> to the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() functio
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the exynos MCT LFRC timers over to the ptimer transaction API.
>
> Signed-off-by: Peter Maydell
> ---
> hw/timer/exynos4210_mct.c | 27 +++
> 1 file changed, 23 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
From: Greg Kurz
Some device types of the XICS model are exposed to the QEMU command
line:
$ ppc64-softmmu/qemu-system-ppc64 -device help | grep ic[sp]
name "icp"
name "ics"
name "ics-spapr"
name "pnv-icp", desc "PowerNV ICP"
These are internal devices that shouldn't be instantiable by the
user.
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the cmsdk-apb-dualtimer code away from bottom-half based
> ptimers to the new transaction-based ptimer API. This just requires
> adding begin/commit calls around the various places that modify the
> ptimer state, and using the new ptimer_init() fun
Traditional PCI INTx for vfio devices can only perform well if using
an in-kernel irqchip. Therefore, vfio_intx_update() issues a warning
if an in kernel irqchip is not available.
We usually do have an in-kernel irqchip available for pseries machines
on POWER hosts. However, because the platform
From: Stefan Brankovic
In previous implementation, invocation of TCG shift function could request
shift of TCG variable by 64 bits when variable 'sh' is 0, which is not
supported in TCG (values can be shifted by 0 to 63 bits). This patch fixes
this by using two separate invocation of TCG shift fu
This method depends only on the active irq controller. Now that we've
formalized the notion of active controller we can dispatch directly
through that, rather than dispatching via SpaprIrq with the dual
version having to do a second conditional dispatch.
Signed-off-by: David Gibson
Reviewed-by:
Vladimir Sementsov-Ogievskiy writes:
> If we want to add some info to errp (by error_prepend() or
> error_append_hint()), we must use the ERRP_AUTO_PROPAGATE macro.
> Otherwise, this info will not be added when errp == &fatal_err
> (the program will exit prior to the error_append_hint() or
> erro
For the benefit of peripheral device allocation, the number of available
irqs really wants to be the same on a given machine type version,
regardless of what irq backends we are using. That's the case now, but
only because we make sure the different SpaprIrq instances have the same
value except fo
On 10/8/19 5:22 PM, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
Connect the recently added SYS_timer.
Now U-Boot does not hang anymore polling a free running counter
stuck at 0.
This timer is also used by the Linux kernel thermal subsystem.
Signed-off-by: Philippe Mathieu-Daudé
---
h
On Wed, Oct 09, 2019 at 09:02:04AM +0800, Wei Yang wrote:
> On Tue, Oct 08, 2019 at 05:40:46PM +0100, Dr. David Alan Gilbert wrote:
> >* Wei Yang (richardw.y...@linux.intel.com) wrote:
> >> Currently, we set PostcopyState blindly to RUNNING, even we found the
> >> previous state is not LISTENING. T
On Wed, Oct 09, 2019 at 01:36:34PM +0800, Peter Xu wrote:
>On Wed, Oct 09, 2019 at 01:07:56PM +0800, Wei Yang wrote:
>> On Wed, Oct 09, 2019 at 12:12:25PM +0800, Peter Xu wrote:
>> >On Wed, Oct 09, 2019 at 09:02:04AM +0800, Wei Yang wrote:
>> >> On Tue, Oct 08, 2019 at 05:40:46PM +0100, Dr. David A
This method essentially represents code which belongs to the interrupt
controller, but needs to be called on all possible intcs, rather than
just the currently active one. The "dual" version therefore calls
into the xics and xive versions confusingly.
Handle this more directly, by making it inste
The SpaprIrq structure is used to represent ths spapr machine's irq
backend. Except that it kind of conflates two concepts: one is the
backend proper - a specific interrupt controller that we might or
might not be using, the other is the irq configuration which covers
the layout of irq space and w
The only thing remaining in this structure are the flags to allow either
XICS or XIVE to be present. These actually make more sense as spapr
capabilities - that way they can take advantage of the existing
infrastructure to sanity check capability states across migration and so
forth.
Signed-off-b
From: Greg Kurz
Some device types of the XIVE model are exposed to the QEMU command
line:
$ ppc64-softmmu/qemu-system-ppc64 -device help | grep xive
name "xive-end-source", desc "XIVE END Source"
name "xive-source", desc "XIVE Interrupt Source"
name "xive-tctx", desc "XIVE Interrupt Thread Conte
On Mon, Oct 07, 2019 at 04:58:30PM +0200, Paolo Bonzini wrote:
> On 07/10/19 16:44, dann frazier wrote:
> > On Mon, Oct 07, 2019 at 01:06:20PM +0200, Paolo Bonzini wrote:
> >> On 02/10/19 11:23, Jan Glauber wrote:
> >>> I've looked into this on ThunderX2. The arm64 code generated for the
> >>> atom
On Wed, Oct 09, 2019 at 01:07:56PM +0800, Wei Yang wrote:
> On Wed, Oct 09, 2019 at 12:12:25PM +0800, Peter Xu wrote:
> >On Wed, Oct 09, 2019 at 09:02:04AM +0800, Wei Yang wrote:
> >> On Tue, Oct 08, 2019 at 05:40:46PM +0100, Dr. David Alan Gilbert wrote:
> >> >* Wei Yang (richardw.y...@linux.intel
Both XICS and XIVE have routines to connect and disconnect KVM with
similar but not identical signatures. This adjusts them to match
exactly, which will be useful for further cleanups later.
While we're there, we add an explicit return value to the connect path
to streamline error reporting in th
The remaining logic in the post_load hook really belongs to the interrupt
controller backends, and just needs to be called on the active controller
(after the active controller is set to the right thing based on the
incoming migration in the generic spapr_irq_post_load() logic).
Signed-off-by: Dav
> -Original Message-
> From: Lukas Straub
> Sent: Saturday, October 5, 2019 9:06 PM
> To: qemu-devel
> Cc: Zhang, Chen ; Jason Wang
> ; Wen Congyang ;
> Xie Changlong ; Kevin Wolf
> ; Max Reitz ; qemu-block
>
> Subject: [PATCH v6 2/4] tests/test-replication.c: Add test for for secondar
Cc: Marc-André for additional monitor and chardev expertise.
Wolfgang Bumiller writes:
> When a monitor's queue is filled up in handle_qmp_command()
> it gets suspended. It's the dispatcher bh's job currently to
> resume the monitor, which it does after processing an event
> from the queue. Howe
On 10/3/2019 7:19 PM, Igor Mammedov wrote:
On Fri, 20 Sep 2019 15:43:45 +0800
Tao Xu wrote:
From: Liu Jingqi
Add -numa hmat-cache option to provide Memory Side Cache Information.
These memory attributes help to build Memory Side Cache Information
Structure(s) in ACPI Heterogeneous Memory Att
This is a substantial rework to clean up the handling of IRQs in
spapr. It includes some cleanups to both the XICS and XIVE interrupt
controller backends, as well as more to the common spapr irq handling
infrastructure.
The last two patches of this series, dealing with VFIO devices, are
RFC only
The nr_msis value we use here has to line up with whether we're using
legacy or modern irq allocation. Therefore it's safer to derive it based
on legacy_irq_allocation rather than having SpaprIrq contain a canned
value.
Signed-off-by: David Gibson
Reviewed-by: Greg Kurz
---
hw/ppc/spapr.c
On Wed, Oct 09, 2019 at 10:37:38AM +0200, Greg Kurz wrote:
> On Wed, 9 Oct 2019 17:08:18 +1100
> David Gibson wrote:
>
> > Traditional PCI INTx for vfio devices can only perform well if using
> > an in-kernel irqchip. Therefore, vfio_intx_update() issues a warning
> > if an in kernel irqchip is
This method depends only on the active irq controller. Now that we've
formalized the notion of active controller we can dispatch directly through
that, rather than dispatching via SpaprIrq with the dual version having
to do a second conditional dispatch.
Signed-off-by: David Gibson
Reviewed-by:
It turns out that all the logic in the SpaprIrq::reset hooks (and some in
the SpaprIrq::post_load hooks) isn't really related to resetting the irq
backend (that's handled by the backends' own reset routines). Rather its
about getting the backend ready to be the active interrupt controller or
stopp
On 09/10/2019 08:08, David Gibson wrote:
> spapr now has the mechanism of constructing both XICS and XIVE instances of
> the SpaprInterruptController interface. However, only one of the interrupt
> controllers will actually be active at any given time, depending on feature
> negotiation with the g
This hook is a bit odd. The only caller is spapr_irq_init_kvm(), but
it explicitly takes an SpaprIrq *, so it's never really called through the
current SpaprIrq. Essentially this is just a way of passing through a
function pointer so that spapr_irq_init_kvm() can handle some
configuration and err
09.10.2019 11:04, Markus Armbruster wrote:
> Vladimir Sementsov-Ogievskiy writes:
>
>> Here is introduced ERRP_AUTO_PROPAGATE macro, to be used at start of
>> functions with errp OUT parameter.
>>
>> It has three goals:
>>
>> 1. Fix issue with error_fatal & error_prepend/error_append_hint: user
>
This method depends only on the active irq controller. Now that we've
formalized the notion of active controller we can dispatch directly
through that, rather than dispatching via SpaprIrq with the dual
version having to do a second conditional dispatch.
Signed-off-by: David Gibson
Reviewed-by:
On 10/9/2019 4:06 PM, Paolo Bonzini wrote:
On 29/09/19 03:57, Tao Xu wrote:
+} else if (function == 7 && index == 0 && reg == R_ECX) {
+if (enable_cpu_pm) {
+ret |= CPUID_7_0_ECX_WAITPKG;
This is incorrect. You should disable WAITPKG if !enable_cpu_pm, but
you should n
08.10.2019 12:08, Markus Armbruster wrote:
> Vladimir Sementsov-Ogievskiy writes:
>
>> Error **errp is almost always OUT-argument: it's assumed to be NULL, or
>> pointer to NULL-initialized pointer, or pointer to error_abort or
>> error_fatal, for callee to report error.
>
> Yes.
>
>> But very
On 10/2/2019 11:16 PM, Igor Mammedov wrote:
On Fri, 20 Sep 2019 15:43:44 +0800
Tao Xu wrote:
[...]
+struct HMAT_LB_Info {
+/* Indicates it's memory or the specified level memory side cache. */
+uint8_t hierarchy;
+
+/* Present the type of data, access/read/write latency or ban
pseries machine type can have one of two different interrupt controllers in
use depending on feature negotiation with the guest. Usually this is
invisible to devices, because they route to a common set of qemu_irqs which
in turn dispatch to the correct back end.
VFIO passthrough devices, however,
Introduce a function to gracefully wake a coroutine sleeping in
qemu_co_sleep_ns().
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Reviewed-by: Eric Blake
---
include/qemu/coroutine.h| 23 +++--
util/qemu-coroutine-sleep.c | 51 +++--
These methods, like cpu_intc_create, really belong to the interrupt
controller, but need to be called on all possible intcs.
Like cpu_intc_create, therefore, make them methods on the intc and
always call it for all existing intcs.
Signed-off-by: David Gibson
Reviewed-by: Greg Kurz
Reviewed-by:
Add test, which starts backup to nbd target and restarts nbd server
during backup.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/264| 95 +++
tests/qemu-iotests/264.out| 13 +
tests/qemu-iotests/group | 1 +
tests/qemu-io
Vladimir Sementsov-Ogievskiy writes:
> If we want to add some info to errp (by error_prepend() or
> error_append_hint()), we must use the ERRP_AUTO_PROPAGATE macro.
> Otherwise, this info will not be added when errp == &fatal_err
> (the program will exit prior to the error_append_hint() or
> erro
Public bug reported:
qemu-x86_64 version 4.1.0 (qemu-x86_64 version 4.0.0 also have the
issue)
In 64-bit mode (x86_64) the DS, ES, SS or CS segment prefixes should be
ignored; qemu-x86_64 does not ignore them.
example: an x86_64 instructions preceded by FS DS (0x64 0x26) segment
prefixes have th
On Fri, Oct 04, 2019 at 01:20:25PM +0200, Eric Auger wrote:
> Introduce support for GTree migration. A custom save/restore
> is implemented. Each item is made of a key and a data.
>
> If the key is a pointer to an object, 2 VMSDs are passed into
> the GTree VMStateField.
>
> When putting the item
On Wed, Oct 09, 2019 at 05:07:59PM +1100, David Gibson wrote:
> This is a substantial rework to clean up the handling of IRQs in
> spapr. It includes some cleanups to both the XICS and XIVE interrupt
> controller backends, as well as more to the common spapr irq handling
> infrastructure.
>
> The
On 29/09/19 03:57, Tao Xu wrote:
> +} else if (function == 7 && index == 0 && reg == R_ECX) {
> +if (enable_cpu_pm) {
> +ret |= CPUID_7_0_ECX_WAITPKG;
This is incorrect. You should disable WAITPKG if !enable_cpu_pm, but
you should not enable it forcefully if enable_cpu_pm
MVCL is interruptible and we should check for interrupts and process
them after writing back the variables to the registers. Let's check
for any exit requests and exit to the main loop. Introduce a new helper
function for that: cpu_loop_exit_requested().
When booting Fedora 30, I can see a handful
On 09/10/19 10:02, Jan Glauber wrote:
> On Mon, Oct 07, 2019 at 04:58:30PM +0200, Paolo Bonzini wrote:
>> On 07/10/19 16:44, dann frazier wrote:
>>> On Mon, Oct 07, 2019 at 01:06:20PM +0200, Paolo Bonzini wrote:
On 02/10/19 11:23, Jan Glauber wrote:
> I've looked into this on ThunderX2. Th
Vladimir Sementsov-Ogievskiy writes:
> Here is introduced ERRP_AUTO_PROPAGATE macro, to be used at start of
> functions with errp OUT parameter.
>
> It has three goals:
>
> 1. Fix issue with error_fatal & error_prepend/error_append_hint: user
> can't see this additional information, because exit(
On 10/8/19 4:53 PM, Philippe Mathieu-Daudé wrote:
On 10/8/19 4:52 PM, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
Add the 64-bit free running timer. Do not model the COMPARE register
(no IRQ generated).
This timer is used by U-Boot and recent Linux kernels:
https://github.com/u-boot/u-b
Aleksandar Markovic писал 2019-10-08 16:37:
On Monday, October 7, 2019, Alex Bennée
wrote:
Mikhail Abakumov writes:
From: Mikhail Abakumov
Hmm the email got truncated here.
This patch add xml files with gdb registers for mips.
Signed-off-by: Mikhail Abakumov
---
configure | 3 ++
gdb
On 09/10/2019 08:08, David Gibson wrote:
> This method depends only on the active irq controller. Now that we've
> formalized the notion of active controller we can dispatch directly through
> that, rather than dispatching via SpaprIrq with the dual version having
> to do a second conditional disp
On Tue, 8 Oct 2019 20:58:30 +0200
Laszlo Ersek wrote:
> Eduardo, Igor,
>
> On 10/08/19 12:52, Laszlo Ersek wrote:
> > FW_CFG_MAX_CPUS exposes the (exclusive) maximum APIC ID to guest firmware,
> > due to historical reasons. That value is not useful to edk2, however. For
> > supporting VCPU hotpl
> -Original Message-
> From: Lukas Straub
> Sent: Saturday, October 5, 2019 9:06 PM
> To: qemu-devel
> Cc: Zhang, Chen ; Jason Wang
> ; Wen Congyang ;
> Xie Changlong ; Kevin Wolf
> ; Max Reitz ; qemu-block
>
> Subject: [PATCH v6 4/4] colo: Update Documentation for continuous
> replicat
On Wed, Oct 09, 2019 at 05:08:17PM +1100, David Gibson wrote:
> pseries machine type can have one of two different interrupt controllers in
> use depending on feature negotiation with the guest. Usually this is
> invisible to devices, because they route to a common set of qemu_irqs which
> in turn
On 09/10/2019 08:08, David Gibson wrote:
> This method depends only on the active irq controller. Now that we've
> formalized the notion of active controller we can dispatch directly
> through that, rather than dispatching via SpaprIrq with the dual
> version having to do a second conditional disp
On Tue, 24 Sep 2019 at 00:54, Alex Bennée wrote:
>
>
> Beata Michalska writes:
>
> > ARMv8.2 introduced support for Data Cache Clean instructions
> > to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
> > - DV CVADP. Both specify conceptual points in a memory system wher
** Project changed: qemu => libvirt (Ubuntu)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1633508
Title:
libvirt cannot hot insert interfaces to qemu
Status in libvirt package in Ubuntu:
Incomp
On Wed, 9 Oct 2019 17:08:18 +1100
David Gibson wrote:
> Traditional PCI INTx for vfio devices can only perform well if using
> an in-kernel irqchip. Therefore, vfio_intx_update() issues a warning
> if an in kernel irqchip is not available.
>
Can you elaborate on what doesn't "perform well" wi
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> On Tue, Oct 08, 2019 at 05:02:02PM +0100, Dr. David Alan Gilbert wrote:
> >* Wei Yang (richardw.y...@linux.intel.com) wrote:
> >> postcopy_ram_incoming_cleanup() does cleanup for
> >> postcopy_ram_incoming_setup(), while the setup happens only aft
On Tue, 24 Sep 2019 at 18:22, Richard Henderson
wrote:
>
> On 9/10/19 2:56 AM, Beata Michalska wrote:
> > @@ -2229,7 +2229,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t
> > cpregid)
> > #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
> > #define ARM_CP_CURRENTEL (ARM_C
Hi all!
Here is NBD reconnect. Previously, if connection failed all current
and future requests will fail. After the series, nbd-client driver
will try to reconnect unlimited times. During first @reconnect-delay
seconds of reconnecting all requests will wait for the connection,
and if it is establi
On 10/8/19 3:32 PM, Eduardo Habkost wrote:
> On Thu, Sep 26, 2019 at 06:02:47PM +0200, Philippe Mathieu-Daudé wrote:
>> On 9/26/19 5:17 PM, Philippe Mathieu-Daudé wrote:
>>> Convert the reset handler into a proper Device reset method.
>>
>> Marc-André noticed this one is incorrect, because while
Implement reconnect. To achieve this:
1. add new modes:
connecting-wait: means, that reconnecting is in progress, and there
were small number of reconnect attempts, so all requests are
waiting for the connection.
connecting-nowait: reconnecting is in progress, there were a lot of
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the cmsdk-apb-watchdog code away from bottom-half based
> ptimers to the new transaction-based ptimer API. This just requires
> adding begin/commit calls around the various places that modify the
> ptimer state, and using the new ptimer_init() func
On Tue, Oct 08, 2019 at 08:01:11PM +0200, free...@tango.lu wrote:
> Hello List,
>
> I'm using a fairly old KVM version
>
> ii pve-qemu-kvm 2.2-28
> amd64Full virtualization on x86 hardware
>
> don't see much point upgrading either since everything works but I co
08.10.2019 13:09, Vladimir Sementsov-Ogievskiy wrote:
> 08.10.2019 12:39, Greg Kurz wrote:
>> On Tue, 8 Oct 2019 08:41:08 +
>> Vladimir Sementsov-Ogievskiy wrote:
>>
>>> 08.10.2019 10:30, Markus Armbruster wrote:
Vladimir Sementsov-Ogievskiy writes:
> Hi all!
>
> Here is
On 07/10/2019 20.21, Markus Armbruster wrote:
> Markus Armbruster writes:
>
>> Please excuse the attention-grabbing subject.
>
> Again.
>
> [...]
>> So, to make use of QEMU's netmap backend (CONFIG_NETMAP), you have to
>> build and install netmap software from sources. Which pretty much
>
> C
On Wed, Oct 09, 2019 at 10:39:44AM +0200, Markus Armbruster wrote:
> Cc: Marc-André for additional monitor and chardev expertise.
>
> Wolfgang Bumiller writes:
>
> > When a monitor's queue is filled up in handle_qmp_command()
> > it gets suspended. It's the dispatcher bh's job currently to
> > r
On 09/10/2019 04.57, Max Filippov wrote:
> Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in
> it. Fix that by regenerating test_mmuhifi_c3 core overlay and
> re-importing it.
>
> Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core")
> Reported-by: Thomas Huth
> Sig
On 09/10/2019 08:08, David Gibson wrote:
> spapr now has the mechanism of constructing both XICS and XIVE instances of
> the SpaprInterruptController interface. However, only one of the interrupt
> controllers will actually be active at any given time, depending on feature
> negotiation with the g
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> On Wed, Oct 09, 2019 at 01:36:34PM +0800, Peter Xu wrote:
> >On Wed, Oct 09, 2019 at 01:07:56PM +0800, Wei Yang wrote:
> >> On Wed, Oct 09, 2019 at 12:12:25PM +0800, Peter Xu wrote:
> >> >On Wed, Oct 09, 2019 at 09:02:04AM +0800, Wei Yang wrote:
>
On Fri, 4 Oct 2019 12:51:01 +0200
David Hildenbrand wrote:
> Let's use consitent names for the region/section/page table entries and
Can you still fixup s/consitent/consistent/ before picking up? :)
> for the macros to extract relevant parts from virtual address. Make them
> match the definiti
On 09/10/2019 08:08, David Gibson wrote:
> This method depends only on the active irq controller. Now that we've
> formalized the notion of active controller we can dispatch directly
> through that, rather than dispatching via SpaprIrq with the dual
> version having to do a second conditional disp
Public bug reported:
PowerPC KVM Guest fails to boot on current qemu master, bad commit:
e68cd0cb5cf49d334abe17231a1d2c28b846afa2
Env:
HW: IBM Power8
Host Kernel: 5.4.0-rc2-00038-ge3280b54afed
Guest Kernel: 4.13.9-300.fc27.ppc64le
Qemu: https://github.com/qemu/qemu.git (master)
Libvirt: 5.4.0
Gu
On 09.10.19 12:45, Cornelia Huck wrote:
> On Fri, 4 Oct 2019 12:51:01 +0200
> David Hildenbrand wrote:
>
>> Let's use consitent names for the region/section/page table entries and
>
> Can you still fixup s/consitent/consistent/ before picking up? :)
Most certainly :) Thanks!
--
Thanks,
Da
* Alex Bennée (alex.ben...@linaro.org) wrote:
> From: "Vanderson M. do Rosario"
>
> These commands allow the exploration of TBs generated by the TCG.
> Understand which one hotter, with more guest/host instructions... and
> examine their guest, host and IR code.
>
> The goal of this command is t
As an alternative to passing to firmware topology info via new fwcfg files
so it could recreate APIC IDs based on it and order CPUs are enumerated,
extend CPU hotplug interface to return APIC ID as response to the new command
CPHP_GET_CPU_ID_CMD.
CC: Laszlo Ersek
CC: Eduardo Habkost
CC: "Micha
* Eric Auger (eric.au...@redhat.com) wrote:
> Introduce support for GTree migration. A custom save/restore
> is implemented. Each item is made of a key and a data.
>
> If the key is a pointer to an object, 2 VMSDs are passed into
> the GTree VMStateField.
>
> When putting the items, the tree is t
On Wednesday, October 9, 2019, Mikhail Abakumov
wrote:
> Aleksandar Markovic писал 2019-10-08 16:37:
>
>> On Monday, October 7, 2019, Alex Bennée
>> wrote:
>>
>> Mikhail Abakumov writes:
>>>
>>> From: Mikhail Abakumov
>>>
>>> Hmm the email got truncated here.
>>>
>>>
This patch add x
QEMU returns 0, in case of erro or invalid value in 'Command field',
make spec match reality, i.e.
Also fix returned value description in case 'Command field' == 0x0,
it's in not PXM but CPU selector value with pending event
Signed-off-by: Igor Mammedov
---
docs/specs/acpi_cpu_hotplug.txt | 5
08.10.2019 15:05, Markus Armbruster wrote:
> Vladimir Sementsov-Ogievskiy writes:
>
>> 08.10.2019 12:08, Markus Armbruster wrote:
>>> Vladimir Sementsov-Ogievskiy writes:
>>>
Error **errp is almost always OUT-argument: it's assumed to be NULL, or
pointer to NULL-initialized pointer, or
On Wed, 9 Oct 2019 12:21:06 +1100
David Gibson wrote:
> On Tue, Oct 08, 2019 at 07:33:17AM -0400, Igor Mammedov wrote:
> > rs6000mc_realize() violates memory_region_allocate_system_memory() contract
> > by calling it multiple times which could break -mem-path. Replace it with
> > plain memory_reg
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