Hi Tomáš
On Wed, Sep 18, 2019 at 3:23 PM Tomáš Golembiovský wrote:
>
> On Mon, Sep 16, 2019 at 04:31:49PM +0400, Marc-André Lureau wrote:
> > Hi
> >
> > On Thu, Aug 29, 2019 at 8:06 PM Tomáš Golembiovský
> > wrote:
> > >
> > > Add command for reporting devices on Windows guest. The intent is no
The WHPX build is broken since commit 12e9493df92 which removed the
"hw/boards.h" where MachineState is declared:
$ ./configure \
--enable-hax --enable-whpx
$ make x86_64-softmmu/all
[...]
CC x86_64-softmmu/target/i386/whpx-all.o
target/i386/whpx-all.c: In function 'whpx_acc
Currently the Avocado framework does not distinct the time spent
downloading assets vs. the time spent running a test. With big
assets (like a full VM image) the tests likely fail.
This is a limitation known by the Avocado team.
Until this issue get fixed, do not run this tests automatically.
Tes
On Tue, 17 Sep 2019 17:00:56 +0100
"Dr. David Alan Gilbert (git)" wrote:
> From: "Dr. David Alan Gilbert"
>
> The virtio-fs virtio device provides shared file system access using
> the FUSE protocol carried over virtio.
> The actual file server is implemented in an external vhost-user-fs device
On Tue, 17 Sep 2019 17:00:54 +0100
"Dr. David Alan Gilbert (git)" wrote:
> From: "Dr. David Alan Gilbert"
>
> Hi,
> This set of patches adds the core of the virtio-fs support to qemu;
> it's marked experimental since the kernel patch isn't in yet; but
> it's nearly there; the spec has passed
Hi all!
Here is a proposal (three of them, actually) of auto propagation for
local_err, to not call error_propagate on every exit point, when we
deal with local_err.
It also may help make Greg's series[1] about error_append_hint smaller.
See definitions and examples below.
I'm cc-ing to this RF
On 18/09/2019 00.29, John Snow wrote:
>
>
> On 9/16/19 10:56 AM, Vladimir Sementsov-Ogievskiy wrote:
[...]
>> Finally do we support something except linux for iotests?
>> for bash tests _supported_os also used only with "Linux" in 87 tests..
The iotests in the "auto" group are supposed to work o
This is in preparation for adding support for ARM64 platforms
where it doesn't use port mapped IO for ACPI IO space. We are
making changes so that MMIO region can be accommodated
and board can pass the base address into the aml build function.
Also move few MEMORY_* definitions to header so that o
From: Samuel Ortiz
With Hardware-reduced ACPI, the GED device will manage ACPI
hotplug entirely. As a consequence, make the memory specific
events AML generation optional. The code will only be added
when the method name is not NULL.
Signed-off-by: Samuel Ortiz
Signed-off-by: Shameer Kolothum
From: Eric Auger
This patch adds the memory hot-plug/hot-unplug infrastructure
in machvirt. The device memory is not yet exposed to the Guest
either through DT or ACPI and hence both cold/hot plug of memory
is explicitly disabled for now.
Signed-off-by: Eric Auger
Signed-off-by: Kwangwoo Lee
S
Documents basic concepts of ACPI Generic Event device(GED)
and interface between QEMU and the ACPI BIOS.
Signed-off-by: Shameer Kolothum
Reviewed-by: Eric Auger
---
Addressed Peter's comments,
-changed to rst format.
-typo/grammer corrections.
---
docs/specs/acpi_hw_reduced_hotplug.rst | 70 +
This series is an attempt to provide device memory hotplug support
on ARM virt platform. This is based on Eric's recent works here[1]
and carries some of the pc-dimm related patches dropped from his
series.
The kernel support for arm64 memory hot add was added recently by
Robin and hence the gues
This initializes the GED device with base memory and irq, configures
ged memory hotplug event and builds the corresponding aml code. With
this, both hot and cold plug of device memory is enabled now for Guest
with ACPI boot. Memory cold plug support with Guest DT boot is not yet
supported.
As DSDT
Generate Memory Affinity Structures for PC-DIMM ranges.
Also, Linux and Windows need ACPI SRAT table to make memory hotplug
work properly, however currently QEMU doesn't create SRAT table if
numa options aren't present on CLI. Hence add support(>=4.2) to
create numa node automatically (auto_enable
From: Samuel Ortiz
The ACPI Generic Event Device (GED) is a hardware-reduced specific
device[ACPI v6.1 Section 5.6.9] that handles all platform events,
including the hotplug ones. This patch generates the AML code that
defines GEDs.
Platforms need to specify their own GED Event bitmap to describ
18.09.2019 2:45, John Snow wrote:
> verify_platform will check an explicit whitelist and blacklist instead.
> The default will now be assumed to be allowed to run anywhere.
>
> For tests that do not specify their platforms explicitly, this has the effect
> of
> enabling these tests on non-linux p
This is in preparation of using GED device for
system_powerdown event. Make the powerdown notifier
registration independent of create_gpio() fn.
Signed-off-by: Shameer Kolothum
Reviewed-by: Eric Auger
Reviewed-by: Igor Mammedov
---
hw/arm/virt.c | 12
include/hw/arm/virt.h
For machines 4.2 or higher with ACPI boot use GED for system_powerdown
event instead of GPIO. Guest boot with DT still uses GPIO.
Signed-off-by: Shameer Kolothum
Reviewed-by: Eric Auger
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 8
hw/arm/virt-acpi-build.
This adds numamem and memhp tests for arm/virt platform.
Signed-off-by: Shameer Kolothum
Reviewed-by: Igor Mammedov
---
v10-->v11
Added Igor's R-by.
In order to avoid "make check" failure, the files listed in patch #10
has to be added to tests/data/acpi/virt folder before this patch.
---
test
The following changes since commit f8c3db33a5e863291182f8862ddf81618a7c6194:
target/sparc: Switch to do_transaction_failed() hook (2019-09-17 12:01:00
+0100)
are available in the Git repository at:
https://github.com/stefanha/qemu.git tags/tracing-pull-request
for you to fetch changes up t
This is in preparation to add numamem and memhp tests to
arm/virt platform. The bios-tables-test-allowed-diff.h
is updated with a list of expected ACPI tables that needs to be
present in tests/data/acpi/virt folder.
Signed-off-by: Shameer Kolothum
---
v10 --> v11
As per Michael's suggestion upda
Am 18.09.2019 um 14:11 schrieb Philippe Mathieu-Daudé:
> The WHPX build is broken since commit 12e9493df92 which removed the
> "hw/boards.h" where MachineState is declared:
>
> $ ./configure \
> --enable-hax --enable-whpx
>
> $ make x86_64-softmmu/all
> [...]
> CC x86_64-softmmu
From: Alexey Kardashevskiy
This adds a trace point which prints every loaded image. This includes
bios/firmware/kernel/initradmdisk/pcirom.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190613050937.124903-1-...@ozlabs.ru>
Signed-off-by: Stefan Hajnoczi
From: Philippe Mathieu-Daudé
Event format ending with newlines confuse the trace reports.
Forbid them.
Add a check to refuse new format added with trailing newline:
$ make
[...]
GEN hw/misc/trace.h
Traceback (most recent call last):
File "scripts/tracetool.py", line 152, in
From: Philippe Mathieu-Daudé
While the tracing framework does not forbid trailing newline in
events format string, using them lead to confuse output.
It is the responsibility of the backend to properly end an event
line.
Some of our formats have trailing newlines, remove them.
[Fixed typo in co
Please check if this commit has solved the issue:
https://git.qemu.org/?p=qemu.git;a=commit;h=ebb6ff25cd888a52a64a9adc3692541c6d1d9a42
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1839428
Title:
18.09.2019 2:45, John Snow wrote:
> Like script_main, but doesn't require a single point of entry.
> Replace all existing initialization sections with this drop-in replacement.
>
> This brings debug support to all existing script-style iotests.
>
> Any specification for supported_oses=['linux'] w
On 18.09.19 13:24, Alex Bennée wrote:
>
> David Hildenbrand writes:
>
>> On 18.09.19 11:47, Alex Bennée wrote:
>>>
>>> David Hildenbrand writes:
>>>
Let's add the simple test based on the example from the PoP.
Signed-off-by: David Hildenbrand
---
tests/tcg/s390x/Makef
Ah I though these would be enabled by default for x86 hosts. I guess we
need another build entry in .Travis even if we can't test it there.
On Wed, 18 Sep 2019, 13:11 Philippe Mathieu-Daudé,
wrote:
> The WHPX build is broken since commit 12e9493df92 which removed the
> "hw/boards.h" where Machin
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsce' instruction.
'mffsce' is identical to 'mffs', except that it also clears the exception
enabl
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffscrn' and 'mffscrni' instructions.
'mffscrn' and 'mffscrni' are similar to 'mffsl', except they d
From: "Paul A. Clarke"
There are FPSCR-related defines in target/ppc/cpu.h which can be used in
place of constants and explicit shifts which arguably improve the code a
bit in places.
Signed-off-by: Paul A. Clarke
---
I confirmed that the generated assembly is identical before and after
the pat
We now know that gen15a is called z15.
Signed-off-by: Christian Borntraeger
---
target/s390x/cpu_models.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 1d16d7d5e794..009afc38b92d 100644
--- a/target/s390x/cpu_model
18.09.2019 2:45, John Snow wrote:
> We can turn logging on/off globally instead of per-function.
>
> Remove use_log from run_job, and use python logging to turn on
> diffable output when we run through a script entry point.
>
> iotest 245 changes output order due to buffering reasons.
Interestin
On 9/18/19 7:31 AM, Paul A. Clarke wrote:
> From: "Paul A. Clarke"
>
> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
> This patch adds support for 'mffscrn' and 'mffscrni' instructions.
>
> 'mffsc
On 18.09.19 16:42, Christian Borntraeger wrote:
> We now know that gen15a is called z15.
>
> Signed-off-by: Christian Borntraeger
> ---
> target/s390x/cpu_models.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
> in
On 9/18/19 7:32 AM, Paul A. Clarke wrote:
> From: "Paul A. Clarke"
>
> There are FPSCR-related defines in target/ppc/cpu.h which can be used in
> place of constants and explicit shifts which arguably improve the code a
> bit in places.
>
> Signed-off-by: Paul A. Clarke
> ---
> I confirmed that
On 9/18/19 4:33 AM, Alex Bennée wrote:
>>> Ahh I was going to hardcode the arm madd instruction in as the builtin
>>> wasn't expanding. I tried setting -march in the CFLAGS but that didn't
>>> trigger it either on my buster arm-hf compiler. Any ideas how to get the
>>> compiler to do the right thin
12.09.2019 16:56, Max Reitz wrote:
> mirror_exit_common() may be called twice (if it is called from
> mirror_prepare() and fails, it will be called from mirror_abort()
> again).
>
> In such a case, many of the pointers in the MirrorBlockJob object will
> already be freed. This can be seen most re
From: Guenter Roeck
Add support for loading initrd with "-initrd "
to the sifive_u machine. This lets us boot into Linux without
disk drive.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 20 +---
1 file chan
The following changes since commit f8c3db33a5e863291182f8862ddf81618a7c6194:
target/sparc: Switch to do_transaction_failed() hook (2019-09-17 12:01:00
+0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1-v3
for you to fetch c
From: Guenter Roeck
The riscv uart needs valid clocks. This requires a refereence
to the clock node. Since the SOC clock is not emulated by qemu,
add a reference to a fixed clock instead. The clock-frequency
entry in the uart node does not seem to be necessary, so drop it.
In addition to a refer
From: Philippe Mathieu-Daudé
The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 3 ++-
targ
From: Guenter Roeck
The correct property name is clock-names, not clocks-names.
Without this patch, the Ethernet driver fails to instantiate with
the following error.
macb 100900fc.ethernet: failed to get macb_clk (-2)
macb: probe of 100900fc.ethernet failed with error -2
Signed-off-by: Guente
From: Bin Meng
This adds 'info mem' command for RISC-V, to show virtual memory
mappings that aids debugging.
Rather than showing every valid PTE, the command compacts the
output by merging all contiguous physical address mappings into
one block and only shows the merged block mapping details.
S
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Behrens
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 12
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed, 1
From: Alistair Francis
Let's create a function that tests if floating point support is
enabled. We can then protect all floating point operations based on if
they are enabled.
This patch so far doesn't change anything, it's just preparing for the
Hypervisor support for floating point operations.
From: Philippe Mathieu-Daudé
Use the always-compiled trace events, remove the now unused
RISCV_DEBUG_PMP definition.
Note pmpaddr_csr_read() could previously do out-of-bound accesses
passing addr_index >= MAX_RISCV_PMPS.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Sign
From: Bin Meng
At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Da
From: Bin Meng
Commit a27bd6c779ba ("Include hw/qdev-properties.h less") wrongly
added "hw/hw.h" to sifive_prci.c and sifive_test.c.
Another inclusion of "hw/hw.h" was later added via
commit 650d103d3ea9 ("Include hw/hw.h exactly where needed"), that
resulted in duplicated inclusion of "hw/hw.h"
From: Alistair Francis
Update the Hypervisor CSR addresses to match the v0.4 spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
From: Bin Meng
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/virt.c | 24 +
From: Bin Meng
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin
From: Bin Meng
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4
hw/riscv/spike.c| 1 -
hw/riscv/virt.c
From: Bin Meng
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_hel
From: Bin Meng
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_e.c | 23 ---
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw/r
From: Bin Meng
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifiv
From: Bin Meng
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_test.c | 4
include/hw/riscv/sifive_test.h | 3 ++-
2 files changed
From: Bin Meng
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 11 +++
From: Bin Meng
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e_prci.c | 2 +
From: Bin Meng
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 --
hw/riscv/virt.c | 2 --
2 file
From: Bin Meng
Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create homogeneous harts. Exact the
hart realize to a separate routine in preparation for supporting
multiple hart arrays.
Note th
From: Bin Meng
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_
From: Bin Meng
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate het
From: Bin Meng
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
[Palmer: Set default CPUs to 2]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 -
include/hw/riscv/sifive_u.h | 2 ++
From: Bin Meng
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 8 +---
hw/riscv/sifive_test.c | 5 +++--
hw/riscv/sifive_uart.
From: Bin Meng
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by:
From: Bin Meng
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/si
From: Bin Meng
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
hw/riscv/sifive_uart.c | 1 -
3 files chang
From: Bin Meng
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 23 +++
i
From: Bin Meng
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 7 ---
1
From: Bin Meng
This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Franci
From: Bin Meng
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/sifive_cpu.h | 31 +++
include/hw/riscv/sifive_
From: Bin Meng
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 24 +++-
include/hw/risc
From: Bin Meng
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/si
From: Bin Meng
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.
Add a new "hartid-base" property so that hartid number can be
assigned based on the proper
From: Bin Meng
In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.
Signed-off-
From: Bin Meng
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 ++--
include/hw/riscv/sifive_u.h
From: Bin Meng
With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv64-sifive_u-fw_j
From: Atish Patra
Use both the generic register name and ABI name for the general purpose
registers and floating point registers.
Signed-off-by: Atish Patra
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 19 +++
1
From: Bin Meng
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c
From: Bin Meng
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing
From: Bin Meng
At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.
Not like other GEM variants, the FU540-specific GEM has a management
block to con
This pull request is not for master.
Hi Conny,
The following changes since commit f8c3db33a5e863291182f8862ddf81618a7c6194:
target/sparc: Switch to do_transaction_failed() hook (2019-09-17 12:01:00
+0100)
are available in the Git repository at:
https://github.com/davidhildenbrand/qemu.git
From: Alistair Francis
This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.
Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
target/riscv/cs
Perform the checks documented in the PoP.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index c31cf49593..7dfa848744 100644
--- a/targ
From: Bin Meng
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3 insert
From: Alistair Francis
Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/r
We'll have to zero-out unused bit positions, so make sure to write the
addresses back.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/target/s390x/mem_helper.c
From: KONRAD Frederic
While debugging an application with GDB the following might happen:
(gdb) return
Make xxx return now? (y or n) y
Could not fetch register "fflags"; remote failure reply 'E14'
This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
number (8). It should u
Let's perform the documented checks.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 86238e0163..20e1ac0ea9 100644
--- a/ta
We use the marker "-1" for "no exception". s390_cpu_do_interrupt() might
get confused by that.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/s390x/mem_helper.c b/targ
Process max 4k bytes at a time, writing back registers between the
accesses. The instruction is interruptible.
"For operands longer than 2K bytes, access exceptions are not
recognized for locations more than 2K bytes beyond the current location
being processed."
Note that on z/Architect
Triggered by a review comment from Richard, also MVCOS has a 32-bit
length in 24/31-bit addressing mode. Add a new helper.
Rename wrap_length() to wrap_length31().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 14 +++---
1 file changed,
Bit position 32-55 of general register 0 must be zero.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 41d7336a1a..ec27be174b 100644
-
We have to zero out unused bits in 24 and 31-bit addressing mode.
Provide a new helper.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/target/s390x/mem_hel
... and don't perform any move in case the length is zero.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 320e9ee65c..41d7336a1a 1
We can process a maximum of 256 bytes, crossing two pages. Calculate the
accessed range upfront - src is accessed right-to-left.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
Let's increment the length once.
While at it, cleanup the comment. The memset() example is given as a
programming note in the PoP, so drop the description.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 20
1 file changed, 1
Let's use the new helper, that also detects destructive overlaps when
wrapping.
We'll make the remaining code (e.g., fast_memmove()) aware of wrapping
later.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/mem_helper.c | 2 +-
1 file changed, 1 insertion(+), 1
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