From: Aleksandar Markovic
FIOGETOWN and FIOSETOWN ioctls have platform-specific definitions,
hence non-standard definition in QEMU too.
Other than that, they both have a single integer argument, and their
functionality is emulated in a straightforward way.
Signed-off-by: Aleksandar Markovic
Re
From: Richard Henderson
Limit the virtual address space for M-profile cpus to 2GB,
so that we avoid all of the magic addresses in the top half
of the M-profile system map.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-Id: <20190822185929.16891-3-richard.hender...@linaro.o
filename is only used to open the file if AT_EXECFD is not provided.
But exec_path already contains the path of the file to open.
Remove filename as it is only used in main.c whereas exec_path is
also used in syscall.c.
Fixes: d088d664f201 ("linux-user: identify running binary in /proc/self/exe")
From: Richard Henderson
Turn the scalar macro into a functional macro. Move the creation
of the cpu up a bit within main() so that we can pass it to the
invocation of MAX_RESERVED_VA. Delay the validation of the -R
parameter until MAX_RESERVED_VA is computed.
So far no changes to any of the MA
From: Aleksandar Markovic
FDRESET, FDRAWCMD, FDTWADDLE, and FDEJECT ioctls are misc commands
for controlling a floppy drive.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Message-Id: <1567601968-26946-7-git-send-email-aleksandar.marko...@rt-rk.com>
Signed-off-by: Laurent Vivie
From: Josh Kunz
This is needed to support debugging PIE ELF binaries running under QEMU
user mode. Currently, `code_offset` and `data_offset` remain unset for
all ELF binaries, so GDB is unable to correctly locate the position of
the binary's text and data.
The fields `code_offset`, and `data_of
From: Max Filippov
QEMU_STRACE and QEMU_RAND_SEED are handled by the parse_args, no need to
do it again in main.
Signed-off-by: Max Filippov
Reviewed-by: Laurent Vivier
Message-Id: <20190906165736.5612-1-jcmvb...@gmail.com>
Signed-off-by: Laurent Vivier
---
linux-user/main.c | 7 ---
1 f
Am 11.09.2019 um 08:20 hat Max Reitz geschrieben:
> On 10.09.19 16:52, Kevin Wolf wrote:
> > Am 09.08.2019 um 18:13 hat Max Reitz geschrieben:
> >> If the driver does not implement bdrv_get_allocated_file_size(), we
> >> should fall back to cumulating the allocated size of all non-COW
> >> children
On Tue, Sep 10, 2019 at 05:34:57PM +0200, Johannes Berg wrote:
> On Tue, 2019-09-10 at 11:33 -0400, Michael S. Tsirkin wrote:
> > On Tue, Sep 10, 2019 at 05:14:36PM +0200, Johannes Berg wrote:
> > > Is any of you familiar with the process of getting a virtio device ID
> > > assigned, and if so, do
From: Aleksandar Markovic
FDMSGON and FDMSGOFF switch informational messages of floppy drives
on and off.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Reviewed-by: Laurent Vivier
Message-Id: <1567601968-26946-6-git-send-email-aleksandar.marko...@rt-rk.com>
Signed-off-by: Lau
On 10.09.19 18:11, Maxim Levitsky wrote:
> On Tue, 2019-09-10 at 14:41 +0200, Max Reitz wrote:
>> While it is more likely that transfers complete after some file
>> descriptor has data ready to read, we probably should not rely on it.
>> Better be safe than sorry and call curl_multi_check_completio
Quick update...
> value INT_MAX (4294967295) seems WRONG for qemu_futex_wait():
>
> - EV_BUSY, being -1, and passed as an argument qemu_futex_wait(void *,
> unsigned), is a two's complement, making argument into a INT_MAX when
> that's not what is expected (unless I missed something).
>
> *** If
Am 10.09.2019 um 21:07 hat Eric Blake geschrieben:
> On 9/10/19 1:58 PM, Thomas Huth wrote:
> > Our "tests" directory is very overcrowded - we store the qtests,
> > unit test and other files there. That makes it difficult to
> > determine which file belongs to each test subsystem, and the
> > wildc
11.09.2019. 08.35, "liuzhiwei" је написао/ла:
>
> Features:
> * support specification riscv-v-spec-0.7.1(
https://content.riscv.org/wp-content/uploads/2019/06/17.40-Vector_RISCV-20190611-Vectors.pdf
).
Hi, Zhivei.
The linked document is a presentation, outlining general concepts of the
instruc
> +static void *dsound_get_buffer_in(HWVoiceIn *hw, size_t *size)
> {
> +int err;
> +void *ret;
> +n
> +hr = IDirectSoundCaptureBuffer_GetCurrentPosition(dscb, &cpos, NULL);
Huh? Stray 'n' here. That can hardly survived a build test ...
Removed it. Builds now. Continuing testing
On 11/09/2019 06:04, David Gibson wrote:
> Certain old guest versions don't understand the radix MMU introduced with
> POWER ISA 3.0, but incorrectly select it if presented with the option at
> CAS time. We workaround this in qemu by explicitly excluding the radix
> (and other ISA 3.0 linked) opti
Le 10/09/2019 à 22:02, Philippe Mathieu-Daudé a écrit :
> On 9/10/19 7:07 PM, Cleber Rosa wrote:
>> On Tue, Sep 10, 2019 at 06:34:30PM +0200, Philippe Mathieu-Daudé wrote:
>>> This test boots a Linux kernel on a Quadra 800 board
>>> and verify the serial is working.
>>>
>>> Example:
>>>
>>> $ avo
Patchew URL: https://patchew.org/QEMU/20190910193347.16000-1-laur...@vivier.eu/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v11 0/9] hw/m68k: add Apple Machintosh Quadra 800
machine
Message-id: 20190910193347.16
02.08.2019. 18.29, "Philippe Mathieu-Daudé" је
написао/ла:
>
> Cc'ing broader MIPS audience.
>
> On 8/2/19 6:04 PM, Peter Maydell wrote:
> > This patchset converts the MIPS target away from the
> > old broken do_unassigned_access hook to the new (added in
> > 2017...) do_transaction_failed hook.
>
On Wed, 11 Sep 2019 14:04:46 +1000
David Gibson wrote:
> Certain old guest versions don't understand the radix MMU introduced with
> POWER ISA 3.0, but incorrectly select it if presented with the option at
> CAS time. We workaround this in qemu by explicitly excluding the radix
> (and other ISA
On 11/09/2019 06:04, David Gibson wrote:
> From: Alexey Kardashevskiy
>
> Add a missing g_free(fdt) if the resulting tree is bigger
> than the space allocated by SLOF.
>
> Signed-off-by: Alexey Kardashevskiy
> Signed-off-by: David Gibson
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
>
On 11/09/2019 06:04, David Gibson wrote:
> The number of NUMA nodes in the system is fixed from the command line.
> Therefore, there's no need to recalculate it at reset time, and we can
> determine the special gpu_numa_id value used for NVLink2 devices at init
> time.
>
> This simplifies the rese
On Wed, 11 Sep 2019 14:04:47 +1000
David Gibson wrote:
> The number of NUMA nodes in the system is fixed from the command line.
> Therefore, there's no need to recalculate it at reset time, and we can
> determine the special gpu_numa_id value used for NVLink2 devices at init
> time.
>
> This sim
On Tue, Sep 10, 2019 at 05:14:36PM +0200, Johannes Berg wrote:
> On Tue, 2019-09-10 at 17:03 +0200, Stefan Hajnoczi wrote:
> >
> > > Now, this means that the CPU (that's part of the simulation) has to
> > > *wait* for the device to add an entry to the simulation calendar in
> > > response to the k
On Wed, 11 Sep 2019 14:04:48 +1000
David Gibson wrote:
> From: Alexey Kardashevskiy
>
> Add a missing g_free(fdt) if the resulting tree is bigger
> than the space allocated by SLOF.
>
> Signed-off-by: Alexey Kardashevskiy
> Signed-off-by: David Gibson
> ---
Reviewed-by: Greg Kurz
> hw/pp
On 11.09.19 08:55, Kevin Wolf wrote:
> Am 11.09.2019 um 08:20 hat Max Reitz geschrieben:
>> On 10.09.19 16:52, Kevin Wolf wrote:
>>> Am 09.08.2019 um 18:13 hat Max Reitz geschrieben:
If the driver does not implement bdrv_get_allocated_file_size(), we
should fall back to cumulating the all
Patchew URL: https://patchew.org/QEMU/20190910163600.19971-1-laur...@vivier.eu/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/15] Linux user for 4.2 patches
Message-id: 20190910163600.19971-1-laur...@vivier.eu
Ty
On 11/09/2019 14:04, David Gibson wrote:
> Certain old guest versions don't understand the radix MMU introduced with
> POWER ISA 3.0, but incorrectly select it if presented with the option at
> CAS time. We workaround this in qemu by explicitly excluding the radix
> (and other ISA 3.0 linked) o
On 11/09/2019 14:04, David Gibson wrote:
> We've made several changes in the past to the machine reset order to fix
> specific problems. However, we've ended up with an order that doesn't make
> a lot of logical sense. This is an attempt to rectify this.
>
> First we reset global CAS options,
On 11/09/2019 14:04, David Gibson wrote:
> The number of NUMA nodes in the system is fixed from the command line.
> Therefore, there's no need to recalculate it at reset time, and we can
> determine the special gpu_numa_id value used for NVLink2 devices at init
> time.
>
> This simplifies the r
On Tuesday 10 September 2019 02:18 PM, Greg Kurz wrote:
> Hi Aravinda,
>
> Sorry for not being able to review the whole series in one pass,
> and thus forcing you to poste more versions... but I have some
> more remarks about migration.
That's fine. In fact I have to thank you for your time fo
On 10.09.19 17:41, Peter Lieven wrote:
> libnfs recently added support for unmounting. Add support
> in Qemu too.
>
> Signed-off-by: Peter Lieven
> ---
> block/nfs.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/block/nfs.c b/block/nfs.c
> index 2c98508275..f39acfdb28 100644
> ---
On Wed, Sep 11, 2019 at 05:40:58PM +1000, Alexey Kardashevskiy wrote:
>
>
> On 11/09/2019 14:04, David Gibson wrote:
> > We've made several changes in the past to the machine reset order to fix
> > specific problems. However, we've ended up with an order that doesn't make
> > a lot of logical se
On 11/09/2019 06:04, David Gibson wrote:
> We've made several changes in the past to the machine reset order to fix
> specific problems. However, we've ended up with an order that doesn't make
> a lot of logical sense. This is an attempt to rectify this.
There are some more problems though. See
On Wed, 11 Sep 2019 14:04:49 +1000
David Gibson wrote:
> From: Alexey Kardashevskiy
>
> The device tree build by QEMU at the machine reset time is used by SLOF
> to build its internal device tree but the node names are not preserved
> exactly so when QEMU provides a device tree update in respon
On 11/09/2019 08.58, Kevin Wolf wrote:
> Am 10.09.2019 um 21:07 hat Eric Blake geschrieben:
>> On 9/10/19 1:58 PM, Thomas Huth wrote:
>>> Our "tests" directory is very overcrowded - we store the qtests,
>>> unit test and other files there. That makes it difficult to
>>> determine which file belongs
On Wed, Aug 21, 2019 at 06:33:33PM +0200, Damien Hedde wrote:
> This commit defines an interface allowing multi-phase reset. This aims
> to solve a problem of the actual single-phase reset (built in
> DeviceClass and BusClass): reset behavior is dependent on the order
> in which reset handlers are
Aleksandar Markovic writes:
> 10.09.2019. 21.34, "Alex Bennée" је написао/ла:
>>
>> This is preparatory for plugins which will want to report the
>> architecture to plugins. Move the ELF_ARCH definition out of the
>> loader and into its own header.
>>
>> Signed-off-by: Alex Bennée
>> ---
>
>
Alex Bennée writes:
> Lets keep all the Elf manipulation bits together. Also rename the file
> to better reflect how it is used and add a little header to the file.
>
> Signed-off-by: Alex Bennée
> ---
> hw/core/loader.c| 4 ++--
It is arguable this could be a priv
Mao Zhongyi writes:
> ‘data’ has the possibility of memory leaks， so use the
> glic macros g_autofree recommended by CODING_STYLE.rst
nit: glib
> to automatically release the memory that returned from
> g_malloc().
>
> Cc: arm...@redhat.com
> Cc: laur...@vivier.eu
> Cc: tony.ngu...@bt.com
> C
The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1:
Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07'
into staging (2019-09-09 09:48:34 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-
From: Guenter Roeck
The correct property name is clock-names, not clocks-names.
Without this patch, the Ethernet driver fails to instantiate with
the following error.
macb 100900fc.ethernet: failed to get macb_clk (-2)
macb: probe of 100900fc.ethernet failed with error -2
Signed-off-by: Guente
On Fri, 23 Aug 2019 16:38:15 PDT (-0700), Alistair Francis wrote:
To handle the new Hypervisor CSR register swapping let's use pointers.
We only need to convert the MIE and MSTATUS CSRs. With the exception of
MIP all of the other CSRs that swap with virtulsation changes are S-Mode
only, so we ca
From: Guenter Roeck
The riscv uart needs valid clocks. This requires a refereence
to the clock node. Since the SOC clock is not emulated by qemu,
add a reference to a fixed clock instead. The clock-frequency
entry in the uart node does not seem to be necessary, so drop it.
In addition to a refer
From: Alistair Francis
Let's create a function that tests if floating point support is
enabled. We can then protect all floating point operations based on if
they are enabled.
This patch so far doesn't change anything, it's just preparing for the
Hypervisor support for floating point operations.
From: Philippe Mathieu-Daudé
Use the always-compiled trace events, remove the now unused
RISCV_DEBUG_PMP definition.
Note pmpaddr_csr_read() could previously do out-of-bound accesses
passing addr_index >= MAX_RISCV_PMPS.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Sign
From: Guenter Roeck
Add support for loading initrd with "-initrd "
to the sifive_u machine. This lets us boot into Linux without
disk drive.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 20 +---
1 file chan
From: Philippe Mathieu-Daudé
The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 3 ++-
targ
From: Bin Meng
This adds a helper routine for finding firmware. It is currently
used only for "-bios default" case.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 22 +++---
include/hw/riscv/boot.h | 1 +
2 f
From: Bin Meng
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_hel
From: Alistair Francis
Update the Hypervisor CSR addresses to match the v0.4 spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Behrens
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 12
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed, 1
From: Bin Meng
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 --
hw/riscv/virt.c | 2 --
2 file
From: Bin Meng
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_test.c | 4
include/hw/riscv/sifive_test.h | 3 ++-
2 files changed
From: Bin Meng
This adds 'info mem' command for RISC-V, to show virtual memory
mappings that aids debugging.
Rather than showing every valid PTE, the command compacts the
output by merging all contiguous physical address mappings into
one block and only shows the merged block mapping details.
S
From: Bin Meng
At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Da
From: Bin Meng
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
hw/riscv/sifive_uart.c | 1 -
3 files chang
From: Bin Meng
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4
hw/riscv/spike.c| 1 -
hw/riscv/virt.c
From: Bin Meng
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 8 +---
hw/riscv/sifive_test.c | 5 +++--
hw/riscv/sifive_uart.
From: Bin Meng
Commit a27bd6c779ba ("Include hw/qdev-properties.h less") wrongly
added "hw/hw.h" to sifive_prci.c and sifive_test.c.
Another inclusion of "hw/hw.h" was later added via
commit 650d103d3ea9 ("Include hw/hw.h exactly where needed"), that
resulted in duplicated inclusion of "hw/hw.h"
From: Bin Meng
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/virt.c | 24 +
From: Bin Meng
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin
From: Bin Meng
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.
Add a new "hartid-base" property so that hartid number can be
assigned based on the proper
From: Bin Meng
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_e.c | 23 ---
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw/r
From: Bin Meng
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifiv
From: Bin Meng
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 11 +++
From: Bin Meng
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 +++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/
From: Bin Meng
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/sifive_cpu.h | 31 +++
include/hw/riscv/sifive_
From: Bin Meng
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by:
From: Bin Meng
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_
From: Bin Meng
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c
From: Bin Meng
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 7 ---
1
From: Bin Meng
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e_prci.c | 2 +
From: Bin Meng
Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create homogeneous harts. Exact the
hart realize to a separate routine in preparation for supporting
multiple hart arrays.
Note th
From: Bin Meng
In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.
Signed-off-
From: Bin Meng
This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Franci
From: Bin Meng
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate het
From: Bin Meng
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 24 +++-
include/hw/risc
From: Bin Meng
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3 insert
From: Bin Meng
With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv64-sifive_u-fw_j
From: Bin Meng
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 ++--
include/hw/riscv/sifive_u.h
From: Bin Meng
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 23 +++
i
From: Alistair Francis
This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.
Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
target/riscv/cs
From: Bin Meng
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/si
On Tue, 10 Sep 2019, Alex Bennée wrote:
diff --git a/include/elf/elf-types.inc.h b/include/elf/elf-types.inc.h
new file mode 100644
index 000..35163adb2b5
--- /dev/null
+++ b/include/elf/elf-types.inc.h
@@ -0,0 +1,63 @@
+/*
+ * Elf Type Specialisation
+ *
+ * Copyright (c) 2019
+ * Writte
From: Bin Meng
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing
From: Alistair Francis
Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/r
From: Bin Meng
At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.
Not like other GEM variants, the FU540-specific GEM has a management
block to con
From: Bin Meng
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/si
Patchew URL: https://patchew.org/QEMU/20190910163600.19971-1-laur...@vivier.eu/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/15] Linux user for 4.2 patches
Message-id: 20190910163600.19971-1-laur...@vivier.eu
Ty
Am 11.09.2019 um 09:37 hat Max Reitz geschrieben:
> On 11.09.19 08:55, Kevin Wolf wrote:
> > Am 11.09.2019 um 08:20 hat Max Reitz geschrieben:
> >> On 10.09.19 16:52, Kevin Wolf wrote:
> >>> Am 09.08.2019 um 18:13 hat Max Reitz geschrieben:
> If the driver does not implement bdrv_get_allocated
From: Atish Patra
Use both the generic register name and ABI name for the general purpose
registers and floating point registers.
Signed-off-by: Atish Patra
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 19 +++
1
Reverting the commit solved my problem, although I don't know why it needed to
be fixed to 64-bit back then. Finally I can now single step a cross-compiled
MIPS program on a QEMU Linux user binary and observe the register and memory
contents.
-- Original --
Fr
Am 11.09.2019 um 10:01 hat Thomas Huth geschrieben:
> On 11/09/2019 08.58, Kevin Wolf wrote:
> > Am 10.09.2019 um 21:07 hat Eric Blake geschrieben:
> >> On 9/10/19 1:58 PM, Thomas Huth wrote:
> >>> Our "tests" directory is very overcrowded - we store the qtests,
> >>> unit test and other files ther
On Wed, 11 Sep 2019 at 02:43, Richard Henderson
wrote:
>
> This forced inlining can result in missing symbols,
> which makes a debugging build harder to follow.
>
> Reported-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/cputlb.c | 16 ++--
> 1 file changed,
On Wed, 2019-09-11 at 09:35 +0200, Stefan Hajnoczi wrote:
> On Tue, Sep 10, 2019 at 05:14:36PM +0200, Johannes Berg wrote:
> > On Tue, 2019-09-10 at 17:03 +0200, Stefan Hajnoczi wrote:
> > > > Now, this means that the CPU (that's part of the simulation) has to
> > > > *wait* for the device to add a
On Wed, 11 Sep 2019 14:04:50 +1000
David Gibson wrote:
> From: Alexey Kardashevskiy
>
> We are going to use spapr_build_fdt() for the boot time FDT and as an
> update for SLOF during handling of H_CAS. SLOF will apply all properties
> from the QEMU's FDT which is usually ok unless there are pro
* Yury Kotov (yury-ko...@yandex-team.ru) wrote:
> This capability realizes simple source validation by UUID.
> It's useful for live migration between hosts.
>
> Signed-off-by: Yury Kotov
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/migration.c | 9 +
> migration/migration.h
On Tue, Sep 10, 2019 at 05:52:36PM +0200, Johannes Berg wrote:
> On Mon, 2019-09-09 at 15:50 +0200, Johannes Berg wrote:
>
> > > We can document how to behave in case of inconsistent protocol features,
> > > yes.
> >
> > OK.
>
> Coming back to this, I was just looking at it.
>
> How/where would
On Thu, Aug 01, 2019 at 08:40:53AM +0800, Wei Yang wrote:
>Persistent backend setup requires some knowledge about nvdimm and ndctl
>tool. Some users report they may struggle to gather these knowledge and
>have difficulty to setup it properly.
>
>Here we provide two examples for persistent backend a
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