On 7/18/2019 2:16 PM, Xiaoyao Li wrote:
On 7/18/2019 9:56 AM, Tao Xu wrote:
On 7/18/2019 2:38 AM, Eduardo Habkost wrote:
On Wed, Jul 17, 2019 at 01:39:01PM +0800, Tao Xu wrote:
Hi Eduardo,
Could I ask a question about introducing a old CPU model? Maybe not
so old
because it was launched in 2
On Wed, Jul 17, 2019 at 07:00:25AM -0400, Michael S. Tsirkin wrote:
> On Wed, Jun 12, 2019 at 10:11:57AM +0800, Tiwei Bie wrote:
> > On Tue, Jun 11, 2019 at 10:10:14AM -0400, Michael S. Tsirkin wrote:
> > > On Tue, Jun 11, 2019 at 02:51:37PM +0800, Tiwei Bie wrote:
> > > > The VIRTIO_NET_F_CTRL_VLA
On 18/07/2019 08.25, Philippe Mathieu-Daudé wrote:
> When building from the GitHub generated archive
> (https://github.com/qemu/qemu/archive/v4.1.0-rc0.tar.gz)
> we get:
>
> ---
> $ ./configure
>
> ERROR: missing file /tmp/qemu-4.1.0-rc0/ui/keycodemapdb/README
>
> This is not a GIT checkout but
On 16/07/2019 07.35, Alexey Kardashevskiy wrote:
> SLOF implements one itself so let's remove it from QEMU. It is one less
> image and simpler setup as the RTAS blob never stays in its initial place
> anyway as the guest OS always decides where to put it.
>
> This totally depends on https://patchw
Paolo, ping? :)
On 14/06/2019 11:52, Alexey Kardashevskiy wrote:
This adds an accelerator name to the "into mtree -f" to tell the user if
a particular memory section is registered with the accelerator;
the primary user for this is KVM and such information is useful
for debugging purposes.
This
Denverton is the Atom Processor of Intel Harrisonville platform.
For more information:
https://ark.intel.com/content/www/us/en/ark/products/\
codename/63508/denverton.html
Signed-off-by: Tao Xu
---
Changes in v3:
- Add MSR features in FEAT_ARCH_CAPABILITIES (Xiaoyao)
---
target/i386/cpu.c
On 16/07/2019 18.12, Max Reitz wrote:
> On 16.07.19 18:09, Eric Blake wrote:
>> On 7/16/19 10:58 AM, Max Reitz wrote:
[...]
Is there any way to create our sockets somewhere under /tmp instead of
inside tests/qemu-iotests, so that we have a shorter filename for
sockets no matter how d
> -Original Message-
> From: Dmitry Fomichev
> Sent: 17 July 2019 22:27
> To: qemu-devel@nongnu.org; qemu-bl...@nongnu.org
> Cc: John Snow ; Kevin Wolf ; Max Reitz
> ; Keith
> Busch ; Stefan Hajnoczi ; Michael
> S. Tsirkin
> ; Stefano Stabellini ; Anthony Perard
> ; Paul Durrant ; Paolo
On 18/07/2019 17:20, Thomas Huth wrote:
On 16/07/2019 07.35, Alexey Kardashevskiy wrote:
SLOF implements one itself so let's remove it from QEMU. It is one less
image and simpler setup as the RTAS blob never stays in its initial place
anyway as the guest OS always decides where to put it.
Th
On 18/07/19 06:55, Jing Liu wrote:
>>
>> + *eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7,
>> + count, R_EAX);
> This needs to be firstly checked as follows, otherwise some
> architectures would fail to compile.
>
> What about hvf a
On 18/07/19 03:25, Wei Yang wrote:
> RAMBlock->used_length is always passed to migration_bitmap_sync_range(),
> which could be retrieved from RAMBlock.
>
> Suggested-by: Paolo Bonzini
> Signed-off-by: Wei Yang
> ---
> migration/ram.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions
There is only one place to set start_postcopy to true,
qmp_migrate_start_postcopy(), which make sure start_postcopy could be
set to true when migrate_postcopy() return true.
So start_postcopy is true implies the other one.
Signed-off-by: Wei Yang
---
migration/migration.c | 3 +--
1 file change
On 18/07/19 09:21, Alexey Kardashevskiy wrote:
> Paolo, ping? :)
Queued, thanks. I'll sneak it into 4.1, I have a couple other patches
to send.
Paolo
>
> On 14/06/2019 11:52, Alexey Kardashevskiy wrote:
>> This adds an accelerator name to the "into mtree -f" to tell the user if
>> a particular
On 7/18/19 8:01 AM, tony.ngu...@bt.com wrote:
> This patch moves the define of target access alignment earlier from
> target/foo/cpu.h to configure.
>
> Suggested in Richard Henderson's reply to "[PATCH 1/4] tcg: TCGMemOp is now
> accelerator independent MemOp"
>
> Signed-off-by: Tony Nguyen
> -
On Thu, Jul 18, 2019 at 10:17:19AM +0200, Paolo Bonzini wrote:
>On 18/07/19 03:25, Wei Yang wrote:
>> RAMBlock->used_length is always passed to migration_bitmap_sync_range(),
>> which could be retrieved from RAMBlock.
>>
>> Suggested-by: Paolo Bonzini
>> Signed-off-by: Wei Yang
>> ---
>> migrat
Rename for better understanding of the code.
Suggested-by: Paolo Bonzini
Signed-off-by: Wei Yang
---
migration/ram.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index c5f9f4b0ef..66792568e2 100644
--- a/migration/ram.c
+++ b/migrat
On 7/18/19 9:10 AM, Thomas Huth wrote:
> On 18/07/2019 08.25, Philippe Mathieu-Daudé wrote:
>> When building from the GitHub generated archive
>> (https://github.com/qemu/qemu/archive/v4.1.0-rc0.tar.gz)
>> we get:
>>
>> ---
>> $ ./configure
>>
>> ERROR: missing file /tmp/qemu-4.1.0-rc0/ui/keycodema
Throttling thread sleeps in VCPU thread. For high throttle percentage
this sleep is more than 10ms. E.g. for 60% - 15ms, for 99% - 990ms.
vm_stop() kicks all VCPUs and waits for them. It's called at the end of
migration and because of the long sleep the migration downtime might be
more than 100ms e
Hi,
V3:
* Rebase fixes (migrate_set_parameter -> migrate_set_parameter_int)
V2:
* Added a test
* Fixed qemu_cond_timedwait for qsp
I wrote a test for migration auto converge and found out a strange thing:
1. Enable auto converge
2. Set max-bandwidth 1Gb/s
3. Set downtime-limit 1ms
4. Run standar
The 'piix3-ide' (and 'piix3-ide-xen') devices are part of the
PIIX3 chipset modelled as TYPE_PIIX3_PCI_DEVICE (respectivelly
TYPE_PIIX3_XEN_DEVICE). The PIIX3 chipset can not be created
in part, it has to be created and used as a whole.
Similarly with the 'piix4-ide' device and the PIIX4 chipset
m
Signed-off-by: Yury Kotov
---
include/qemu/thread.h| 18 ++
util/qemu-thread-posix.c | 40
util/qemu-thread-win32.c | 16
util/qsp.c | 18 ++
4 files changed, 80 insertions(+), 12 deletions
Signed-off-by: Yury Kotov
---
tests/migration-test.c | 119 +
1 file changed, 108 insertions(+), 11 deletions(-)
diff --git a/tests/migration-test.c b/tests/migration-test.c
index a4feb9545d..bb69517fc8 100644
--- a/tests/migration-test.c
+++ b/tests/migra
On 18/07/19 11:17, Philippe Mathieu-Daudé wrote:
> The 'piix3-ide' (and 'piix3-ide-xen') devices are part of the
> PIIX3 chipset modelled as TYPE_PIIX3_PCI_DEVICE (respectivelly
> TYPE_PIIX3_XEN_DEVICE). The PIIX3 chipset can not be created
> in part, it has to be created and used as a whole.
>
>
From: Zhang Chen
This patch to fix the origin "char *data" menory leak, code style issue
and add necessary check here.
Reported-by: Coverity (CID 1402785)
Signed-off-by: Zhang Chen
---
net/colo-compare.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff
On Wed, 17 Jul 2019 08:52:54 -0400
Collin Walling wrote:
> On 7/17/19 5:27 AM, Christian Borntraeger wrote:
> >
> >
> > On 17.07.19 10:54, Cornelia Huck wrote:
> >> On Tue, 16 Jul 2019 14:34:22 -0400
> >> Collin Walling wrote:
> >>
> >>> On 7/16/19 11:20 AM, Cornelia Huck wrote:
> O
On 17/07/19 23:27, Dmitry Fomichev wrote:
> diff --git a/hw/scsi/scsi-generic.c b/hw/scsi/scsi-generic.c
> index a43efe39ec..e38d3160fa 100644
> --- a/hw/scsi/scsi-generic.c
> +++ b/hw/scsi/scsi-generic.c
> @@ -238,6 +238,7 @@ static void scsi_read_complete(void * opaque, int ret)
> SCSIGeneri
On 18/07/19 03:45, Peter Xu wrote:
> On Thu, Jul 18, 2019 at 09:04:54AM +0800, Wei Yang wrote:
>> Patch 1 refine bitmap_set a little.
>> Patch 2 add related test case to bitmap_set.
>>
>> v3:
>> * free bmap
>> * all 1's set correctly
>> * expand range to 2 long
>> * check each possible of o
On 18/07/19 08:01, tony.ngu...@bt.com wrote:
> This patch moves the define of target access alignment earlier from
> target/foo/cpu.h to configure.
>
> Suggested in Richard Henderson's reply to "[PATCH 1/4] tcg: TCGMemOp is now
> accelerator independent MemOp"
>
> Signed-off-by: Tony Nguyen
> --
On Thu, 18 Jul 2019 13:42:11 +1000
Nicholas Piggin wrote:
> Implement cpu_exec_enter/exit on ppc which calls into new methods of
> the same name in PPCVirtualHypervisorClass. These are used by spapr
> to implement the splpar VPA dispatch counter initially.
>
> Signed-off-by: Nicholas Piggin
> -
On Wed, 17 Jul 2019 at 15:55, Laurent Vivier wrote:
>
> The following changes since commit a1a4d49f60d2b899620ee2be4ebb991c4a90a026:
>
> Merge remote-tracking branch
> 'remotes/philmd-gitlab/tags/pflash-next-20190716' into staging (2019-07-16
> 17:02:44 +0100)
>
> are available in the Git repo
Patchew URL: https://patchew.org/QEMU/20190717173937.18747-1-js...@redhat.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
make do
On 7/18/19 11:22 AM, Zhang Chen wrote:
> From: Zhang Chen
>
> This patch to fix the origin "char *data" menory leak, code style issue
"memory"
> and add necessary check here.
> Reported-by: Coverity (CID 1402785)
>
> Signed-off-by: Zhang Chen
> ---
> net/colo-compare.c | 28 +
On Thu, 18 Jul 2019 at 11:28, Philippe Mathieu-Daudé wrote:
>
> On 7/18/19 11:22 AM, Zhang Chen wrote:
> > From: Zhang Chen
> >
> > This patch to fix the origin "char *data" menory leak, code style issue
>
> "memory"
>
> > and add necessary check here.
> > Reported-by: Coverity (CID 1402785)
> >
Commit 1405819637f53 ("qmp: don't emit the RESET event on wakeup from
S3") changed system wakeup to avoid calling qapi_event_send_reset.
Commit 76ed4b18debfe ("s390/ipl: fix ipl with -no-reboot") appears to
have inadvertently broken that logic.
Signed-off-by: Nicholas Piggin
---
I'm not quite sur
Any comments on this series would be welcome. Hopefully someone who
knows i386 can give some feedback on the possible bug fix, and
whether the new wakeup method will suit i386.
Thanks,
Nick
Nicholas Piggin (3):
qmp: don't emit the RESET event on wakeup
machine: Add wakeup method to MachineCla
Waking from suspend is not logically a machine reset on all machines,
particularly in the paravirtualized case rather than hardware
emulated. The ppc spapr machine for example just invokes hypervisor
to suspend, and expects that call to return with the machine in the
same state (modulo some possibl
On Thu, 18 Jul 2019 17:55:12 +1000
Alexey Kardashevskiy wrote:
>
>
> On 18/07/2019 17:20, Thomas Huth wrote:
> > On 16/07/2019 07.35, Alexey Kardashevskiy wrote:
> >> SLOF implements one itself so let's remove it from QEMU. It is one less
> >> image and simpler setup as the RTAS blob never stay
This has been useful to modify and test the Linux pseries suspend
code but it requires modification to the guest to call it (due to
being gated by other unimplemented features). It is not otherwise
used by Linux yet, but work is slowly progressing there.
This allows a (lightly modified) guest kern
Le 18/07/2019 à 12:20, Peter Maydell a écrit :
> On Wed, 17 Jul 2019 at 15:55, Laurent Vivier wrote:
>>
>> The following changes since commit a1a4d49f60d2b899620ee2be4ebb991c4a90a026:
>>
>> Merge remote-tracking branch
>> 'remotes/philmd-gitlab/tags/pflash-next-20190716' into staging (2019-07-1
On Thu, 18 Jul 2019 13:42:12 +1000
Nicholas Piggin wrote:
> H_PROD is added, and H_CEDE is modified to test the prod bit
> according to PAPR.
>
> Signed-off-by: Nicholas Piggin
> ---
Reviewed-by: Greg Kurz
> Changes since v5:
> - Add the prod bit here
> - Fix target CPU
>
> hw/ppc/spapr.c
On Thu, 18 Jul 2019 13:42:13 +1000
Nicholas Piggin wrote:
> This does not do directed yielding and is not quite as strict as PAPR
> specifies in terms of precise dispatch behaviour. This generally will
> mean suboptimal performance, rather than guest misbehaviour. Linux
> does not rely on exact d
On Thu, 18 Jul 2019 13:42:14 +1000
Nicholas Piggin wrote:
> This has been useful to modify and test the Linux pseries suspend
> code but it requires modification to the guest to call it (due to
> being gated by other unimplemented features). It is not otherwise
> used by Linux yet, but work is sl
To avoid incoherent states when the machine resets (see but report
below), add the device reset callback.
A "system reset" sets the device state machine in READ_ARRAY mode
and, after some delay, set the SR.7 READY bit.
Since we do not model timings, we set the SR.7 bit directly.
Fixes: https://b
The pflash device lacks a reset() function.
When a machine is resetted, the flash might be in an
inconsistent state, leading to unexpected behavior.
Resolve this issue by adding a DeviceReset() handler.
v7: Surgical bugfix, do not attempt to improve the model in any
way, thus ignoring all comm
On 18/07/2019 12.40, Greg Kurz wrote:
> On Thu, 18 Jul 2019 17:55:12 +1000
> Alexey Kardashevskiy wrote:
>
>>
>>
>> On 18/07/2019 17:20, Thomas Huth wrote:
>>> On 16/07/2019 07.35, Alexey Kardashevskiy wrote:
SLOF implements one itself so let's remove it from QEMU. It is one less
image
Hi Igor,
> -Original Message-
> From: Qemu-devel
> [mailto:qemu-devel-bounces+shameerali.kolothum.thodi=huawei.com@nongn
> u.org] On Behalf Of Igor Mammedov
> Sent: 17 July 2019 15:33
> To: Shameerali Kolothum Thodi
> Cc: peter.mayd...@linaro.org; sa...@linux.intel.com;
> shannon.zha...@g
On 7/18/19 12:37 PM, Peter Maydell wrote:
> On Thu, 18 Jul 2019 at 11:28, Philippe Mathieu-Daudé
> wrote:
>>
>> On 7/18/19 11:22 AM, Zhang Chen wrote:
>>> From: Zhang Chen
>>>
>>> This patch to fix the origin "char *data" menory leak, code style issue
>>
>> "memory"
>>
>>> and add necessary chec
On Thu, 18 Jul 2019 at 11:40, Laurent Vivier wrote:
> It comes from linux-user/syscall.c:
>
> 6328 /* automatic consistency check if same arch */
> 6329 #if (defined(__i386__) && defined(TARGET_I386) &&
> defined(TARGET_ABI32)) || \
> 6330 (defined(__x86_64__) && defined(TARGET_X86
On 18/07/19 12:39, Nicholas Piggin wrote:
> Commit 1405819637f53 ("qmp: don't emit the RESET event on wakeup from
> S3") changed system wakeup to avoid calling qapi_event_send_reset.
> Commit 76ed4b18debfe ("s390/ipl: fix ipl with -no-reboot") appears to
> have inadvertently broken that logic.
>
>
On 18/07/19 12:39, Nicholas Piggin wrote:
> Any comments on this series would be welcome. Hopefully someone who
> knows i386 can give some feedback on the possible bug fix, and
> whether the new wakeup method will suit i386.
Looks good, though only i386 supports wakeup so perhaps it's better to
DT
Le 18/07/2019 à 13:00, Peter Maydell a écrit :
> On Thu, 18 Jul 2019 at 11:40, Laurent Vivier wrote:
>> It comes from linux-user/syscall.c:
>>
>> 6328 /* automatic consistency check if same arch */
>> 6329 #if (defined(__i386__) && defined(TARGET_I386) &&
>> defined(TARGET_ABI32)) || \
On Thu, 18 Jul 2019 at 12:10, Laurent Vivier wrote:
> Do you think we should defer the whole patch after 4.1 release?
> But then the build of 4.1 will be broken with 5.2+ kernel
I think this is worth putting into 4.1; but we should
look at maybe tidying up the loose ends for 4.2.
thanks
-- PMM
On 18.07.19 13:06, Paolo Bonzini wrote:
> On 18/07/19 12:39, Nicholas Piggin wrote:
>> Commit 1405819637f53 ("qmp: don't emit the RESET event on wakeup from
>> S3") changed system wakeup to avoid calling qapi_event_send_reset.
>> Commit 76ed4b18debfe ("s390/ipl: fix ipl with -no-reboot") appears
On 18/07/2019 12.55, Aleksandar Markovic wrote:
> On Thu, Jul 18, 2019 at 10:58 AM Philippe Mathieu-Daudé
> wrote:
>>
>> On 7/18/19 9:10 AM, Thomas Huth wrote:
>>> On 18/07/2019 08.25, Philippe Mathieu-Daudé wrote:
>
...
>
Now there are no archive to download at this url...
>>>
>>> You
Patchew URL:
https://patchew.org/QEMU/20190718010456.4234-1-richardw.y...@linux.intel.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin
On Thu, Jul 18, 2019 at 01:29:02PM +0200, Thomas Huth wrote:
> On 18/07/2019 12.55, Aleksandar Markovic wrote:
> > On Thu, Jul 18, 2019 at 10:58 AM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 7/18/19 9:10 AM, Thomas Huth wrote:
> >>> On 18/07/2019 08.25, Philippe Mathieu-Daudé wrote:
> >
> >>>
Am 18.07.2019 um 13:29 schrieb Thomas Huth:
> I guess we should simply re-arrange the order of the tabs ... the
> OS-agnostic source code tab should come first (since this is about what
> we provide for download on our site), and then the others with
> references to the distros etc.
>
> Does someon
On 18.07.19 05:50, David Gibson wrote:
> On Wed, Jul 17, 2019 at 12:35:48PM +0200, David Hildenbrand wrote:
>> We are using the wrong functions to set/clear bits, effectively touching
>> multiple bits, writing out of range of the bitmap, resulting in memory
>> corruptions. We have to use set_bit()/
On 18/07/2019 13.43, Daniel P. Berrangé wrote:
> On Thu, Jul 18, 2019 at 01:29:02PM +0200, Thomas Huth wrote:
>> On 18/07/2019 12.55, Aleksandar Markovic wrote:
>>> On Thu, Jul 18, 2019 at 10:58 AM Philippe Mathieu-Daudé
>>> wrote:
On 7/18/19 9:10 AM, Thomas Huth wrote:
> On 18/07/20
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 55c53c741776..085e468ea69a 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -149,13 +149,11 @@
When a vCPU is not dispatched anymore on a HW thread, the Hypervisor
(KVM on Linux) invalidates the OS interrupt context of a vCPU with
this special command. It returns the OS CAM line value and resets the
VO bit.
Signed-off-by: Cédric Le Goater
---
hw/intc/xive.c | 15 ++-
1 file ch
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv_xscom.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 2b81c75f5654..3efa9c8fa13f 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -107,6 +107,16 @@ static uint64_t x
If backlog is activated ('b' bit) on the END, the pending priority of
a missed event is recorded in the IPB field of the NVT for a later
resend.
Signed-off-by: Cédric Le Goater
---
hw/intc/xive.c | 77 +++---
1 file changed, 48 insertions(+), 29 deleti
Hello,
The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
acts as an hypervisor (L0). Supporting emulation of KVM to run guests
(L1) requires a few more extensions, among which guest support for the
XIVE interrupt controller on POWER9 processor.
The following changes include some
When an interrupt can not be presented to a vCPU, the XIVE presenter
updates the Interrupt Pending Buffer of the XIVE NVT if backlog is
activated in the END.
Later, when the same vCPU is dispatched, its context is pushed in the
thread context registers and the VO bit is set in the CAM line word to
Provide a better output of the XIVE END structures including the
escalation information and extend the PowerNV machine 'info pic'
command with a dump of the END EAS table used for escalations.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 5
include/hw/ppc/xive_regs.h |
When the 'u' bit is set the escalation is said to be 'unconditional'
which means that the ESe PQ bits are not used. Introduce a
xive_router_end_es_notify() routine to share code with the ESn
notification.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive_regs.h | 2 ++
hw/intc/xive.c
pnv_xive_vst_size() tries to compute the size of a VSD table from the
information given by FW. The number of entries of the table are
deduced from the result and the MMIO regions of the ESBs and the ENDS
are also resized with the computed value.
But for indirect tables, the result is incorrect. An
When the 's' bit is set the escalation is said to be 'silent' or
'silent/gather'. In such configuration, the notification sequence is
skipped and only the escalation sequence is performed. This is used to
configure all the EQs of a vCPU to escalate on a single EQ which will
then target the hypervis
This is to perform lookups in the NVT table when a vCPU is dispatched
and possibily resend interrupts.
Future XIVE chip will use a different class for the model of the
interrupt controller and we might need to change the type of
'XiveRouter *' to 'Object *'
Signed-off-by: Cédric Le Goater
---
i
This prevents the compiler from reporting a possible uninitialized use
of maybe_keycode in function curses_refresh.
Cc: Gerd Hoffmann
Signed-off-by: Paolo Bonzini
---
ui/curses.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/ui/curses.c b/ui/curses.c
index a6e260e..a3ec9b5 100644
--- a/
Our module system does not support Windows, because it relies on
resolving symbols from the main executable.
If there is enough interest in supporting modules on Windows, we could
generate an import library for the executable and link with it:
https://stackoverflow.com/questions/15454968/dll-plugi
It removes a useless call to pnv_xive_get_ic() which is making some
assumption on the chip_id format.
Signed-off-by: Cédric Le Goater
---
hw/intc/pnv_xive.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index a48f6750154e.
We try to loop on the full table skipping empty indirect pages which
are not necessarily allocated. This is useful to dump the contexts of
the KVM vCPUs.
Signed-off-by: Cédric Le Goater
---
hw/intc/pnv_xive.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/h
When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field
overrides the hardwired chip ID in the Powerbus operations and for CAM
compares. This is typically used in one block-per-chip configurations
to associate a unique block id number to each IC of the system.
The model does support
Am 18.07.2019 um 11:26 hat Paolo Bonzini geschrieben:
> On 18/07/19 11:17, Philippe Mathieu-Daudé wrote:
> > The 'piix3-ide' (and 'piix3-ide-xen') devices are part of the
> > PIIX3 chipset modelled as TYPE_PIIX3_PCI_DEVICE (respectivelly
> > TYPE_PIIX3_XEN_DEVICE). The PIIX3 chipset can not be crea
Patchew URL:
https://patchew.org/QEMU/1563451264-46176-1-git-send-email-pbonz...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH] curses: assert get_wch return value is okay
Message-id: 1563
We will use it to resend missed interrupts when a vCPU context is
pushed a HW thread.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 1 +
hw/intc/xive.c| 15 +++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/p
If the XIVE presenter can not find the NVT dispatched on any of the HW
threads, it can not deliver the interrupt. XIVE offers an escalation
mechanism to handle such scenarios and inform the hypervisor that an
action should be taken.
Escalation is configured by setting the 'e' bit and the EAS in wo
On Thu, Jul 18, 2019 at 1:43 PM Daniel P. Berrangé
wrote:
> On Thu, Jul 18, 2019 at 01:29:02PM +0200, Thomas Huth wrote:
> > On 18/07/2019 12.55, Aleksandar Markovic wrote:
> > > On Thu, Jul 18, 2019 at 10:58 AM Philippe Mathieu-Daudé <
> phi...@redhat.com>
> > > wrote:
> > >>
> > >> On 7/18/19 9
This is to track the configuration of the base END index of the vCPU
and the Interrupt Pending Buffer. The NVT IPB is updated when an
interrupt can not be presented to a vCPU.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive_regs.h | 2 ++
hw/intc/pnv_xive.c | 22
When dumping the END and NVT tables, the error logging is too noisy.
Signed-off-by: Cédric Le Goater
---
hw/intc/pnv_xive.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index c1501a6b5bce..e7acab0dff51 100644
--- a/hw/intc/pnv_x
On Wed, 17 Jul 2019 at 16:08, Laszlo Ersek wrote:
>
> On 07/17/19 15:46, Peter Maydell wrote:
> > On Wed, 17 Jul 2019 at 14:36, Philippe Mathieu-Daudé
> > wrote:
> >> I still wonder why this didn't assert on Peter's setup.
> >
> > My setup does not assert because my host kernel correctly
> > pro
On Thu, 18 Jul 2019 10:52:10 +
Shameerali Kolothum Thodi wrote:
> Hi Igor,
>
> > -Original Message-
> > From: Qemu-devel
> > [mailto:qemu-devel-bounces+shameerali.kolothum.thodi=huawei.com@nongn
> > u.org] On Behalf Of Igor Mammedov
> > Sent: 17 July 2019 15:33
> > To: Shameerali Kol
On Tue, 16 Jul 2019 16:38:12 +0100
Shameer Kolothum wrote:
> This initializes the GED device with base memory and irq, configures
> ged memory hotplug event and builds the corresponding aml code. With
> this, both hot and cold plug of device memory is enabled now for Guest
> with ACPI boot.
>
>
Allow bit 15 to be 1 in the slbmfee and slbmfev in TCG
as per Power ISA 3.0B (Power 9) Book III pages 1029 and 1030.
Per this specification, bit 15 is implementation specific
so it may be 1, but can probably ne safely ignored.
Power ISA 2.07B (Power 7/Power 8) indicates the bit is
reserved but so
On Thu, Jul 18, 2019 at 04:04:13PM +0400, Marc-André Lureau wrote:
> Our module system does not support Windows, because it relies on
> resolving symbols from the main executable.
>
> If there is enough interest in supporting modules on Windows, we could
> generate an import library for the execut
On 18/07/19 14:04, Marc-André Lureau wrote:
> Our module system does not support Windows, because it relies on
> resolving symbols from the main executable.
>
> If there is enough interest in supporting modules on Windows, we could
> generate an import library for the executable and link with it:
In arm_cpu_realizefn() we make several assertions about the values of
guest ID registers:
* if the CPU provides AArch32 v7VE or better it must advertise the
ARM_DIV feature
* if the CPU provides AArch32 A-profile v6 or better it must
advertise the Jazelle feature
These are essentially cons
On Tue, 16 Jul 2019 16:38:15 +0100
Shameer Kolothum wrote:
> Use GED for system_powerdown event instead of GPIO for ACPI.
> Guest boot with DT still uses GPIO.
I'd hate to keep ACPI GPIO around but taking in account migration
wouldn't this patch break ACPI GPIO based button on 4.0 and older wh
On 18/07/2019 08:16, David Gibson wrote:
> On Thu, Jul 18, 2019 at 03:12:17PM +0930, Joel Stanley wrote:
>> Currently we fail to boot a qemu powernv machine with a Power9
>> processor:
>>
>> PLAT: Detected generic platform
>> PLAT: Detected BMC platform generic
>> CPU: All 1 processors called in
On Tue, 16 Jul 2019 16:38:14 +0100
Shameer Kolothum wrote:
> This adds support to use GED for system power down event.
[...]
> @@ -232,6 +238,13 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev,
> AcpiEventStatusBits ev)
> acpi_ged_event(s, sel);
> }
>
> +static void acpi_ged_pm_po
From: Daniel P. Berrangé
The SIOCGSTAMP symbol was previously defined in the
asm-generic/sockios.h header file. QEMU sees that header
indirectly via sys/socket.h
In linux kernel commit 0768e17073dc527ccd18ed5f96ce85f9985e9115
the asm-generic/sockios.h header no longer defines SIOCGSTAMP.
Instead
This happens because:
* the host kernel is older than 4.15 and does not expose ID registers to
userspace via the KVM_GET_ONE_REG ioctl
* our fallback set of ID register values in target/arm/kvm64.c
kvm_arm_get_host_cpu_features() is extremely minimalist
* the consistency checks on ID register
On Tue, 16 Jul 2019 16:38:16 +0100
Shameer Kolothum wrote:
> From: Eric Auger
>
> PCDIMM hotplug addition updated the DSDT. Update the reference table.
it's not correct process. series should be merged through Michael's pci branch
and see
commit ab50f22309a17c772c51931940596e707c200739 (mst/pc
On 18/07/19 14:49, Daniel P. Berrangé wrote:
> On Thu, Jul 18, 2019 at 04:04:13PM +0400, Marc-André Lureau wrote:
>> Our module system does not support Windows, because it relies on
>> resolving symbols from the main executable.
>>
>> If there is enough interest in supporting modules on Windows, we
On Thu, 18 Jul 2019 at 12:50, Stefan Weil wrote:
>
> Am 18.07.2019 um 13:29 schrieb Thomas Huth:
> > I guess we should simply re-arrange the order of the tabs ... the
> > OS-agnostic source code tab should come first (since this is about what
> > we provide for download on our site), and then the
If configure detects that it's being run on a source tree which
is missing git modules, it prints an error messages suggesting
that the user downloads a correct source archive from the project
website. However https://www.qemu.org/download/ is a link to a
page with multiple tabs, with the default b
On 18/07/2019 15.16, Peter Maydell wrote:
> If configure detects that it's being run on a source tree which
> is missing git modules, it prints an error messages suggesting
> that the user downloads a correct source archive from the project
> website. However https://www.qemu.org/download/ is a lin
On Thu, 18 Jul 2019 at 10:27, Zhang Chen wrote:
>
> From: Zhang Chen
>
> This patch to fix the origin "char *data" menory leak, code style issue
> and add necessary check here.
> Reported-by: Coverity (CID 1402785)
>
> Signed-off-by: Zhang Chen
> ---
> net/colo-compare.c | 28 ++
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