On 6/28/19 5:50 PM, Lucien Murray-Pitts wrote:
> op_helper.c
>static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
>...
> if (cs->exception_index == EXCP_ACCESS) {
> ...
> do_stack_frame(env, &sp, 7, oldsr, 0, retaddr /*LMP: BROKEN - needs PC
> NEXT*/);
>
> Actua
On Freitag, 28. Juni 2019 16:23:08 CEST Greg Kurz wrote:
> > > This feature applies to all backends IIUC. We don't really care for the
> > > synth backend since it generates non-colliding inode numbers by design,
> > > but the proxy backend has the same issue as local. So...
> >
> > Yeah, I was no
On 6/28/19 10:02 PM, Eduardo Habkost wrote:
> Replace the static variable with a PCMachineClass field. This
> will help us eventually get rid of the pc_compat_*() init
> functions.
>
> Signed-off-by: Eduardo Habkost
> ---
> include/hw/i386/pc.h | 3 +++
> hw/i386/pc.c | 22 +---
Hi Marlies,
On 6/29/19 1:26 AM, Marlies Ruck wrote:
> Hi,
>
> I just wanted to follow up since I sent this patch a week ago to make sure
> it was a received. An ack would be appreciated.
You did not Cc'ed the maintainer, so he likely missed it.
See:
https://wiki.qemu.org/Contribute/SubmitAPatch
On Freitag, 28. Juni 2019 16:56:15 CEST Christian Schoenebeck via Qemu-devel
> > > + */
> > > +#define EXP_GOLOMB_K0
> > > +
> > > +# if !EXP_GOLOMB_K
> > > +
> > > +/** @brief Exponential Golomb algorithm limited to the case k=0.
> > > + *
> >
> > This doesn't really help to have a special i
Hi Thomas,
On 6/28/19 8:15 PM, Thomas Huth wrote:
> The NeXTcube uses a linear framebuffer with 4 greyscale colors and
> a fixed resolution of 1120 * 832.
> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>
> https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c
On 6/28/19 8:15 PM, Thomas Huth wrote:
> It is likely still quite incomplete (e.g. mouse and interrupts are not
> implemented yet), but it is good enough for keyboard input at the firmware
> monitor.
> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>
> https://github.com/bl
On 6/28/19 7:06 PM, Jan Bobek wrote:
> That's true. (Although not in all cases; see Table 2-5 in the Intel Manual,
> Volume 2, Chapter 2, Section 2.2.1 "REX Prefixes" for some cases when REX.B
> is not decoded.) This is a compromise that I've accepted, at least for v1
> of the patch series. Note th
On 6/28/19 8:15 PM, Thomas Huth wrote:
> It is still quite incomplete (no SCSI, no floppy emulation, no network,
> etc.), but the firmware already shows up the debug monitor prompt in the
> framebuffer display, so at least the very basics are already working.
>
> This code has been taken from Bryc
On 6/28/19 8:15 PM, Thomas Huth wrote:
> I don't have much clue about the NeXT hardware, but at least I know now
> the source files a little bit, so I volunteer to pick up patches and send
> PULL requests for them until someone else with more knowledge steps up
> to do this job instead.
>
> Signed
On 6/29/19 2:26 PM, Philippe Mathieu-Daudé wrote:
> On 6/28/19 8:15 PM, Thomas Huth wrote:
>> It is still quite incomplete (no SCSI, no floppy emulation, no network,
>> etc.), but the firmware already shows up the debug monitor prompt in the
>> framebuffer display, so at least the very basics are a
On Fri, 28 Jun 2019 at 16:56, Dr. David Alan Gilbert
wrote:
>
> * Yuval Shaia (yuval.sh...@oracle.com) wrote:
> > On Fri, Jun 21, 2019 at 08:15:41PM +0530, Sukrit Bhatnagar wrote:
> > > Define and register SaveVMHandlers pvrdma_save and
> > > pvrdma_load for saving and loading the device state,
>
This is only used for 32-bit hosts.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index cb604b76a3..9a44670180 100644
--- a/tcg/ppc
Changes since v5:
* Disable runtime altivec detection until all of the required
opcodes are implemented.
Because dup2 was last, that really means all of the pure altivec
bits, so the initial patches are not bisectable in any meaningful
sense. I thought about reshuffling dup2 earl
Now that we have implemented the required tcg operations,
we can enable detection of host vector support.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 9a
Introduce macros VRT(), VRA(), VRB(), VRC() used for encoding
elements of Altivec instructions.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.opc.h | 8 +++
tcg/ppc/tcg-target.inc.c | 112 ++-
3 files changed, 120 insertions(+), 2
Introduce macro VX4() used for encoding Altivec instructions.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 8e1bba7824..9e560db993 100
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58 ++--
2 files changed, 57
Altivec supports 32 128-bit vector registers, whose names are
by convention v0 through v31.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 11 -
tcg/ppc/tcg-target.inc.c | 88 +---
2 files changed, 65 in
Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg
Add support for vector add/subtract using Altivec instructions:
VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 20
1 file changed, 20 insertions(+)
diff --git a/tcg/pp
This line is just preparation for full vector multiply support
in some of subsequent patches.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
Introduce all of the flags required to enable tcg backend vector support,
and a runtime flag to indicate the host supports Altivec instructions.
For now, do not actually set have_isa_altivec to true, because we have not
yet added all of the code to actually generate all of the required insns.
Howe
This includes single-word loads and stores, lots of double-word
arithmetic, and a few extra logical operations.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 128 ++-
2 fi
This includes double-word loads and stores, double-word load and splat,
double-word permute, and bit select. All of which require multiple
operations in the base Altivec instruction set.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 5 ++--
Add support for vector maximum/minimum using Altivec instructions
VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and
VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.
Add various bits and peaces related mostly to load and store
operations. In that context, logic, compare, and splat Altivec
instructions are used, and, therefore, the support for emitting
them is included in this patch too.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
This includes vector load/store with immediate offset, some extra
move and splat insns, compare ne, and negate.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 103 ++-
2 fi
Patchew URL:
https://patchew.org/QEMU/20190629130017.2973-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v6 00/16] tcg/ppc: Add vector opcodes
Message-id: 20190629130017.2973-1-richa
This operation can always be emitted, even if we need to
fall back to xor. Adjust the assertions to match.
Signed-off-by: Richard Henderson
---
While expanding the AA64 vector ORC, Altivec needs a bare NOT operation.
This failure does not appear for aa64 or power8 hosts because we have a
nativ
On 6/28/19 8:15 PM, Thomas Huth wrote:
> Bryce apparently never got around to work on this again, so I'll have
> another try now ...
>
> During Google Summer of Code 2011, Bryce Lanham added the possibility to
> emulate the NeXTcube machine in QEMU, e.g. see this URL for some details:
>
> https:/
Hi,
I was looking at Thomas' last series [*] where he adds the
NeXTcube machine, thinking about enforcing a new rule "new
machines must have tests". Then I realized the UART is not
yet implemented, so our current sample tests are not helpful.
Since the framebuffer is working, I gave a try at dump
Add a test of the NeXTcube framebuffer using the Tesseract OCR
engine on a screenshot of the framebuffer device.
The test is very quick:
$ avocado --show=app,ocr run tests/acceptance/machine_m68k_nextcube.py
JOB ID : f7d3c27976047036dc568183baf64c04863d9985
JOB LOG: ~/avocado/job-re
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/.travis.yml b/.travis.yml
index aeb9b211cd..16907b5a78 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -231,7 +231,7 @@ matrix:
# Acceptance (Functional) tests
-
On Sat, Jun 29, 2019 at 12:15:44PM +0200, Richard Henderson wrote:
> On 6/28/19 5:50 PM, Lucien Murray-Pitts wrote:
> > op_helper.c
> >static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
> >...
> > if (cs->exception_index == EXCP_ACCESS) {
> > ...
> > do_stack_fra
On 29/06/2019 13.53, Philippe Mathieu-Daudé wrote:
> Hi Thomas,
>
> On 6/28/19 8:15 PM, Thomas Huth wrote:
>> The NeXTcube uses a linear framebuffer with 4 greyscale colors and
>> a fixed resolution of 1120 * 832.
>> This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at
>>
>> http
On Wed, Feb 13, 2019 at 10:12 AM Palmer Dabbelt wrote:
>
> On Fri, 08 Feb 2019 10:57:17 PST (-0800), alistai...@gmail.com wrote:
> >
> > Good catch!
> >
> > Reviewed-by: Alistair Francis
>
> Ya, thanks -- that's a somewhat embarrassing bug, as someone else just fixed
> one on the line below :).
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