[Qemu-devel] [PATCH v3] deprecate -mem-path fallback to anonymous RAM

Fallback might affect guest or worse whole host performance or functionality if backing file were used to share guest RAM with another process. Patch deprecates fallback so that we could remove it in future and ensure that QEMU will provide expected behavior and fail if it can't use user provided

Re: [Qemu-devel] [PATCH v2 03/14] target/arm/monitor: Introduce qmp_query_cpu_model_expansion

Hi Drew, On 6/21/19 6:34 PM, Andrew Jones wrote: > Add support for the query-cpu-model-expansion QMP command to Arm. We > do this selectively, only exposing CPU properties which represent > optional CPU features which the user may want to enable/disable. Also, > for simplicity, we restrict the lis

Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes

On 6/25/19 7:55 PM, Mark Cave-Ayland wrote: > And here's where we are blowing up according to -d in_asm,op_out_asm: > > IN: > 0x00f22ca0: 101ffc84 vor v0, v31, v31 > > OP: > ld_i32 tmp0,env,$0xfff8 > movi_i32 tmp1,$0x0 > brcond_i32 tmp0,tmp1,lt,$L0 > > 00f22ca0 > ld_vec v128

Re: [Qemu-devel] [PATCH v2] block/rbd: add preallocation support

On Tue, Jun 25, 2019 at 06:06:02PM +0200, Max Reitz wrote: > On 06.05.19 14:23, Stefano Garzarella wrote: > > This patch adds the support of preallocation (off/full) for the RBD > > block driver. > > If available, we use rbd_writesame() to quickly fill the image when > > full preallocation is requi

Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64

On 6/26/19 8:07 AM, Palmer Dabbelt wrote: > On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote: >> On 6/24/19 8:08 PM, Joel Sing wrote: >>> Regarding the alignment for reservations, the >>> specification does require this, although I do not recall seeing any >>> enforcemen

[Qemu-devel] [PATCH v2 3/4] libvhost-user: implement VHOST_USER_PROTOCOL_F_MQ

Existing vhost-user device backends, including vhost-user-scsi and vhost-user-blk, support multiqueue but libvhost-user currently does not advertise this. VHOST_USER_PROTOCOL_F_MQ enables the VHOST_USER_GET_QUEUE_NUM request needed for a vhost-user master to query the number of queues. For exampl

[Qemu-devel] [PATCH v2 2/4] libvhost-user: support many virtqueues

Currently libvhost-user is hardcoded to at most 8 virtqueues. The device backend should decide the number of virtqueues, not libvhost-user. This is important for multiqueue device backends where the guest driver needs an accurate number of virtqueues. This change breaks libvhost-user and libvhos

[Qemu-devel] [PATCH v2 0/4] libvhost-user: VHOST_USER_PROTOCOL_F_MQ support

v2: * Add missing dev->max_queues = max_queues assignment in vu_init() [dgilbert] * Folded in Marc-André's Reviewed-By Sebastien Boeuf pointed out that libvhost-user doesn't advertise VHOST_USER_PROTOCOL_F_MQ. Today this prevents vhost-user-net multiqueue from working. In virtio-fs we also wa

[Qemu-devel] [PATCH v2 4/4] docs: avoid vhost-user-net specifics in multiqueue section

The "Multiple queue support" section makes references to vhost-user-net "queue pairs". This is confusing for two reasons: 1. This actually applies to all device types, not just vhost-user-net. 2. VHOST_USER_GET_QUEUE_NUM returns the number of virtqueues, not the number of queue pairs. Reword t

[Qemu-devel] [PATCH v2 1/4] libvhost-user: add vmsg_set_reply_u64() helper

The VhostUserMsg request is reused as the reply by message processing functions. This is risky since request fields may corrupt the reply if the vhost-user message handler function forgets to re-initialize them. Changing this practice would be very invasive but we can introduce a helper function

Re: [Qemu-devel] [PATCH v12 5/5] linux-user: Fix flock structure for MIPS O64 ABI

On Jun 19, 2019 6:34 PM, "Laurent Vivier" wrote: > > Le 19/06/2019 à 16:17, Aleksandar Markovic a écrit : > > From: Aleksandar Markovic > > > > Only MIPS O32 and N32 have special (different than other > > architectures) definition of structure flock in kernel. > > > > Bring flock definition for M

Re: [Qemu-devel] [PATCH v12 5/5] linux-user: Fix flock structure for MIPS O64 ABI

Le 26/06/2019 à 09:54, Aleksandar Markovic a écrit : > > On Jun 19, 2019 6:34 PM, "Laurent Vivier" > wrote: >> >> Le 19/06/2019 à 16:17, Aleksandar Markovic a écrit : >> > From: Aleksandar Markovic > >> > >> > Only MIPS O32 and N32 have sp

Re: [Qemu-devel] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore

On Fri, 17 May 2019 14:35:56 PDT (-0700), Alistair Francis wrote: On Fri, 2019-05-17 at 08:51 -0700, Bin Meng wrote: At present the PLIC is instantiated to support only one hart, while the machine allows at most 4 harts to be created. When more than 1 hart is configured, PLIC needs to instantiat

Re: [Qemu-devel] [PATCH 1/2] riscv: sifive_u: Do not create hard-coded phandles in DT

On Tue, 25 Jun 2019 18:47:15 PDT (-0700), bmeng...@gmail.com wrote: Hi, On Sat, May 18, 2019 at 5:34 AM Alistair Francis wrote: On Fri, 2019-05-17 at 08:51 -0700, Bin Meng wrote: > At present the cpu, plic and ethclk nodes' phandles are hard-coded > to 1/2/3 in DT. If we configure more than 1

Re: [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding

On Tue, 25 Jun 2019 18:47:33 PDT (-0700), bmeng...@gmail.com wrote: Hi, On Fri, Jun 7, 2019 at 2:46 AM Alistair Francis wrote: On Thu, Jun 6, 2019 at 5:55 AM Bin Meng wrote: > > On Thu, May 30, 2019 at 11:36 AM Bin Meng wrote: > > > > Hi Alistair, > > > > On Thu, May 30, 2019 at 11:14 AM Al

Re: [Qemu-devel] [PATCH] qemu-nbd: Permit TLS with Unix sockets

On Tue, Jun 25, 2019 at 09:49:42PM -0500, Eric Blake wrote: > Although you generally won't use encryption with a Unix socket (after > all, everything is local, so why waste the CPU power), there are > situations in testsuites where Unix sockets are much nicer than TCP > sockets. Since nbdkit allow

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

On Tue, 25 Jun 2019 23:58:34 PDT (-0700), bmeng...@gmail.com wrote: On Wed, Jun 26, 2019 at 4:23 AM Jonathan Behrens wrote: I just did some testing on a HiFive Unleashed board and can confirm what you are saying. The low 5 bits of both mcounteren and scounteren are writable (if you try to writ

Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64

On Wed, 26 Jun 2019 00:48:51 PDT (-0700), richard.hender...@linaro.org wrote: On 6/26/19 8:07 AM, Palmer Dabbelt wrote: On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote: On 6/24/19 8:08 PM, Joel Sing wrote: Regarding the alignment for reservations, the specification

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

On Tue, 25 Jun 2019 23:54:06 PDT (-0700), bmeng...@gmail.com wrote: Hi Palmer, On Tue, Jun 25, 2019 at 5:57 PM Palmer Dabbelt wrote: On Mon, 24 Jun 2019 16:03:20 PDT (-0700), finte...@gmail.com wrote: > Apparently my previous message didn't make it out onto the list (sorry > about all these e

Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64

On 6/26/19 10:25 AM, Palmer Dabbelt wrote: >> You misunderstand.  The code is exactly correct as-is.  The alignment check >> happens implicitly as a part of the softmmu tlb resolution. > > Sorry, I thought you said it wasn't happening for linux-user?  If it happens > for both then we're good. Oh,

Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64

On Wed, 26 Jun 2019 01:30:35 PDT (-0700), richard.hender...@linaro.org wrote: On 6/26/19 10:25 AM, Palmer Dabbelt wrote: You misunderstand.  The code is exactly correct as-is.  The alignment check happens implicitly as a part of the softmmu tlb resolution. Sorry, I thought you said it wasn't h

Re: [Qemu-devel] [Qemu-block] [PATCH] blk: postpone request execution on a context protected with "drained section"

On 24.06.2019 12:46, Denis Plotnikov wrote: > > > On 21.06.2019 12:59, Vladimir Sementsov-Ogievskiy wrote: >> 21.06.2019 12:16, Kevin Wolf wrote: >>> Am 09.04.2019 um 12:01 hat Kevin Wolf geschrieben: Am 02.04.2019 um 10:35 hat Denis Plotnikov geschrieben: > On 13.03.2019 19:04, Kevin

[Qemu-devel] [PATCH] target/i386: HAX: Enable ROM/ROM device memory region support

From: Hang Yuan Add ROM and ROM device memory region support in HAX. Their memory region is read only and write access will generate EPT violation. The violation will be handled in the HAX kernel with the following patch. https://github.com/intel/haxm/commit/33ceea09a1655fca12c47f1e112b1d269357f

Re: [Qemu-devel] [PATCH] qemu-nbd: Permit TLS with Unix sockets

On Tue, Jun 25, 2019 at 09:49:42PM -0500, Eric Blake wrote: > Although you generally won't use encryption with a Unix socket (after > all, everything is local, so why waste the CPU power), there are > situations in testsuites where Unix sockets are much nicer than TCP > sockets. Since nbdkit allow

Re: [Qemu-devel] [PATCH] target/i386: HAX: Enable ROM/ROM device memory region support

Patchew URL: https://patchew.org/QEMU/1561528815-4912-1-git-send-email-hang.y...@linux.intel.com/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 1561528815-4912-1-git-send-email-hang.y...@linux.intel.com Type: series Subject: [Qemu

Re: [Qemu-devel] [PATCH v8 03/10] dp8393x: manage big endian bus

On 6/25/19 7:09 PM, Laurent Vivier wrote: > Le 25/06/2019 à 17:57, Philippe Mathieu-Daudé a écrit : >> On 6/24/19 10:07 PM, Laurent Vivier wrote: >>> Hi, >>> >>> Jason, Can I have an Acked-by from you (as network devices maintainer)? >> >> Hmm something seems odd here indeed... >> >> What a stable

Re: [Qemu-devel] [PATCH v5 2/2] s390: diagnose 318 info reset and migration support

On 25.06.19 17:17, Collin Walling wrote: > index a606547..4c26754 100644 > --- a/target/s390x/cpu.h > +++ b/target/s390x/cpu.h > @@ -39,7 +39,13 @@ > > #define MMU_USER_IDX 0 > > -#define S390_MAX_CPUS 248 > +/* > + * HACK: The introduction of additional facility bytes in the Read Info > +

Re: [Qemu-devel] [PATCH v5 1/2] s390/kvm: header sync for diag318

On 25.06.19 17:17, Collin Walling wrote: > Signed-off-by: Collin Walling > --- > linux-headers/asm-s390/kvm.h | 4 > 1 file changed, 4 insertions(+) > > diff --git a/linux-headers/asm-s390/kvm.h b/linux-headers/asm-s390/kvm.h > index 03ab596..4a857bb 100644 > --- a/linux-headers/asm-s390/kv

Re: [Qemu-devel] [PATCH] virtio-pci: fix missing device properties

Hi On Wed, Jun 26, 2019 at 3:56 AM Eduardo Habkost wrote: > > On Wed, Jun 26, 2019 at 01:23:33AM +0200, Marc-André Lureau wrote: > > Since commit a4ee4c8baa37154 ("virtio: Helper for registering virtio > > device types"), virtio-gpu-pci, virtio-vga, and virtio-crypto-pci lost > > some properties:

Re: [Qemu-devel] [PATCH v2 02/14] target/arm/cpu: Ensure we can use the pmu with kvm

On 6/21/19 6:34 PM, Andrew Jones wrote: > We first convert the pmu property from a static property to one with > its own accessors. Then we use the set accessor to check if the PMU is > supported when using KVM. Indeed a 32-bit KVM host does not support > the PMU, so this check will catch an attemp

Re: [Qemu-devel] [PATCH v2 06/14] target/arm: Allow SVE to be disabled via a CPU property

Hi Drew, On 6/21/19 6:34 PM, Andrew Jones wrote: > Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via > a CPU property") we can disable the 'max' cpu model's VFP and neon > features, but there's no way to disable SVE. Add the 'sve=on|off' > property to give it that flexibility

Re: [Qemu-devel] [PATCH v2 05/14] target/arm/helper: zcr: Add build bug next to value range assumption

Hi Drew, On 6/21/19 6:34 PM, Andrew Jones wrote: > Suggested-by: Dave Martin > Signed-off-by: Andrew Jones > --- > target/arm/helper.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index df4276f5f6ca..edba94004e0b 100644 > --- a/target/arm

[Qemu-devel] [PATCH v6 8/8] target/mips: Fix big endian host behavior for interleave MSA instructions

From: Aleksandar Markovic Fix big endian host behavior for interleave MSA instructions. Previous fix used TARGET_WORDS_BIGENDIAN instead of HOST_WORDS_BIGENDIAN, which was a mistake. Signed-off-by: Aleksandar Markovic --- target/mips/msa_helper.c | 24 1 file changed,

[Qemu-devel] [PATCH v6 0/8] target/mips: Improve MSA TCG tests

From: Aleksandar Markovic This series contains various improvements and additions of MSA ASE TCG tests. v5->v6: - fixed bad values for some test cases of pack instructions - fixex big endian host behavior for interleave instructions v4->v5: - added patch on MIPS32R6 support - amended

[Qemu-devel] [PATCH v6 7/8] tests/tcg: target/mips: Fix some test cases for pack MSA instructions

From: Aleksandar Markovic Fix certian test cases for MSA pack instructions. Signed-off-by: Aleksandar Markovic --- .../tcg/mips/user/ase/msa/pack/test_msa_pckev_b.c | 64 +++--- .../tcg/mips/user/ase/msa/pack/test_msa_pckev_d.c | 64 +++--- .../tcg/mips/user/a

Re: [Qemu-devel] [PATCH v2 05/14] target/arm/helper: zcr: Add build bug next to value range assumption

On 6/21/19 6:34 PM, Andrew Jones wrote: > Suggested-by: Dave Martin > Signed-off-by: Andrew Jones > --- > target/arm/helper.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson > diff --git a/target/arm/helper.c b/target/arm/helper.c > index df4276f5f6ca..edba94004e0b 1006

[Qemu-devel] [PATCH v6 1/8] tests/tcg: target/mips: Add tests for MSA bit move instructions

From: Aleksandar Markovic Add tests for MSA bit move instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo --- tests/tcg/mips/include/wrappers_msa.h | 32 ++- .../mips/user/ase/msa/bit-move/test_msa_binsl_b.c | 214 + .../mips/user/

[Qemu-devel] [PATCH v6 2/8] tests/tcg: target/mips: Add tests for MSA move instructions

From: Aleksandar Markovic Add tests for MSA move instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo --- tests/tcg/mips/include/wrappers_msa.h | 8 ++ tests/tcg/mips/user/ase/msa/move/test_msa_move_v.c | 149 + tests/tcg/mips/user

[Qemu-devel] [PATCH v6 6/8] tests/tcg: target/mips: Add support for MSA MIPS32R6 testings

From: Aleksandar Markovic Add files for MSA MIPS32R6 target testings (copiling and running). Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo --- .../mips/user/ase/msa/test_msa_compile_32r6eb.sh | 627 + .../mips/user/ase/msa/test_msa_compile_32r6el.sh

[Qemu-devel] [PATCH v6 4/8] tests/tcg: target/mips: Amend tests for MSA int multiply instructions

From: Aleksandar Markovic Amend tests for MSA int multiply instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo --- tests/tcg/mips/include/wrappers_msa.h | 16 ++ .../user/ase/msa/int-multiply/test_msa_maddv_b.c | 214 + .../user/

[Qemu-devel] [PATCH v6 3/8] tests/tcg: target/mips: Amend tests for MSA int dot product instructions

From: Aleksandar Markovic Add tests for instructions whose result depends on the value in destination register (prior to instruction execution). Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo --- tests/tcg/mips/include/wrappers_msa.h | 40 .../ase/msa/int

Re: [Qemu-devel] [PATCH v6 8/8] target/mips: Fix big endian host behavior for interleave MSA instructions

> From: Aleksandar Markovic > Sent: Wednesday, June 26, 2019 12:07 PM > To: qemu-devel@nongnu.org > Cc: Aleksandar Markovic; Aleksandar Rikalo > Subject: [PATCH v6 8/8] target/mips: Fix big endian host behavior for > interleave MSA instructions > > From: Aleksandar Markovic > > Fix big endian ho

Re: [Qemu-devel] [PATCH v8 03/10] dp8393x: manage big endian bus

Le 26/06/2019 à 10:57, Philippe Mathieu-Daudé a écrit : > On 6/25/19 7:09 PM, Laurent Vivier wrote: >> Le 25/06/2019 à 17:57, Philippe Mathieu-Daudé a écrit : >>> On 6/24/19 10:07 PM, Laurent Vivier wrote: Hi, Jason, Can I have an Acked-by from you (as network devices maintainer)? >>

Re: [Qemu-devel] [PATCH v6 7/8] tests/tcg: target/mips: Fix some test cases for pack MSA instructions

> From: Aleksandar Markovic > Sent: Wednesday, June 26, 2019 12:07 PM > To: qemu-devel@nongnu.org > Cc: Aleksandar Markovic; Aleksandar Rikalo > Subject: [PATCH v6 7/8] tests/tcg: target/mips: Fix some test cases for pack > MSA instructions > > From: Aleksandar Markovic > > Fix certian test case

Re: [Qemu-devel] [PATCH v2 06/14] target/arm: Allow SVE to be disabled via a CPU property

On 6/21/19 6:34 PM, Andrew Jones wrote: > Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via > a CPU property") we can disable the 'max' cpu model's VFP and neon > features, but there's no way to disable SVE. Add the 'sve=on|off' > property to give it that flexibility. We also

Re: [Qemu-devel] [Qemu-block] [RFC] nvme: how to support multiple namespaces

On 26/06/19 06:46, Markus Armbruster wrote: >> I'm not sure how to wire it together without the bus abstraction? So >> I'll stick with the bus for now. It *is* extremely convenient! > > As far as I can tell offhand, a common use of bus-less connections > between devices is wiring together composit

Re: [Qemu-devel] [PATCH v4 1/5] virtio: add "use-started" property

On Wed, 26 Jun 2019 10:31:26 +0800 elohi...@gmail.com wrote: > From: Xie Yongji > > In order to avoid migration issues, we introduce a "use-started" > property to the base virtio device to indicate whether use > "started" flag or not. This property will be true by default and > set to false when

Re: [Qemu-devel] [PATCH v3] deprecate -mem-path fallback to anonymous RAM

On 6/26/19 9:42 AM, Igor Mammedov wrote: > Fallback might affect guest or worse whole host performance > or functionality if backing file were used to share guest RAM > with another process. > > Patch deprecates fallback so that we could remove it in future > and ensure that QEMU will provide expe

Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes

g On Tue, Jun 25, 2019 at 05:56:42PM +0200, Richard Henderson wrote: > On 6/25/19 5:37 PM, Mark Cave-Ayland wrote: > > The problem is that in tcg/tcg-op.h we define "DEF(dup2_vec, 1, 2, 0, > > IMPLVEC | > > IMPL(TCG_TARGET_REG_BITS == 32))" and in the last patchset dup2_vec isn't > > introduced

Re: [Qemu-devel] [PATCH v2 1/5] iotests: Add -display none to the qemu options

On 6/25/19 11:19 PM, Max Reitz wrote: > Without this argument, qemu will print an angry message about not being > able to connect to a display server if $DISPLAY is not set. For me, > that breaks iotests.supported_formats() because it thus only sees > ["Could", "not", "connect"] as the supported f

Re: [Qemu-devel] [PATCH v2 09/14] target/arm/kvm64: Move the get/put of fpsimd registers out

On 6/21/19 6:34 PM, Andrew Jones wrote: > Move the getting/putting of the fpsimd registers out of > kvm_arch_get/put_registers() into their own helper functions > to prepare for alternatively getting/putting SVE registers. > > No functional change. > > Signed-off-by: Andrew Jones > Reviewed-by:

Re: [Qemu-devel] [PATCH v4 0/5] virtio: fix some issues of "started" and "start_on_kick" flag

On 26/06/2019 04:31, elohi...@gmail.com wrote: > From: Xie Yongji Could you use the same address to send the series? Or may be you need to add a Signed-off-by with your name and this address? I don't know what is the rule when someone send a patch with a different address than the author one but

Re: [Qemu-devel] [PATCH v2 1/4] add and link a statistic struct to TBs

Alex Bennée writes: > Vanderson Martins do Rosario writes: > >> When the tb_flush removes a block and it's recreated, this shouldn't >> be creating a new block but using the one that is found by: >> >> lookup_result = g_list_find_custom(tb_ctx.tb_statistics, new_stats, >> statistics_cmp); >> >

Re: [Qemu-devel] [PATCH] Regression for m68k causing Single-Step via GDB/RSP to not single step

Hi Richard/Laurent, Great catch, I also just stumbled on this problem as well which I didnt see with my other application code. But I have another problem after applying the changes from your email, "RTE" and breakpoints around a MOV/BusException/RTE behave oddly. I would like to test with the s

Re: [Qemu-devel] [SeaBIOS] [PATCH v3 3/4] geometry: Add boot_lchs_find_*() utility functions

Kevin, Rethinking this change (where we construct the device path from outside and call boot_prio_find()), this is pretty tricky to implement since we need to take care of csm_bootprio_ata() and csm_bootprio_pci() which do not work with device path. In addition, bootprio_find_fdc_device

Re: [Qemu-devel] [PATCH] Regression for m68k causing Single-Step via GDB/RSP to not single step

Le 26/06/2019 à 13:24, Lucien Anti-Spam a écrit : > Hi Richard/Laurent, > > Great catch, I also just stumbled on this problem as well which I didnt > see with my other application code. > > But I have another problem after applying the changes from your email, > "RTE" and breakpoints around a MOV

[Qemu-devel] [PULL 03/17] hw/mips/gt64xxx_pci: Fix 'braces' coding style issues

From: Philippe Mathieu-Daudé Since we'll move this code around, fix its style first: ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Message-Id: <20190624222844.26584-4-f4...@amsat.org> --- hw/mips/gt64xxx

[Qemu-devel] [PULL 02/17] hw/mips/gt64xxx_pci: Fix 'tabs' coding style issues

From: Philippe Mathieu-Daudé Since we'll move this code around, fix its style first: ERROR: code indent should never use tabs Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Message-Id: <20190624222844.26584-3-f4...@amsat.org> --- hw/mips/gt64xxx_pci.c | 312

[Qemu-devel] [PULL 04/17] hw/mips/gt64xxx_pci: Fix 'spaces' coding style issues

From: Philippe Mathieu-Daudé Since we'll move this code around, fix its style first: ERROR: space prohibited between function name and open parenthesis ERROR: line over 90 characters Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Message-Id: <20190624222844.26584-5

[Qemu-devel] [PULL 07/17] hw/mips/gt64xxx_pci: Align the pci0-mem size

From: Philippe Mathieu-Daudé One byte is missing, use an aligned size. (qemu) info mtree memory-region: pci0-mem -fffe (prio 0, i/o): pci0-mem ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovi

[Qemu-devel] [PULL 01/17] hw/mips/gt64xxx_pci: Fix multiline comment syntax

From: Philippe Mathieu-Daudé Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline comment syntax. Since we'll move this code around, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Message-Id: <20190624222844.26584-2-f4...@amsat.org> --- h

[Qemu-devel] [PULL 06/17] hw/mips/gt64xxx_pci: Convert debug printf()s to trace events

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Message-Id: <20190624222844.26584-7-f4...@amsat.org> --- Makefile.objs | 1 + hw/mips/gt64xxx_pci.c | 29 ++--- hw/mips/trace-events | 4 3 files changed,

[Qemu-devel] [PULL 08/17] dma/rc4030: Fix off-by-one error in specified memory region size

From: Aleksandar Markovic The size is one byte less than it should be: address-space: rc4030-dma -fffe (prio 0, i/o): rc4030.dma rc4030 is used in MIPS Jazz board context. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Reviewed-by: Philippe Ma

[Qemu-devel] [PULL 09/17] dma/rc4030: Minor code style cleanup

From: Aleksandar Markovic Fix some simple checkpatch.pl warnings in rc4030.c. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1561472838-32272-3-git-send-email-aleksandar.marko...@rt-rk.com> --- hw/dma/rc4030.c | 18 +

[Qemu-devel] [PULL 10/17] tests/tcg: target/mips: Add tests for MSA bit move instructions

From: Aleksandar Markovic Add tests for MSA bit move instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1561543629-20327-2-git-send-email-aleksandar.marko...@rt-rk.com> --- tests/tcg/mips/include/wrappers_msa.h | 32 ++- .../mips/user/as

[Qemu-devel] [PULL 05/17] hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Message-Id: <20190624222844.26584-6-f4...@amsat.org> --- hw/mips/gt64xxx_pci.c | 48 +--- 1 file changed, 37 insertions(+), 11 deletions(-) diff --gi

[Qemu-devel] [PULL 17/17] target/mips: Fix big endian host behavior for interleave MSA instructions

From: Aleksandar Markovic Fix big endian host behavior for interleave MSA instructions. Previous fix used TARGET_WORDS_BIGENDIAN instead of HOST_WORDS_BIGENDIAN, which was a mistake. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1561543629-20327-9-git-send-emai

[Qemu-devel] [PULL 13/17] tests/tcg: target/mips: Amend tests for MSA int multiply instructions

From: Aleksandar Markovic Amend tests for MSA int multiply instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1561543629-20327-5-git-send-email-aleksandar.marko...@rt-rk.com> --- tests/tcg/mips/include/wrappers_msa.h | 16 ++ .../user/as

[Qemu-devel] [PULL 00/17] MIPS queue for June 2016th, 2019

From: Aleksandar Markovic The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 15:40:50 +0100) are available in the git repository at: https://github.com/AMarkovic

[Qemu-devel] [PULL 12/17] tests/tcg: target/mips: Amend tests for MSA int dot product instructions

From: Aleksandar Markovic Add tests for instructions whose result depends on the value in destination register (prior to instruction execution). Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1561543629-20327-4-git-send-email-aleksandar.marko...@rt-rk.com> ---

[Qemu-devel] trace: floating-point values blacklisted

[I forgot to Cc the list, resending] Hi Stefan, Lluís, When trying to add a trace event to report a float value, I get: trace-events:11: Argument type 'float' is not in whitelist. Only standard C types and fixed size integer types should be used. struct, union, and other complex pointer types sh

[Qemu-devel] [PULL 11/17] tests/tcg: target/mips: Add tests for MSA move instructions

From: Aleksandar Markovic Add tests for MSA move instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1561543629-20327-3-git-send-email-aleksandar.marko...@rt-rk.com> --- tests/tcg/mips/include/wrappers_msa.h | 8 ++ tests/tcg/mips/user/a

[Qemu-devel] [PULL 16/17] tests/tcg: target/mips: Fix some test cases for pack MSA instructions

From: Aleksandar Markovic Fix certian test cases for MSA pack instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1561543629-20327-8-git-send-email-aleksandar.marko...@rt-rk.com> --- .../tcg/mips/user/ase/msa/pack/test_msa_pckev_b.c | 64 +++--

[Qemu-devel] [PULL 15/17] tests/tcg: target/mips: Add support for MSA MIPS32R6 testings

From: Aleksandar Markovic Add files for MSA MIPS32R6 target testings (copiling and running). Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1561543629-20327-7-git-send-email-aleksandar.marko...@rt-rk.com> --- .../mips/user/ase/msa/test_msa_compile_32r6eb.sh |

[Qemu-devel] [PULL 6/6] linux-user: set default PPC64 CPU

The default CPU for pseries has been set to POWER9 by default. We can use the same default for linux-user Signed-off-by: Laurent Vivier Message-Id: <20190609143521.19374-2-laur...@vivier.eu> Signed-off-by: Laurent Vivier --- linux-user/ppc/target_elf.h | 2 +- 1 file changed, 1 insertion(+), 1

[Qemu-devel] [PULL 5/6] linux-user: update PPC64 HWCAP2 feature list

QEMU_PPC_FEATURE2_VEC_CRYPTO enables the use of VSX instructions in libcrypto that are accelerated by the TCG vector instructions now. QEMU_PPC_FEATURE2_DARN allows to use the new builtin qemu_guest_getrandom() function. Signed-off-by: Laurent Vivier Message-Id: <20190609143521.19374-1-laur...@v

[Qemu-devel] [PULL 1/6] util/path: Do not cache all filenames at startup

From: Richard Henderson If one uses -L $PATH to point to a full chroot, the startup time is significant. In addition, the existing probing algorithm fails to handle symlink loops. Instead, probe individual paths on demand. Cache both positive and negative results within $PATH, so that any one

[Qemu-devel] [PULL 0/6] Linux user for 4.1 patches

The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 15:40:50 +0100) are available in the Git repository at: git://github.com/vivier/qemu.git tags/linux-user-for-4.1

[Qemu-devel] [PULL 3/6] linux-user: Add support for setsockopt() option SOL_ALG

From: Yunqiang Su Add support for options SOL_ALG of the syscall setsockopt(). This option is used in relation to Linux kernel Crypto API, and allows a user to set additional information for the cipher operation via syscall setsockopt(). The field "optname" must be one of the following: - ALG_

Re: [Qemu-devel] trace: floating-point values blacklisted

Philippe Mathieu-Daudé writes: > [I forgot to Cc the list, resending] > > Hi Stefan, Lluís, > > When trying to add a trace event to report a float value, I get: > > trace-events:11: Argument type 'float' is not in whitelist. Only > standard C types and fixed size integer types should be used. s

[Qemu-devel] [PULL 2/6] linux-user: emulate msgsnd(), msgrcv() and semtimedop()

When we have updated kernel headers to 5.2-rc1 we have introduced new syscall numbers that can be not supported by older kernels and fail with ENOSYS while the guest emulation succeeded before because the syscalls were emulated with ipc(). This patch fixes the problem by using ipc() if the new sys

[Qemu-devel] [PULL 4/6] linux-user: Add support for setsockopt() options IPV6__MEMBERSHIP

From: Neng Chen Add support for the option IPV6__MEMBERSHIP of the syscall setsockopt(). This option controls membership in multicast groups. Argument is a pointer to a struct ipv6_mreq. The glibc header defines the ipv6_mreq structure, which includes the following members: struct in6_addr

[Qemu-devel] [PATCH 2/2] hw/timer/m48t59: Convert debug printf()s to trace events

Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/m48t59-internal.h | 5 - hw/timer/m48t59.c | 11 +-- hw/timer/trace-events | 6 ++ 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/timer/m48t59-internal.h b/hw/timer/m48t59-internal.h index 4d4f

Re: [Qemu-devel] [PATCH v5 2/2] s390: diagnose 318 info reset and migration support

On Wed, 26 Jun 2019 11:12:04 +0200 Christian Borntraeger wrote: > On 25.06.19 17:17, Collin Walling wrote: > > index a606547..4c26754 100644 > > --- a/target/s390x/cpu.h > > +++ b/target/s390x/cpu.h > > @@ -39,7 +39,13 @@ > > > > #define MMU_USER_IDX 0 > > > > -#define S390_MAX_CPUS 248 > >

[Qemu-devel] [PATCH 1/2] MAINTAINERS: Add missing m48t59 files to the PReP section

Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cad58b9487..fbe89c0812 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1047,6 +1047,8 @@ F: hw/pci-host/prep.[hc] F: hw/isa/i82378.c F: hw/isa/pc87312.c F:

[Qemu-devel] [PATCH 0/2] hw/timer/m48t59: Convert to trace events

Another trivial cleanup series. Philippe Mathieu-Daudé (2): MAINTAINERS: Add missing m48t59 files to the PReP section hw/timer/m48t59: Convert debug printf()s to trace events MAINTAINERS| 2 ++ hw/timer/m48t59-internal.h | 5 - hw/timer/m48t59.c | 11 +-

Re: [Qemu-devel] trace: floating-point values blacklisted

On Wed, Jun 26, 2019 at 01:57:43PM +0200, Philippe Mathieu-Daudé wrote: > [I forgot to Cc the list, resending] > > Hi Stefan, Lluís, > > When trying to add a trace event to report a float value, I get: > > trace-events:11: Argument type 'float' is not in whitelist. Only > standard C types and fi

Re: [Qemu-devel] [PATCH v5 2/2] s390: diagnose 318 info reset and migration support

On Tue, 25 Jun 2019 11:17:09 -0400 Collin Walling wrote: > DIAGNOSE 0x318 (diag318) is a privileged s390x instruction that must > be intercepted by SIE and handled via KVM. Let's introduce some > functions to communicate between QEMU and KVM via ioctls. These > will be used to get/set the diag318

[Qemu-devel] [SeaBIOS] [PATCH v4 0/5] Add Qemu to SeaBIOS LCHS interface

v1: Non-standard logical geometries break under QEMU. A virtual disk which contains an operating system which depends on logical geometries (consistent values being reported from BIOS INT13 AH=08) will most likely break under QEMU/SeaBIOS if it has non-standard logical geometries - for example 56

[Qemu-devel] [SeaBIOS] [PATCH v4 2/5] boot: Reorder functions in boot.c

Currently glob_prefix() and build_pci_path() are under the "Boot priority ordering" section. Move them to a new "Helper search functions" section since we will reuse them in the next commits. Reviewed-by: Karl Heubaum Reviewed-by: Arbel Moshe Signed-off-by: Sam Eiderman --- src/boot.c | 94 +++

[Qemu-devel] [SeaBIOS] [PATCH v4 3/5] boot: Build ata and scsi paths in function

Introduce build_scsi_path() and build_ata_path(). We will reuse these functions in the next commit. Reviewed-by: Karl Heubaum Reviewed-by: Arbel Moshe Signed-off-by: Sam Eiderman --- src/boot.c | 36 1 file changed, 28 insertions(+), 8 deletions(-) diff --

[Qemu-devel] [QEMU] [PATCH v5 1/8] block: Refactor macros - fix tabbing

Fixing tabbing in block related macros. Reviewed-by: Karl Heubaum Reviewed-by: Arbel Moshe Signed-off-by: Sam Eiderman --- hw/ide/qdev.c| 2 +- include/hw/block/block.h | 16 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/ide/qdev.c b/hw/ide/qde

[Qemu-devel] [SeaBIOS] [PATCH v4 1/5] geometry: Read LCHS from fw_cfg

Read bios geometry for boot devices from fw_cfg. By receiving LCHS values directly from QEMU through fw_cfg we will be able to support logical geometries which can not be inferred by SeaBIOS itself. (For instance: A 8GB virtio-blk hard drive which was originally created as an IDE and must report L

[Qemu-devel] [SeaBIOS] [PATCH v4 4/5] geometry: Add boot_lchs_find_*() utility functions

Adding the following utility functions: * boot_lchs_find_pci_device * boot_lchs_find_scsi_device * boot_lchs_find_ata_device These will be used to apply LCHS values received through fw_cfg. Reviewed-by: Karl Heubaum Reviewed-by: Arbel Moshe Signed-off-by: Sam Eiderman --- src/Kco

Re: [Qemu-devel] [PATCH] virtio-pci: fix missing device properties

On Wed, Jun 26, 2019 at 11:48:20AM +0200, Marc-André Lureau wrote: > Hi > > On Wed, Jun 26, 2019 at 3:56 AM Eduardo Habkost wrote: > > > > On Wed, Jun 26, 2019 at 01:23:33AM +0200, Marc-André Lureau wrote: > > > Since commit a4ee4c8baa37154 ("virtio: Helper for registering virtio > > > device typ

[Qemu-devel] [QEMU] [PATCH v5 3/8] bootdevice: Add interface to gather LCHS

Add an interface to provide direct logical CHS values for boot devices. We will use this interface in the next commits. Reviewed-by: Karl Heubaum Reviewed-by: Arbel Moshe Signed-off-by: Sam Eiderman --- bootdevice.c| 55 + include/sys

[Qemu-devel] [SeaBIOS] [PATCH v4 5/5] geometry: Apply LCHS values for boot devices

Boot devices which use overriden LCHS values are: * ata * ahci * scsi * esp * lsi * megasas * mpt * pvscsi * virtio * virtio-blk We use these values in get_translation() and setup_translation() by introducing a new translation type:

[Qemu-devel] [QEMU] [PATCH v5 4/8] scsi: Propagate unrealize() callback to scsi-hd

We will need to add LCHS removal logic to scsi-hd's unrealize() in the next commit. Reviewed-by: Karl Heubaum Reviewed-by: Arbel Moshe Signed-off-by: Sam Eiderman --- hw/scsi/scsi-bus.c | 15 +++ include/hw/scsi/scsi.h | 1 + 2 files changed, 16 insertions(+) diff --git a/hw/

[Qemu-devel] [QEMU] [PATCH v5 0/8] Add Qemu to SeaBIOS LCHS interface

v1: Non-standard logical geometries break under QEMU. A virtual disk which contains an operating system which depends on logical geometries (consistent values being reported from BIOS INT13 AH=08) will most likely break under QEMU/SeaBIOS if it has non-standard logical geometries - for example 56

[Qemu-devel] [QEMU] [PATCH v5 2/8] block: Support providing LCHS from user

Add logical geometry variables to BlockConf. A user can now supply "lcyls", "lheads" & "lsecs" for any HD device that supports CHS ("cyls", "heads", "secs"). These devices include: * ide-hd * scsi-hd * virtio-blk-pci In future commits we will use the provided LCHS and pass it to the

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