Patchew URL:
https://patchew.org/QEMU/20190621213712.16222-1-liran.a...@oracle.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
m
On Fri, Jun 21, 2019 at 07:01:20PM -0300, Fabiano Rosas wrote:
> This is a left-over from "f4ec5e26ed vfio: Add host side DMA window
> capabilities", which added support to more than one DMA window.
>
> Signed-off-by: Fabiano Rosas
Acked-by: David Gibson
> ---
> include/hw/vfio/vfio-common.h
On Sat, Jun 22, 2019 at 4:13 PM Stefan Hajnoczi wrote:
> On Tue, Jun 11, 2019 at 10:57 AM Stefan Hajnoczi wrote:
> > On Mon, Jun 10, 2019 at 07:18:53PM +0530, Aarushi Mehta wrote:
> > > This patch series adds support for the newly developed io_uring Linux AIO
> > > interface. Linux io_uring is fa
On Fri, 21 Jun 2019 17:23:44 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Jun 20, 2019 at 7:49 PM Palmer Dabbelt wrote:
On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistai...@gmail.com wrote:
> On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt wrote:
>>
>> On Mon, 17 Jun 2019 18:31:00 PDT (-07
On Thu, 20 Jun 2019 22:40:24 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Fri, Jun 21, 2019 at 10:53 AM Palmer Dabbelt wrote:
On Wed, 19 Jun 2019 06:42:21 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Alistair,
>
> On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis wrote:
>>
>> On Fri, J
On Fri, Jun 21, 2019 at 9:38 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Alistair,
>
> On 6/19/19 6:54 AM, Alistair Francis wrote:
> > Add M mode initial entry PC and SP properties.
> >
> > Signed-off-by: Alistair Francis
> > ---
> > target/arm/cpu.c | 47
From: Aleksandar Markovic
Changes since v4:
* Patch 1, "tcg/ppc: Introduce Altivec registers", is divided into
ten smaller patches.
* The net result (code-wise) is not changed between former patch 1
and ten new patches.
* Remaining (2-7) patches from v4 are applied verbatim.
* Thi
From: Richard Henderson
Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg
From: Richard Henderson
This line is just preparation for full vector multiply support
in some of subsequent patches.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/ppc/tcg-target.inc.c b
From: Richard Henderson
Altivec (in all its versions) supports 32 128-bit vector registers,
whase names are by convention v0, v1,..., and v32.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 11 +-
tcg/ppc/tcg-target.inc.c | 88 ++
From: Richard Henderson
This includes double-word loads and stores, double-word load and splat,
double-word permute, and bit select. All of which require multiple
operations in the base Altivec instruction set.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/t
From: Richard Henderson
Introduce macros VRT(), VRA(), VRB(), VRC() used for coding/decoding
elements of Altivec instructions.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/ppc/tcg-
From: Richard Henderson
Add support for vector maximum/minimum using Altivec instructions
VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and
VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +
From: Richard Henderson
Add empty file tcg-target.opc.h to be used in future.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.opc.h | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 tcg/ppc/tcg-target.opc.h
diff --git a/tcg/ppc/tcg-target
From: Richard Henderson
Add support for vector add/subtract using Altivec instructions:
VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 20
1 file changed, 20 insertio
From: Richard Henderson
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58
From: Richard Henderson
This is only used for 32-bit hosts.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 3005c51..61732c1
From: Richard Henderson
Introduce macro VX4() used for coding/decoding Altivec instructions.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
From: Richard Henderson
Add various bits and peaces related mostly to load and store
operations. In that context, logic, compare, and splat Altivec
instructions are used, and, therefore, the support for emitting
them is included in this patch too.
Signed-off-by: Richard Henderson
Signed-off-by:
From: Richard Henderson
This includes vector load/store with immediate offset, some extra
move and splat insns, compare ne, and negate.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 103 +++
From: Richard Henderson
Detect during initialization if the emulated CPU supports Altivec,
and store the result in the flag have_isa_altivec. The definition
of Altivec SIMD instructions set evolved over time. Different
generations of Altivec will be distinguished by other flags in TCG,
and they a
On Sat, Jun 22, 2019 at 5:02 PM Mark Cave-Ayland
wrote:
>
> On 22/06/2019 15:20, Mark Cave-Ayland wrote:
>
> > I've just given your tcg-ppc-vsx branch a spin here, and like Howard I'm
> > getting
> > segfaults trying to launch my MacOS images :( The segfault is weird: it
> > doesn't get
> > cau
On Fri, 21 Jun 2019 at 14:23, Max Reitz wrote:
>
> The following changes since commit 33d609990621dea6c7d056c86f707b8811320ac1:
>
> Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
> (2019-06-18 17:00:52 +0100)
>
> are available in the Git repository at:
>
> https:/
From: Richard Henderson
This includes single-word loads and stores, lots of double-word
arithmetic, and a few extra logical operations.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 111 +++
On Sun, 23 Jun 2019 at 16:22, Juan Rafael García Blanco
wrote:
> I think the latest changes to qemu-io-cmds.c make it impossible to compile
> under macOS. It now uses clock_gettime, which is not available in this OS.
> I’m using 10.9.5; I think this function is now included in 10.12.
>
> I would
From: Richard Henderson
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 112 ++-
tcg/ppc/tcg-target.opc.h | 8
3 f
Patchew URL:
https://patchew.org/QEMU/1561309489-16146-1-git-send-email-aleksandar.marko...@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes
Type: series
Message-id: 1
Public bug reported:
Steps to reproduce
- Open ESXi 6.5 Web UI
- Export OVF
- qemu-img convert disk.vmdk disk.qcow2
Error:
qemu-img: Could not open './disk-1.vmdk': Invalid footer
I found another person having this problem here:
https://forum.proxmox.com/threads/error-converting-vmdk-file-t
I just compiled the version in the master branch and the same error
occurred.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1833871
Title:
qemu-img convert file.vmdk: Invalid footer
Status in QEMU
Probably my image was corrupt since it works with another image. So this
bug can be closed.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1833871
Title:
qemu-img convert file.vmdk: Invalid footer
The ibm,get_system_parameter rtas call is used by the guest to retrieve
data relating to certain parameters of the system. The SPLPAR
characteristics option (token 20) is used to determin characteristics of
the environment in which the lpar will run.
It may be useful for a guest to know the number
Patchew URL:
https://patchew.org/QEMU/20190624013921.11944-1-sjitindarsi...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [QEMU-PPC] [PATCH] powerpc/spapr: Add host threads
parameter to ibm, get_system_parame
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1577937
Title:
netbeans no
On Thu, Jun 20, 2019 at 09:04:43PM +0800, Peter Xu wrote:
> On Thu, Jun 20, 2019 at 08:59:55PM +0800, Peter Xu wrote:
> > On Thu, Jun 20, 2019 at 10:35:29AM +0200, Paolo Bonzini wrote:
> > > On 20/06/19 06:02, Peter Xu wrote:
> > > > Seems workable, to be explicit - we can even cut it into chunks w
if an entry has parts out of scope of notifier's range, print warning
message.
Out of scope mapping/unmapping would cause problem, as in below case:
1. initially there are two notifiers with ranges
0-0xfedf, 0xfef0-0x,
IOVAs from 0x3c00 - 0x3c1f is in shadow page t
It adds a new structure which is linked with each TBs and stores its statistics.
We collect the execution count of the TBs and store in this new structure.
The information stored in this new struct is then used to support a new
command line -d hot_tbs:N which dumps information of the N most hot TBs
We want to store statistics for each TB even after flushes.
We do not want to modify or grow the TB struct.
So we create a new struct to contain this statistics and
link it to each TB while they are created.
Signed-off-by: Vanderson M. do Rosario
---
accel/tcg/translate-all.c | 40 ++
Adding a function to dump the Nth hottest TBs.
The block PC, execution count and ops is dump to the log.
Signed-off-by: Vanderson M. do Rosario
---
accel/tcg/translate-all.c | 45 +++
include/exec/exec-all.h | 2 ++
2 files changed, 47 insertions(+)
diff -
We collect the number of times each TB is executed
and store it in the its TBStatistics.
We also count the number of times the execution counter overflows.
Signed-off-by: Vanderson M. do Rosario
---
accel/tcg/tcg-runtime.c | 10 ++
accel/tcg/tcg-runtime.h | 2 ++
accel/tcg/translato
Enable in-kernel handling of the hcall H_PURR. This means that if the
kernel implements an hcall handler for H_PURR, it will be used.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr.c | 3 +++
target/ppc/kvm.c | 5 +
target/ppc/kvm_ppc.h | 5 +
3 files changed, 13 insertio
add option to dump the N most hot TB blocks.
-d hot_tbs:N
Signed-off-by: vandersonmr
---
include/qemu/log-for-trace.h | 2 ++
linux-user/exit.c| 3 +++
util/log.c | 9 +
3 files changed, 14 insertions(+)
diff --git a/include/qemu/log-for-trace.h b/include/q
The hcall H_PURR is used by a guest to read the PURR (processor
utilisation of resources register). A guest expects that this register
will count at a rate of timebase scaled by the number of guest vcpus
present in the vcore. That is the per vcpu purr will count at a rate of
timebase / # vcpus per
Patchew URL:
https://patchew.org/QEMU/20190624055442.2973-1-vanderson...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2 0/4] dumping hot TBs
Type: series
Message-id: 20190624055442.2973-1-vanderson...
On Mon, Jun 24, 2019 at 01:22:55AM -0400, Yan Zhao wrote:
> On Thu, Jun 20, 2019 at 09:04:43PM +0800, Peter Xu wrote:
> > On Thu, Jun 20, 2019 at 08:59:55PM +0800, Peter Xu wrote:
> > > On Thu, Jun 20, 2019 at 10:35:29AM +0200, Paolo Bonzini wrote:
> > > > On 20/06/19 06:02, Peter Xu wrote:
> > > >
Hello,
I have the same qemu behaviour. It happens every time I have unplugged physical
usb device attached to guest from the host system. My device is USB GSM dongle.
Some times it disconnects and reconnects again for unknown reason, may be power
loss... With version 3.1.0 qemu (gentoo linux) th
Yan & Paolo,
I've re-ordered the patch into two, and I'm making bold to do that
with your authorships and sign-offs as I see correct. Please reply if
any of you have problem with that.
Yan,
Please feel free to test this series and offer your tested-by again
here. I can't do that for you becaus
From: Paolo Bonzini
This is an replacement work of Yan Zhao's patch:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg625340.html
vtd_address_space_unmap() will do proper page mask alignment to make
sure each IOTLB message will have correct masks for notification
messages (2^N-1), but some
From: Yan Zhao
IOMMUNotifier is with inclusive ranges, so we should check
against (VTD_ADDRESS_SIZE(s->aw_bits) - 1).
Signed-off-by: Yan Zhao
[peterx: split from another bigger patch]
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Mon, Jun 17, 2019 at 4:53 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/16/19 12:19 PM, Joel Sing wrote:
> > +/*
> > + * Clear the load reservation, since an SC must fail if there is
> > + * an SC to any address, in between an LR and SC pair.
> > + */
> > +
On Mon, Jun 24, 2019 at 02:37:33PM +0800, Peter Xu wrote:
> From: Paolo Bonzini
>
> This is an replacement work of Yan Zhao's patch:
>
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg625340.html
>
> vtd_address_space_unmap() will do proper page mask alignment to make
> sure each IOTLB m
Rename struct BlockLatencyHistogram to BlockHistogram, and rename
related functions.
Make this struct and functions be common, they can be used widely.
Signed-off-by: zhenwei pi
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/accounting.c | 44 +++
Modify command 'block-latency-histogram-set' to make block histogram
interface common to use. And support block size histogram.
Thanks to Eric Blake&Vladimir Sementsov-Ogievskiy for the suggestions.
This command has been tested for half year on QEMU-2.12, and we found
that 3K+ virtual machines wri
Modify command 'block-latency-histogram-set' to 'block-histogram-set'
and modify struct 'BlockLatencyHistogramInfo' to struct
'BlockHistogramInfo', this makes block histogram interface common to
use.
Currently 'BlockHistogramType' supports 'latency', it works as same
as the old command 'block-late
Introduce block size histogram statics for block devices.
For read/write/flush operation type, the block size region
[0, +inf) is divided into subregions by several points.
It works like block latency histogram.
Signed-off-by: zhenwei pi
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/acco
On Mon, Jun 24, 2019 at 02:41:22AM -0400, Yan Zhao wrote:
> On Mon, Jun 24, 2019 at 02:37:33PM +0800, Peter Xu wrote:
> > From: Paolo Bonzini
> >
> > This is an replacement work of Yan Zhao's patch:
> >
> > https://www.mail-archive.com/qemu-devel@nongnu.org/msg625340.html
> >
> > vtd_address_sp
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