Currently we fill the memory space with two 64MB NOR images when
using persistent UEFI variables on virt board. Actually we only use
a very small(non-zero) part of the memory while the rest significant
large(zero) part of memory is wasted.
So this patch checks the block status and only writes the
On Fri, May 03, 2019 at 03:42:06PM -0300, Eduardo Habkost wrote:
> On Mon, Apr 29, 2019 at 09:22:12AM -0600, Alex Williamson wrote:
> [...]
> > > > What's a good 4.0.1 strategy to resolve this? Re-instate KVM irqchip
> > > > as the Q35 default? I can't see that simply switching to current QEMU
>
On 30/04/2019 17:25, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> void helper_xsaddqp(CPUPPCState *env, uint32_t opcode)
>> {
>> -ppc_vsr_t xt, xa, xb;
>> +ppc_vsr_t *xt = &env->vsr[rD(opcode) + 32];
>> +ppc_vsr_t *xa = &env->vsr[rA(opcode) + 32];
>> +
On 30/04/2019 17:29, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> #define VSX_LXVL(name, lj) \
>> void helper_##name(CPUPPCState *env, target_ulong addr, \
>> - target_ulong xt_num, target
On 30/04/2019 17:32, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
>> target_ulong xbn, uint32_t index)
>> {
>> -ppc_vsr_t xt, xb;
>> +ppc_vsr_t *xt = &env->vsr[xtn];
>> +
On 30/04/2019 17:36, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> +#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type)
>> \
>> +static void gen_##name(DisasContext *ctx)
>> \
>> +{
On 30/04/2019 17:38, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> +#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type)
>> \
>> +static void gen_##name(DisasContext *ctx)
>> \
>> +{
On 30/04/2019 17:41, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> Rather than perform the VSR register decoding within the helper itself,
>> introduce a new GEN_VSX_HELPER_X2_AB macro which performs the decode based
>> upon xA and xB at translation time.
>>
>> Signed-o
On 30/04/2019 17:43, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> Rather than perform the VSR register decoding within the helper itself,
>> introduce a new GEN_VSX_HELPER_X1 macro which performs the decode based
>> upon xB at translation time.
>>
>> Signed-off-by: Mar
On 30/04/2019 17:47, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> +#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type)
>> \
>> +static void gen_##name(DisasContext *ctx)
>> \
>> +{
On 30/04/2019 18:00, Richard Henderson wrote:
> On 4/28/19 7:38 AM, Mark Cave-Ayland wrote:
>> #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp)
>> \
>> void helper_##op(CPUPPCState *env, uint32_t opcode,
>> \
>> - ppc_vsr_t
Public bug reported:
QEMU does not support sprite/overlay in DMA-buf mode for Intel gvt
vGPUs. Some use cases relies on sprite plane support, e.g. hw
accelerated video playback in Windows 10 guest.
To support this feature, functions in both kernel and QEMU should be
implemented:
- query support
On 04/05/2019 22:02, Artyom Tarasenko wrote:
> AIX/PReP does access to the aliased IO registers of 53810.
> Implement aliasing to make the AIX driver work.
>
> Signed-off-by: Artyom Tarasenko
> ---
> hw/scsi/lsi53c895a.c | 17 ++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
On 04/05/2019 22:02, Artyom Tarasenko wrote:
> AIX 5.1 expects the base year to be 1900. Adjust accordingly.
>
> Signed-off-by: Artyom Tarasenko
> Reviewed-by: Hervé Poussineau
> ---
> hw/isa/i82378.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/isa/i82378.c
This is a trivial cleanup patch.
Signed-off-by: Yuval Shaia
---
hw/rdma/rdma_backend.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/hw/rdma/rdma_backend.c b/hw/rdma/rdma_backend.c
index d1660b6474..05f6b03221 100644
--- a/hw/rdma/rdma_backend.c
+++ b/hw/rdma/rdma_backend.c
@@ -14,16
Any GID change in guest must be propogate to host. This is already done
by firing QMP event to managment system such as libvirt which in turn
will update the host with the relevant change.
When qemu is executed on non-qmp framework (ex from command-line) we
need to update the host instead.
Fix it
On Fri, May 03, 2019 at 11:44:24PM +0800, Boxuan Li wrote:
> Use traces for debug message and qemu_log_mask for errors.
>
> Signed-off-by: Boxuan Li
> ---
> v1: https://patchew.org/QEMU/20190428110258.86681-1-libox...@connect.hku.hk/
> v2: https://patchew.org/QEMU/20190501081039.58938-1-libox...@
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 8 +---
hw/arm/Kconfig | 8
Some machines have an AHCI adapter, but no PCI. To be able to
compile hw/ide/ahci.c without CONFIG_PCI, we still need the two
functions msi_enabled() and msi_notify() for linking.
This is required for the new Kconfig-like build system, if a user
wants to compile a QEMU binary with just one machine
Some of our machines (like the ARM cubieboard) use CONFIG_AHCI for an AHCI
sysbus device, but do not use CONFIG_PCI since they do not feature a PCI
bus. With CONFIG_AHCI but without CONFIG_PCI, currently linking fails:
../hw/ide/ich.o: In function `pci_ich9_ahci_realize':
hw/ide/ich.c:124:
Add Kconfig dependencies for the Exynos-related boards (nuri and
smdkc210).
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
defau
Hi Peter,
the following changes since commit a6ae23831b05a11880b40f7d58e332c45a6b04f7:
Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request'
into staging (2019-05-03 15:26:09 +0100)
are available in the Git repository at:
https://gitlab.com/huth/qemu.git tags/pull-
Add Kconfig dependencies for the xilinx-zynq-a9 board.
This patch is based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
defa
Add Kconfig dependencies for the Strongarm collie machine.
This patch is based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 7 +--
hw/arm/Kconfig | 11 +++
2 files changed, 12 in
Add Kconfig dependencies for the PXA2xx machines (akita, borzoi,
connex and verdex gumstix, tosa, mainstone, spitz, terrier and z2).
This patch is based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathi
Add Kconfig dependencies for the highbank machine (and the midway
machine).
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
defau
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 24 -
hw/arm/Kconfig
Dependencies have been determined by looking at hw/arm/aspeed.c
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 7 +--
hw/arm/Kconfig | 10 ++
2 f
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 6 +-
hw/arm/Kconfig | 5 +
Dependencies have been determined by looking at hw/arm/virt.c
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/aarch64-softmmu.mak | 1 -
default-configs/arm-softmmu.mak | 11 +--
hw/arm/Kconfig
Add Kconfig dependencies for the fsl-imx31 / kzm machine.
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Peter Chubb
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
--
Add dependencies for the Cubitech Cubieboard.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 6 +-
hw/arm/Kconfig | 9 +
2 files changed, 10 insertions(+), 5 deletions(-)
diff
Netduino only depends on the stm32f205 SoC which in turn depends on
its components.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 9 +
hw/arm/Kconfig
Add Kconfig dependencies for the OMAP machines (cheetah, n800, n810,
sx1 and sx1-v1).
This patch is slightly based on earlier work by Ákos Kovács (i.e.
his "hw/arm/Kconfig: Add ARM Kconfig" patch).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
Add Kconfig dependencies for the mps2-an* machines.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 20 +---
hw/arm/Kconfig | 19 +++
2 files changed, 20 inse
Most of the code is directly controlled by the CONFIG_RASPI switch,
so not much to add here additionally.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 4 +---
hw/arm/Kconfig
Add Kconfig dependencies for the DIGIC / canon-a1100 machine.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 2 +-
hw/arm/Kconfig | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
dif
Add Kconfig dependencies for the Sabrelite / iMX6 machine.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 4 +---
hw/arm/Kconfig | 9 +
hw/arm/Makefile.objs| 3 ++-
3 fi
Dependencies have been determined with trial-and-error and by
looking at the xlnx-versal.c source file.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
hw/arm/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/Kconfig b/h
Add Kconfig dependencies for the emcraft-sf2 machine - we also
distinguish between the machine (CONFIG_EMCRAFT_SF2) and the SoC
(CONFIG_MSF2) now.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 3 +--
hw/ar
Add Kconfig dependencies for the NRF51 / microbit machine.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 3 +--
hw/arm/Kconfig | 6 ++
hw/arm/Makefile.ob
The PCI devices should be pulled in by default if PCI_DEVICES
is set, so there is no need anymore to enforce them in the configs
file.
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 8
1 file changed, 8 deletions(-)
diff --git a/defa
This cleans up most settings in default-configs/aarch64-softmmu.mak.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/aarch64-softmmu.mak | 4
hw/arm/Kconfig | 11 +
Dependencies have been determined with trial-and-error and by
looking at the musca.c source file.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
hw/arm/Kconfig | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/
IMX25, IMX7 and IMX6UL were still missing the Kconfig dependencies.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 2 --
hw/arm/Kconfig | 19 +++
2 files changed, 19 insert
On 5/5/19 2:27 AM, Mark Cave-Ayland wrote:
> I've spent a bit of time today going through the functions and it seems that
> all
> functions which have an xt parameter, minus a couple of the TEST macros,
> require the
> result to be calculated in a local variable first.
>
> I think the best solut
On 5/5/19 2:34 AM, Mark Cave-Ayland wrote:
>>> EA = tcg_temp_new();\
>>> -xt = tcg_const_tl(xT(ctx->opcode)); \
>>> gen_set_access_type(ctx, ACCESS_INT); \
>>> gen_addr_register(ctx, EA);
... and remove the square brackets from "path" and "security_model",
since these parameters are not optional.
Buglink: https://bugs.launchpad.net/qemu/+bug/1581976
Signed-off-by: Thomas Huth
---
qemu-options.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-options.hx b
On 5/5/19 2:52 AM, Mark Cave-Ayland wrote:
> Right, it looks like VSX_CMP is the culprit here. Am I right in thinking that
> it's
> best to remove the opc parameter from GEN_VSX_HELPER_X3 above, and then have a
> separate gen and helper function for just the VSX_CMP instructions?
> Presumably thi
** Changed in: qemu
Importance: Undecided => Wishlist
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1583421
Title:
Please provide an option to print the default hardware configuration
as comma
Patchew URL: https://patchew.org/QEMU/20190430100802.15368-1-be...@igalia.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/
Which version of QEMU did you use here? Does it still reproduce with the
latest version of QEMU?
** Changed in: qemu
Status: New => Incomplete
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/146
On 5/5/19 2:57 AM, Mark Cave-Ayland wrote:
> For reference the culprits here is helper_xscvqpdp(). But again if you agree
> that it
> makes sense to create separate gen/helper functions then I can remove the
> opcode
> later on in the series.
Yes. Or indeed in a completely separate series.
r~
Philippe Mathieu-Daudé writes:
> Install optional dependencies of QEMU to get better coverage.
>
> The following components are now enabled:
>
> $ ./configure
> ...
> Multipath support yes
> VNC SASL support yes
> RDMA support yes
> PVRDMA supportyes
> libiscsi support
On 5/5/19 3:20 AM, Mark Cave-Ayland wrote:
>> The afrm argument is no longer used.
>> This also means that e.g.
>>
>> VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
>> VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
>>
>> are redundant. Similarly with all of the other pa
Hi Mark, Artyom.
On 5/5/19 12:46 PM, Mark Cave-Ayland wrote:
> On 04/05/2019 22:02, Artyom Tarasenko wrote:
>
>> AIX 5.1 expects the base year to be 1900. Adjust accordingly.
>>
>> Signed-off-by: Artyom Tarasenko
>> Reviewed-by: Hervé Poussineau
>> ---
>> hw/isa/i82378.c | 4 +++-
>> 1 file ch
Hi,
This series is to properly do the fix sent by Artyom here:
https://lists.gnu.org/archive/html/qemu-devel/2019-04/msg02264.html
There is no RTC on the i82378, move it to the board code,
set the base year there.
Regards,
Phil.
Artyom Tarasenko (1):
hw/ppc/40p: use 1900 as a base year
Phil
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/prep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index b7f459d4754..ebee3211480 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -601,7 +601,7 @@ static int prep_set_cmos_checksum(DeviceState
From: Artyom Tarasenko
AIX 5.1 expects the base year to be 1900. Adjust accordingly.
Signed-off-by: Artyom Tarasenko
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/prep.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 7a0d311d43c..
The MC146818 RTC was incorrectly added to the i82378 chipset in
commit a04ff940974a. In the next commit (506b7ddf8893) the PReP
machine use the i82378.
Since the MC146818 is specific to the PReP machine, move its use
there.
Fixes: a04ff940974a
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/i82
On Sat, 4 May 2019 at 06:26, Alistair Francis wrote:
> Ah, it seems like -device loader doesn't work, it looks like not
> setting the thumb register causes this core dump:
>
> qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1)
>
> R00=2000 R01=0574 R02=200015d0 R03=20
On Sun, 5 May 2019 at 08:02, Xiang Zheng wrote:
>
> Currently we fill the memory space with two 64MB NOR images when
> using persistent UEFI variables on virt board. Actually we only use
> a very small(non-zero) part of the memory while the rest significant
> large(zero) part of memory is wasted.
Paolo Bonzini writes:
> *** BLURB HERE ***
I assume there was going to be a bit more background here?
--
Alex Bennée
On 05/05/2019 15:31, Richard Henderson wrote:
> On 5/5/19 2:27 AM, Mark Cave-Ayland wrote:
>> I've spent a bit of time today going through the functions and it seems that
>> all
>> functions which have an xt parameter, minus a couple of the TEST macros,
>> require the
>> result to be calculated
On 5/4/19 1:36 AM, Sarah Harris wrote:
> This utility module builds a decision tree to decode instructions, starting
> from a human readable list of instruction bit patterns.
> Automatic tree generation will hopefully be more efficient and more
> maintainable than a hand-designed opcode parser.
>
On 05/05/2019 15:34, Richard Henderson wrote:
> On 5/5/19 2:34 AM, Mark Cave-Ayland wrote:
EA = tcg_temp_new();\
-xt = tcg_const_tl(xT(ctx->opcode)); \
gen_set_access_type(ctx, ACCESS_INT);
On 03/05/2019 18.15, Alex Bennée wrote:
>
> Thomas Huth writes:
>
>> On 03/05/2019 16.39, Alex Bennée wrote:
>>> This attempts to clean-up the output to better match the output of the
>>> rest of the QEMU check system. This includes:
>>>
>>> - formatting as " TESTiotest: nnn"
>>> - calc
On 05/05/2019 16:17, Richard Henderson wrote:
> On 5/5/19 3:20 AM, Mark Cave-Ayland wrote:
>>> The afrm argument is no longer used.
>>> This also means that e.g.
>>>
>>> VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
>>> VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
>>
On 5/4/19 1:36 AM, Sarah Harris wrote:
> Signed-off-by: Sarah Harris
...
>
> +AVR
> +M: Michael Rolnik
> +S: Odd Fixes
> +F: target-avr/
> +F: hw/avr/
> +
This is not how things work. Michael wasn't up to maintaining the code 2 years
ago; that's why it was never committed.
You would need to
On 5/5/19 8:49 AM, Mark Cave-Ayland wrote:
> Okay in that case I'll leave it as-is. So just to satisfy my curiosity here:
> is the
> problem here the mixing and matching of offsets and TCG globals, rather than
> the use
> of offsets as done for the VMX/VSX registers?
Correct.
r~
On 03/05/2019 16.39, Alex Bennée wrote:
> This attempts to clean-up the output to better match the output of the
> rest of the QEMU check system. This includes:
>
> - formatting as " TESTiotest: nnn"
> - calculating time diff at the end
> - only dumping config on failure
>
> Signed-off
On Sat, 04 May 2019 00:20:47 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > renesas_tmr: 8bit timer modules.
> > renesas_cmt: 16bit compare match timer modules.
> > This part use many renesas's CPU.
> > Hardware manual.
> > https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_
On Sat, 04 May 2019 00:38:38 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > rx62n - RX62N cpu.
> > rxqemu - QEMU virtual target.
> >
> > Signed-off-by: Yoshinori Sato
> > ---
> > include/hw/rx/rx.h| 7 ++
> > include/hw/rx/rx62n.h | 54
> > hw/rx/rx62n.c
On Sat, 04 May 2019 01:06:44 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > Signed-off-by: Yoshinori Sato
> > ---
> > target/rx/gdbstub.c | 112
> >
> > target/rx/monitor.c | 38
> > target/rx/Makefile.o
On Sat, 04 May 2019 03:43:23 +0900,
Richard Henderson wrote:
>
> On 5/2/19 7:33 AM, Yoshinori Sato wrote:
> > +/* conditional branch helper */
> > +static void rx_bcnd_main(DisasContext *ctx, int cd, int dst)
> > +{
> > +DisasCompare dc;
> > +TCGLabel *t, *done;
> > +
> > +switch (cd)
On Sat, 04 May 2019 00:27:29 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > Some RX peripheral using 8bit and 16bit registers.
> > Added 8bit and 16bit APIs.
>
> Doesn't this mean the build breaks at some point? Features used by other
> patches should be introduced first so the b
On Sat, 04 May 2019 01:11:48 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
> > Hello.
> > This patch series is added Renesas RX target emulation.
>
> I think the series is almost there - it's mostly just nits and clean
> build fixes to sort out now. If you run the branch through CI
On Sat, 04 May 2019 00:22:44 +0900,
Alex Bennée wrote:
>
>
> Yoshinori Sato writes:
>
>
> nit: typo in subject (serical->serial)
>
> > This module supported only non FIFO type.
> > Hardware manual.
> > https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
>
On 5/4/19 5:05 AM, Paolo Bonzini wrote:
> This backend is faster (100ns vs 150ns per switch on my laptop), but
> especially it will be possible to add CET support to it. Most of the
> code is actually not architecture specific.
>
> Signed-off-by: Paolo Bonzini
> ---
> configure
On 5/4/19 5:05 AM, Paolo Bonzini wrote:
> The speedup is similar to x86, 120 ns vs 180 ns on an APM Mustang.
>
> Signed-off-by: Paolo Bonzini
> ---
> configure| 2 +-
> scripts/qemugdb/coroutine_asm.py | 6 -
> util/Makefile.objs | 2 ++
> util/corout
On 5/4/19 5:05 AM, Paolo Bonzini wrote:
> + "bras %%r3, 1f\n"/* source PC will be after the BR */ \
> + "1: aghi %%r3, 12\n" /* 4 */ \
> + "stg %%r3, %[SCRATCH](%%r1)\n" /* 6 save switch-back PC */ \
> + "br %%r4\n"
On 5/4/19 5:05 AM, Paolo Bonzini wrote:
> Add endbr annotations before indirect branch targets. This lets QEMU enable
> IBT even for TCG-enabled builds.
>
> Signed-off-by: Paolo Bonzini
> ---
> Makefile.target | 2 ++
> configure | 9 +
> include/qemu/cpuid.h
All these devices do not contain any target-specific code. While
most of them are arch-specific, they are shared between different
targets of the same arch family (ARM and AArch64, MIPS32/MIPS64,
multiple endianess, ...).
Put them into common-obj-y to compile them once for all targets.
Signed-off-
Hi Thomas,
Thanks for the janitoring :)
On Sun, 5 May 2019 16:45:27 +0200
Thomas Huth wrote:
> ... and remove the square brackets from "path" and "security_model",
> since these parameters are not optional.
>
Well this is only true when fsdriver == local, but the other fs drivers,
ie. proxy
On 4/26/19 6:26 PM, Stephen Checkoway wrote:
> When erasing the chip, use the typical time specified in the CFI table
> rather than arbitrarily selecting 5 seconds.
>
> Since the currently unconfigurable value set in the table is 12, this
> means a chip erase takes 4096 ms so this isn't a big chan
The 'CFI01' NOR flash was introduced in commit 29133e9a0fff, with
timing modelled. One year later, the CFI02 model was introduced
(commit 05ee37ebf630) based on the CFI01 model. As noted in the
header, "It does not support timings". 12 years later, we never
had to model the device timings. Time to
The pflash device lacks a reset() function.
When a machine is resetted, the flash might be in an
inconsistent state, leading to unexpected behavior:
https://bugzilla.redhat.com/show_bug.cgi?id=1678713
Resolve this issue by adding a DeviceReset() handler.
Both CFI01/CFI02 devices are fixed by this
The pflash device is a child of TYPE_DEVICE, so it can implement
the DeviceReset handler. Actually it has to implement it, else
on machine reset it might stay in an incoherent state, as it has
been reported in the buglink listed below.
Add the DeviceReset handler and remove its call from the reali
The reset() code is used in various places, refactor it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 6dc04f156a7..073cd14978f 1
The reset() code is used in various places, refactor it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index f2c6201f813..f321b744
The pflash device is a child of TYPE_DEVICE, so it can implement
the DeviceReset handler. Actually it has to implement it, else
on machine reset it might stay in an incoherent state, as it has
been reported in the buglink listed below.
Add the DeviceReset handler and remove its call from the reali
** Patch added: "disas.patch"
https://bugs.launchpad.net/qemu/+bug/1774830/+attachment/5261663/+files/disas.patch
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1774830
Title:
qemu monitor disas
Hi Richard.
I can maintain it
Sent from my cell phone, please ignore typos
On Sun, May 5, 2019, 8:57 AM Richard Henderson
wrote:
> On 5/4/19 1:36 AM, Sarah Harris wrote:
> > Signed-off-by: Sarah Harris
> ...
> >
> > +AVR
> > +M: Michael Rolnik
> > +S: Odd Fixes
> > +F: target-avr/
> > +F: hw
Richard Henderson writes:
> On 5/3/19 8:27 AM, Alex Bennée wrote:
>>
>> Yoshinori Sato writes:
>>
>>> Some RX peripheral using 8bit and 16bit registers.
>>> Added 8bit and 16bit APIs.
>>
>> Doesn't this mean the build breaks at some point? Features used by other
>> patches should be introduced
Hi,
While reviewing Stephen Checkoway's v4 "Implement missing AMD
pflash functionality" [*] I found it hard (for me) to digest,
so I took step by step notes. This series is the result of
those notes.
Regarding Stephen's series, this series only contains the
generic code movement and trivial cleanu
Signed-off-by: Philippe Mathieu-Daudé
---
tests/pflash-cfi02-test.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c
index 40af1bb523e..ff775618c02 100644
--- a/tests/pflash-cfi02-test.c
+++ b/
Extract the code block in a new function, remove a goto statement.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, remove the XXX tracing
No change in functionality is intended with this commit.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-D
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block
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