Hi
On Wed, Feb 13, 2019 at 1:34 PM Philippe Mathieu-Daudé
wrote:
>
> The correct name is Wacom.
> Fix the typo which is present since 378af96155d.
>
> Reviewed-by: Marc-André Lureau
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> v2: Use correct English in description
thanks, I'll queue the pa
On Wed, 13 Feb 2019 15:13:08 +1100
David Gibson wrote:
> On Tue, Feb 12, 2019 at 07:25:25PM +0100, Greg Kurz wrote:
> > Hotplugging PHBs is a machine-level operation, but PHBs reside on the
> > main system bus, so we register spapr machine as the handler for the
> > main system bus.
> >
> > Prov
Hi
On Sat, Feb 2, 2019 at 12:09 PM Paolo Bonzini wrote:
>
> This will be needed by vhost-user-test, when each test switches to
> its own GMainLoop and GMainContext. Otherwise, for a reconnecting
> socket the initial connection will happen on the default GMainContext,
> and no one will be listeni
On Wed, 13 Feb 2019 10:25:07 +0100
David Hildenbrand wrote:
> On 12.02.19 19:25, Greg Kurz wrote:
> > Hotplugging PHBs is a machine-level operation, but PHBs reside on the
> > main system bus, so we register spapr machine as the handler for the
> > main system bus.
> >
> > Provide the usual pre-
Igor Mammedov writes:
> QEMU will crashes with
> qapi/qobject-output-visitor.c:210: qobject_output_complete: Assertion
> `qov->root && ((&qov->stack)->slh_first == ((void *)0))' failed
> when trying to get value of empty hostmem.host-nodes property.
>
> Fix it by calling visitor even if host-no
On Wed, Feb 13, 2019 at 09:56:38AM +0100, Philippe Mathieu-Daudé wrote:
>Hi Laurent,
>
>On 2/13/19 9:49 AM, Laurent Vivier wrote:
>> On 12/02/2019 06:34, Michael S. Tsirkin wrote:
>>> On Tue, Feb 12, 2019 at 01:22:24PM +0800, Wei Yang wrote:
On Wed, Jan 30, 2019 at 08:06:50AM +0800, Wei Yang w
From: Wei Xu
https://github.com/Whishay/qemu.git
Userspace and vhost-net backedn test has been done with upstream kernel
in guest.
v2->v3
v2/01 - drop it since the header has been synchronized from kernel.(mst &
jason)
v3/01 - rename 'avail_wrap_counter' to 'last_avail_wrap_counter',
From: Wei Xu
Redefine packed ring structure according to Qemu nomenclature.
Signed-off-by: Wei Xu
---
hw/virtio/virtio.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index a1ff647..eafb4cc 100644
--- a/hw/virtio/virtio.c
+++ b/hw/
From: Wei Xu
This is a helper for packed ring.
To support packed ring, the head descriptor in a chain should be updated
lastly since no 'avail_idx' like in packed ring to explicitly tell the
driver side that all payload is ready after having done the chain, so
the head is always visible immediat
From: Wei Xu
last_used_idx/wrap_counter should be equal to last_avail_idx/wrap_counter
after a successful flush.
Batching in vhost-net & dpdk testpmd is not equivalently supported in
userspace backend, but a chained descriptors for Rx is similarly presented
as a lightweight batch, so a write bar
On Wed, Feb 13, 2019 at 07:38:58AM -0500, Igor Mammedov wrote:
>cleanup file_backend_memory_alloc() by using one CONFIG_POSIX ifdef
>instead of several ones within the function to make it simpler to follow.
>
>Signed-off-by: Igor Mammedov
>Suggested-by: Wei Yang
Reviewed-by: Wei Yang
>---
>Cc:
From: Wei Xu
Set to 'true' by default due to spec.
Signed-off-by: Wei Xu
---
hw/virtio/virtio.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 1a98e61..54dc098 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1238,6 +1238,9 @@ v
From: Wei Xu
There is slight size difference between split/packed rings.
This is a refactor of split ring as well as a helper to expand
device and driver area size calculation for packed ring.
Signed-off-by: Wei Xu
---
hw/virtio/virtio.c | 16 ++--
1 file changed, 10 insertions(+)
From: Wei Xu
Initialize packed ring memory region with correct size and attribute.
Signed-off-by: Wei Xu
---
hw/virtio/virtio.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 6769e54..1a98e61 100644
--- a/hw/vir
From: Wei Xu
Difference between 'avail_wrap_counter' and 'last_avail_wrap_counter':
For Tx(guest transmitting), they are the same after each pop of a desc.
For Rx(guest receiving), they are also the same when there are enough
descriptors to carry the payload for a packet(e.g. usually 16 descs ar
From: Wei Xu
Add packed ring headcount check.
Common part of split/packed ring are kept.
Signed-off-by: Wei Xu
---
hw/virtio/virtio.c | 197 -
1 file changed, 179 insertions(+), 18 deletions(-)
diff --git a/hw/virtio/virtio.c b/hw/virtio/vi
From: Wei Xu
Add userspace and vhost kernel/user support.
Add CLI "ring_packed=true/false" to enable/disable packed ring provision.
Usage:
-device virtio-net-pci,netdev=xx,mac=xx:xx:xx:xx:xx:xx,ring_packed=false
By default it is provided.
Signed-off-by: Wei Xu
---
hw/net/vhost_net.c
From: Wei Xu
These are descriptor available and queue empty check helpers.
Signed-off-by: Wei Xu
---
hw/virtio/virtio.c | 56 +-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 54dc0
From: Wei Xu
Both userspace and vhost-net/user are supported with this patch.
A new subsection is introduced for packed ring, only 'last_avail_idx'
and 'last_avail_wrap_counter' are saved/loaded presumably based on
all the others relevant data(inuse, used/avail index and wrap count
should be the
On 2/4/19 5:26 AM, Cornelia Huck wrote:
On Tue, 29 Jan 2019 08:29:08 -0500
"Jason J. Herne" wrote:
Add bootindex property and iplb data for vfio-ccw devices. This allows us to
forward boot information into the bios for vfio-ccw devices.
Signed-off-by: Jason J. Herne
Acked-by: Halil Pasic
--
On 13/02/2019 09:56, Philippe Mathieu-Daudé wrote:
> Hi Laurent,
>
> On 2/13/19 9:49 AM, Laurent Vivier wrote:
>> On 12/02/2019 06:34, Michael S. Tsirkin wrote:
>>> On Tue, Feb 12, 2019 at 01:22:24PM +0800, Wei Yang wrote:
On Wed, Jan 30, 2019 at 08:06:50AM +0800, Wei Yang wrote:
> There
On 13/02/2019 14:09, Laurent Vivier wrote:
> Hi,
>
> this one is really a cut'n'paste but it introduces a problem with
> qemu-alpha, I don't know how/why:
>
> $ sudo unshare --ipc --uts --pid --fork --kill-child --mount chroot
> chroot/alpha/sid/
> Unsupported ioctl: cmd=0x80047476
>
> And
On Wed, Feb 13, 2019 at 3:03 PM Alex Bennée wrote:
>
>
> Thomas Huth writes:
>
> > On 2019-02-13 13:06, Marc-André Lureau wrote:
> >> Hi
> >>
> >> On Wed, Feb 13, 2019 at 12:55 PM Thomas Huth wrote:
> >>>
> >>> This is very convenient for people like me who store their QEMU git trees
> >>> on gi
Thomas Huth writes:
> On 2019-02-13 13:06, Marc-André Lureau wrote:
>> Hi
>>
>> On Wed, Feb 13, 2019 at 12:55 PM Thomas Huth wrote:
>>>
>>> This is very convenient for people like me who store their QEMU git trees
>>> on gitlab.com: Automatic CI pipelines are now run for each branch that is
>>
On 2019-02-13 11:46 AM, Kevin Wolf wrote:
> Reading from the backing file would be correct in your special case
> (because the overlay was only just created and doesn't contain data
> yet), but generally speaking, this would make the disk content
> inconsistent because it would mix newer data from
On 2/11/19 11:38 AM, Thomas Huth wrote:
On 2019-01-29 14:29, Jason J. Herne wrote:
We need a method for finding the subchannel of a dasd device. Let's
modify find_dev to handle this since it mostly does what we need. Up to
this point find_dev has been specific to only virtio devices.
Signed-off
On Wed, 19 Dec 2018 10:40:51 +0200
Bishara AbuHattoum wrote:
> Since Windows Server 2016, Microsoft stopped upgrading the major and minor
> versions of their new Windows Server product, so, the current functionality
> of checking major and minor version numbers to determine the Windows Server
> v
On Wed, Feb 13, 2019 at 08:25:35AM -0500, w...@redhat.com wrote:
> From: Wei Xu
>
> https://github.com/Whishay/qemu.git
>
> Userspace and vhost-net backedn test has been done with upstream kernel
> in guest.
Just a general comment: please format *all* patches
with --subject-prefix "PATCH v3",
On 13/02/19 10:49, Markus Armbruster wrote:
> * Define QAPI_COMMON_MODULES, QAPI_TARGET_MODULES and QAPI_MODULES in
> Makefile.obj
>
> * Add to util-obj-y in Makefile.obj
>
> * Add to obj-y in Makefile.target
Why can't both be in Makefile.objs, or in qapi/Makefile.objs?
Paolo
> No go, beca
We already forward the 3 bits correctly in the translation functions. We
also have to handle them properly and check for specification
exceptions.
Setting an invalid rounding mode (BFP only, all DFP rounding modes)
results in a specification exception. Setting unassigned bits in the
fpc, results i
Let's detect normal and denormal ("subnormal") numbers reliably. Also
test for quiet NaN's. As only one class is possible, test common cases
first.
While at it, use a better check to test for the mask bits in the data
class mask. The data class mask has 12 bits, whereby bit 0 is the
leftmost bit a
This series is based on the patches currently on the list:
- softfloat: Implement float128_to_uint32
- softfloat: add float128_is_{normal,denormal}
- s390x: add zPCI feature to "qemu" CPU model
For the KVM folks, only the last patch is of interest.
The floating-point extension facility seems to b
Let's use the proper conversion functions now that we have them.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c
index
We want to reuse that function in vector instruction context. While at it,
cleanup the code, using defines for magic values and avoiding the
handcrafted bit conversion.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 25 +
We want to reuse this in the context of vector instructions. So use
better matching names and introduce s390_restore_bfp_rounding_mode().
While at it, add proper newlines.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 112 ++
Many things are wrong and some parts cannot be fixed yet. Fix what we
can fix easily and add two FIXMEs:
The fpc flags are not updated in case an exception is actually injected.
Inexact exceptions have to be handled separately, as they are the only
exceptions that can coexist with underflows and o
With the floating-point extension facility
- CONVERT FROM LOGICAL
- CONVERT TO LOGICAL
- CONVERT TO FIXED
- CONVERT FROM FIXED
- LOAD FP INTEGER
have both, a rounding mode specification and the inexact-exception control
(XxC). Other instructions will be handled separatly.
Check for valid rounding
IEEE underflows are not reported when the mask bit is off and we don't
also have an inexact exception.
z14 PoP, 9-20, "IEEE Underflow":
An IEEE-underflow exception is recognized for an
IEEE target when the tininess condition exists and
either: (1) the IEEE-underflow mask bit in the FPC
With the floating-point extension facility, LOAD ROUNDED has
a rounding mode specification and the inexact-exception control (XxC).
Handle them just like e.g. LOAD FP INTEGER.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 23 +-
We can directly work on the uint64_t value, no need for a temporary
uint32_t value.
Also cleanup and shorten the comments.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-
Some instructions allow to suppress IEEE inexact exceptions.
z14 PoP, 9-23, "Suppression of Certain IEEE Exceptions"
IEEE-inexact-exception control (XxC): Bit 1 of
the M4 field is the XxC bit. If XxC is zero, recogni-
tion of IEEE-inexact exception is not suppressed;
if XxC is one,
The trap is triggered based on priority of the enabled signaling flags.
Only overflow and underflow allow a concurrent inexact exception.
z14 PoP, 9-33, Figure 9-21
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 13 +
1 file changed,
PoP describes "Round to nearest with ties away from 0" as
"The candidate nearest to the input value is selected. In case of a tie,
the candidate selected is the one that is larger in magnitude."
While float_round_ties_away is according to the introducing commit
f9288a76f181 ("softfloat: Add s
Let's split handling of BFP/DFP rounding mode configuration. Also,
let's not reuse the sfpc handler, use a separate handler so we can
properly check for specification exceptions for SRNMB.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 11 ++
The floating-point extension facility implemented certain changes to
BFP, HFP and DFP instructions.
As we don't implement HFP/DFP, we can ignore those completely. Related
to BFP, the changes include
- SET BFP ROUNDING MODE (SRNMB) instruction
- BFP-rounding-mode field in the FPC register is change
https://bugzilla.redhat.com/show_bug.cgi?id=1608226
On startup/link-up in multiqueue configuration the virtio-net
tries to starts all the queues, including those that the guest
will not enable by VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET.
If the guest driver does not allocate queues that it will not
use (for
On Wed, Feb 13, 2019 at 01:40:34PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/13/19 7:53 AM, Yuval Shaia wrote:
> > The function argument rdma_dev_res is not needed as it is stored in the
> > backend_dev object at init.
> >
> > Signed-off-by: Yuval Shaia
> > Reviewed-by: Marcel Apfelbaum
>
> Sh
On 2/4/19 5:57 AM, Cornelia Huck wrote:
On Tue, 29 Jan 2019 08:29:14 -0500
"Jason J. Herne" wrote:
Create a separate library for channel i/o related code. This decouples
channel i/o operations from virtio and allows us to make use of them for
the real dasd boot path.
Signed-off-by: Jason J. H
On Wed, 13 Feb 2019 08:41:43 -0500
"Jason J. Herne" wrote:
> On 2/4/19 5:26 AM, Cornelia Huck wrote:
> > On Tue, 29 Jan 2019 08:29:08 -0500
> > "Jason J. Herne" wrote:
> >> @@ -311,8 +312,12 @@ static CcwDevice *s390_get_ccw_device(DeviceState
> >> *dev_st)
> >> VirtioCcwDevice *virt
On 06/02/19 18:43, Marc-André Lureau wrote:
> Hi,
>
> Some chardev-related patches I have accumulated.
> Please review, thanks!
>
> v2:
> - rebased
> - update commit messages
>
> Marc-André Lureau (6):
> char: update the mux handlers in class callback
> char-fe: set_handlers() needs an assoc
From: Aleksandar Markovic
Add a header that contains wrappers around MSA instructions assembler
invocations. For now, only bit counting instructions (NLOC, NLZC, and
PCNT; each in four data format flavors) are supported.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/wrappers_ms
From: Aleksandar Markovic
v1->v2:
- added refference to the original commit in patch #1
- corrected copy-and-paste error in comments in 12 new source files
- renamed "bit_counting" subdirectory to "bit-counting"
- added wrappers and tests for MSA interleave instructions
This series begi
From: Aleksandar Markovic
The file tests/tcg/mips/include/test_inputs.h is planned to
contain various test inputs. For now, it contains 64 128-bit
pattern inputs (alternating groups od ones and zeroes) and
16 128-bit random inputs.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/
From: Aleksandar Markovic
Add wrappers for MSA interleave instructions.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/wrappers_msa.h | 39 +++
1 file changed, 39 insertions(+)
diff --git a/tests/tcg/mips/include/wrappers_msa.h
b/tests/tcg/mips/
From: Aleksandar Markovic
Remove a file that was added long time ago by mistake. The commit
that introduced this file was commit d70080c4 (from 2012).
Reviewed-by: Eric Blake
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mips64-dspr2/.directory | 2 --
1 file changed, 2 deletions(-)
From: Aleksandar Markovic
Add a header that contains test utilities. For now, it contains
only a function for checking and printing test results for bit
counting and similar MSA instructions.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/test_utils.h | 84 ++
From: Aleksandar Markovic
Add tests for MSA bit counting instructions. Each test consists of 80
test cases, so altogether there are 960 test cases.
Signed-off-by: Aleksandar Markovic
---
.../user/ase/msa/bit-counting/test_msa_nloc_b.c| 144 +
.../user/ase/msa/bit-counti
From: Aleksandar Markovic
Add tests for MSA interleave instructions. Each test consists of 80
test cases, so altogether there are 1280 test cases.
Signed-off-by: Aleksandar Markovic
---
.../user/ase/msa/interleave/test_msa_ilvev_b.c | 153 +
.../user/ase/msa/interleave/
On Wed, 13 Feb 2019 01:06:41 PST (-0800), Bastian Koppelmann wrote:
On 2/13/19 3:15 AM, Palmer Dabbelt wrote:
On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt wrote:
[snip]
Do you, by any chance, have a v7? It looks like there's quite a few merge
conflicts here, and while I'm OK fixing them
On 2/13/19 6:40 AM, Philippe Mathieu-Daudé wrote:
> On 2/13/19 7:53 AM, Yuval Shaia wrote:
>> The function argument rdma_dev_res is not needed as it is stored in the
>> backend_dev object at init.
>>
>> Signed-off-by: Yuval Shaia
>> Reviewed-by: Marcel Apfelbaum
>
> Should we teach checkpatch.pl
On 13/02/19 08:45, Markus Armbruster wrote:
> * If it doesn't, "default" / "imply" supply the value if condition is
> met
>
> * What about contradictions between "default" / "imply"?
We would avoid those by forbidding "default n", then "imply" would also
be just another "default y". I'm quite
From: Richard Henderson
Signed-off-by: Michael Clark
Reviewed-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/tar
From: Michael Clark
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
-
merged tag 'pull-tcg-20190211'
Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
The following changes since commit 22c5f446514a2a4bb0dbe1fea26713da92fc85fa:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190211' into
staging (2019-02-11 17:04:57 +)
are
From: Alistair Francis
The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 7 +--
1 file changed, 5 insertions(+),
From: Xi Wang
Access to a counter in U-mode is permitted only if the corresponding
bit is set in both mcounteren and scounteren. The current code
ignores mcounteren and checks scounteren only for U-mode access.
Signed-off-by: Xi Wang
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
From: Michael Clark
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Co-authored-by: Matthew Suozzo
Co-authored-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c |
From: Richard Henderson
Modifed from Richard Henderson's patch [1] to integrate
with the new control and status register implementation.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html
Note: the f* CSRs already mark mstatus.FS dirty using
env->mstatus |= mstatus.FS so
From: Michael Clark
* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
and rename cpu_riscv_init to riscv_cpu_init
From: Alistair Francis
Cast the kernel start address to the target bit length.
This ensures that we calculate the initrd offset to a valid address for
the architecture.
Steps to reproduce the original problem (reported by Alex):
Build U-Boot for the virt machine for riscv32. Then run it with
From: Michael Clark
Add misa checks for M, A, F and D extensions and if they are
not present generate illegal instructions. This improves
emulation accurary for harts with a limited set of extensions.
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Michael is no longer employed by SiFive and does not want to continue
maintianing the RISC-V port.
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a2da141a928f..e170a4c73376 100644
--- a/MAINTAINERS
+++ b/MAINTAINER
From: Michael Clark
This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing
I noticed the qemu-iotests 200 was failing due to the commit
"703fef6fcf3 : s390x/pci: Warn when adding PCI devices without the
'zpci' feature".
This patch fixes the failure :).
Thanks
Farhan
On 02/12/2019 06:23 AM, David Hildenbrand wrote:
As we now always have PCI support, let's add it to
On 12.02.19 22:21, Marc Olson wrote:
> On 1/11/19 7:00 AM, Max Reitz wrote:
>> On 12.11.18 08:06, Marc Olson wrote:
[...]
>>> diff --git a/qapi/block-core.json b/qapi/block-core.json
>>> index d4fe710..72f7861 100644
>>> --- a/qapi/block-core.json
>>> +++ b/qapi/block-core.json
>>> @@ -3057,6 +30
From: Bastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans/trans_rvi.inc.c | 49 ++
Patchew URL:
https://patchew.org/QEMU/1549945516-25643-1-git-send-email-changpeng@intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1549945516-25643-1-git-send-email-changpeng@intel.com
Subject: [Qemu-d
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19 +++
target/riscv/translate.c
Palmer: I caused some merge conflicts in Bastian's patch set so I
figured I'd attempt to clean these up. As far as I'm concerned v6 was
good to go, but since the merge conflicts were fairly extensive (if
somewhat mechanical) I'd like to pass the baton back to Bastian here for
at least a sanity che
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/riscv/translate.
It's either "GNU *Library* General Public License version 2" or "GNU
Lesser General Public License version *2.1*", but there was no "version
2.0" of the "Lesser" license. So assume that version 2.1 is meant here.
Signed-off-by: Thomas Huth
---
crypto/block-luks.c | 2 +-
crypto/block-l
From: Bastian Koppelmann
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 58 -
2 files changed, 63 ins
From: Bastian Koppelmann
it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them
reuse the code generator used for the non compressed insns.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn16-32.decode | 7 +
target/riscv/in
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 149
target/riscv/translate
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58 ++
target/riscv/translate.c
From: Bastian Koppelmann
only one translate functions of rvc needs to handle special cases. For
the other rvc insns we can remove the extra layer of indirection.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn16.decode | 37 +
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv/insn_trans/trans_rvm.inc.c | 10
From: Bastian Koppelmann
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 21 +
1 file changed, 1 insertion(+), 20 de
From: Bastian Koppelmann
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Pee
From: Bastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +-
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
target/riscv/translate.c| 4 ++--
3 files changed, 18 ins
From: Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 46 +---
target/riscv/t
From: Bastian Koppelmann
These all expand simply to R format instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/riscv/Makefile.objs | 10 +++---
target/riscv/insn16-64.decode | 24 ++
target/riscv/insn16.decode
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvi.inc.c | 48 +
2 files changed, 58
From: Bastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 93 +
target/riscv/translate.c| 59 +---
2 files changed, 81 insertions(+), 71
From: Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +-
target/ris
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 27 +
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