This can avoid setting a negative value to
etc/boot-fail-wait.
Signed-off-by: Li Qiang
---
hw/nvram/fw_cfg.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index f4a52d8..276dcb1 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/n
On 2018-09-03 05:38, Zhang Chen wrote:
> Make sure master start block replication after slave's block
> replication started.
>
> Besides, we need to activate VM's blocks before goes into
> COLO state.
>
> Signed-off-by: zhanghailiang
> Signed-off-by: Li Zhijian
> Signed-off-by: Zhang Chen
> Si
On Wed, Oct 24, 2018 at 3:21 PM Thomas Huth wrote:
> On 2018-09-03 05:38, Zhang Chen wrote:
> > Make sure master start block replication after slave's block
> > replication started.
> >
> > Besides, we need to activate VM's blocks before goes into
> > COLO state.
> >
> > Signed-off-by: zhanghaili
We will never get the canonical path from the object
before object_property_add_child.
Signed-off-by: Zhang Yi
---
backends/hostmem-file.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c
index 639c8d4..9691c48
On 10/23/18 9:37 PM, Fredrik Noring wrote:
> Hi Peter, Aleksandar,
>
>> Hi: I get compile errors on 32-bit hosts:
>>
>> /home/petmay01/qemu-for-merges/disas/mips.c:615:35: error: large
>> integer implicitly truncated to unsigned type [-Werror=overflow]
>> #define INSN_5900 0x1
The latest thread for supporting DISCARD and WRITE ZEROES feature for
virtio-blk is here:
virtio_blk: add discard and write zeroes support
https://lists.linuxfoundation.org/pipermail/virtualization/2018-October/039534.html
I don't take further more steps about it, please go ahead and make the
s
We are missing the VIRT_COMPAT_3_0 definition and setting.
Let's add them.
Signed-off-by: Eric Auger
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9f677825f9..a2b8d8f7c2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1871,6 +187
Hi Greg,
On 10/22/18 4:39 PM, Greg Kurz wrote:
> On Fri, 21 Sep 2018 10:17:58 +0200
> Eric Auger wrote:
>
>> To prepare for testing yet another extension, let's
>> refactor the code. We introduce vfio_iommu_get_type()
>> helper which selects the richest API (v2 first). Then
>> vfio_init_container
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
@@ -338,27 +375,63 @@ static bool trans_and(DisasContext *ctx, arg_and *a,
uint32_t insn)
static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
{
-gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
-return
On 10/23/18 2:04 PM, Richard Henderson wrote:
This primarily solves the case for RVC that several insns are
completely different, decode and all, between the two. But it
also means that we need less ifdefing for RV{I,M,A,F,D}.
---
target/riscv/insn_trans/trans_rva.inc.c | 46 +---
Various shell files contain a mix between obsolete ``
and modern $(); It would be nice to convert to using
$() everywhere.
Cc: kw...@redhat.com
Cc: mre...@redhat.com
Cc: ebl...@redhat.com
Suggested-by: Eric Blake
Signed-off-by: Mao Zhongyi
---
tests/qemu-iotests/check | 60
POSIX requires $PWD to be reliable, and we expect all
shells used by qemu scripts to be relatively close to
POSIX. Thus, it is smarter to avoid forking the pwd
executable for something that is already available in
the environment.
In addtion, clean up unused variable here and use $()
to instead
run
git grep '\$here' tests/qemu-iotests
has 0 hits, which means we are setting a variable that
no use, so execute the following cmd to remove all of
the 'here=...' lines as dead code.
sed -i '/here=/d' $(git grep -l 'here=' tests/qemu-iotests)
Cc: kw...@redhat.com
Cc: mre...@redhat.com
Cc: ebl.
s/armbru/tags/pull-error-2018-10-22' into
staging (2018-10-23 17:20:23 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20181024
for you to fetch changes up to 93f379b0c43617b1361f742f261479eaed4959cb:
target/arm:
POSIX requires $PWD to be reliable, and we expect all
shells used by qemu scripts to be relatively close to
POSIX. Thus, it is smarter to avoid forking the pwd
executable for something that is already available in
the environment.
So replac it with the following:
sed -i 's/`pwd`/$PWD/g' $(git gr
On 10/24/18 10:33 AM, Bastian Koppelmann wrote:
> On 10/23/18 2:04 PM, Richard Henderson wrote:
> Either this or one of the last two patches breaks booting fedora. I couldn't
> figure the problem out just yet.
I didn't do any testing on it, and may well have messed something up in the
process. (I
The null-machine code used to be target specific since it used the
target-specific cpu_init() function in the past. But in the recent
commit 2278b93941d42c30e2950 ("Use cpu_create(type) instead of
cpu_init(cpu_model)") this has been change, so that the code now
uses the common cpu_create() function
Hi Peter,
the following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into
staging (2018-10-23 17:20:23 +0100)
are available in the git repository at:
https://gitlab.com/huth/qemu.git tags/pull-reque
From: Mao Zhongyi
Various shell files contain a mix between obsolete ``
and modern $(); It would be nice to convert to using $()
everywhere.
Signed-off-by: Mao Zhongyi
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Signed-off-by: Thomas Huth
---
tests/docker/dockerfiles/debian-bootstrap.pr
The migration test for s390x sometimes hangs when running with TCG,
similar to the problems that we have already observed with TCG for
the ppc64 guests. Thus disable the s390x test when we are not running
with KVM for now until the problem with TCG has been resolved.
Reviewed-by: Laurent Vivier
R
This device is not user-creatable and currently only used for the
"alpha" target. So if the user does not want to compile alpha-softmmu,
we should also not compile this device. Add a proper config switch to
be able to compile this more flexibly.
Reviewed-by: Peter Maydell
Signed-off-by: Thomas Hu
From: Liam Merwick
The configure script detects if the compiler has AVX2 support and
automatically sets avx2_opt="yes" which in turn defines CONFIG_AVX2_OPT.
There is no way of explicitly overriding this setting so this commit adds
two command-line options: --enable-avx2 and --disable-avx2.
The
From: Mao Zhongyi
Various shell files contain a mix between obsolete ``
and modern $(); It would be nice to convert to using $()
everywhere.
Signed-off-by: Mao Zhongyi
Reviewed-by: Thomas Huth
Signed-off-by: Thomas Huth
---
po/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
Hi, Eric
On 10/23/18 4:21 PM, Eric Blake wrote:
On 10/22/18 2:48 PM, Mao Zhongyi wrote:
The subject line says "what", but the commit body should say "why". My
suggestion:
POSIX requires $PWD to be reliable, and we expect all shells used by
qemu scripts to be relatively close to POSIX. Thu
wrote:
> From: Manish Jaggi
>
> This option is user opt-in. hostinvariant will replace guest's invariant
> registers with hosts.
>
> Signed-off-by: Manish Jaggi
Reviewed-by: Juan Quintela
As I said in previous discussions, I still think that you should create
a better cpu model. But as there
On Mon, Oct 15, 2018 at 12:47:23PM +0800, Robert Hoo wrote:
> Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
> Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
>
> Signed-off-by: Robert Hoo
Reviewed-by: Eduardo Habkost
--
Eduardo
On Mon, Oct 15, 2018 at 12:47:24PM +0800, Robert Hoo wrote:
> Add FeatureWordType indicator in struct FeatureWordInfo.
> Change feature_word_info[] accordingly.
> Change existing functions that refer to feature_word_info[] accordingly.
>
> Signed-off-by: Robert Hoo
> ---
> target/i386/cpu.c | 18
On Mon, Oct 15, 2018 at 12:47:25PM +0800, Robert Hoo wrote:
> Note RSBA is specially treated -- no matter host support it or not, qemu
> pretends it is supported.
>
> Signed-off-by: Robert Hoo
I am now wondering what else we need to be able to remove
CPUID_7_0_EDX_ARCH_CAPABILITIES from
feature_
On Mon, Oct 15, 2018 at 12:47:24PM +0800, Robert Hoo wrote:
> Add FeatureWordType indicator in struct FeatureWordInfo.
> Change feature_word_info[] accordingly.
> Change existing functions that refer to feature_word_info[] accordingly.
>
> Signed-off-by: Robert Hoo
> ---
> target/i386/cpu.c | 18
We don't use CONFIG_PARALLEL_ISA in any of our Makefiles, so this
is just a dead config option which can be removed.
Fixes: a4cb773928e047b137c6998209cf2eec857fac6b
Signed-off-by: Thomas Huth
---
default-configs/alpha-softmmu.mak | 1 -
1 file changed, 1 deletion(-)
diff --git a/default-configs
This series reworks some pci hotplug handlers (except for s390, that will
require more work but is not required for now).
1. Route all unplug calls via the hotplug handler when called from the
unplug_request handler. This will be required to get multi-stage
hotplug handlers running, but also
Perform the check in the pre_plug handler. In addition, we need the
capability only if the device is actually hotplugged (and not created
during machine initialization). This is a preparation for coldplugging
devices via that hotplug handler.
Signed-off-by: David Hildenbrand
---
hw/acpi/pcihp.c
Preparation for multi-stage hotplug handlers.
Signed-off-by: David Hildenbrand
---
hw/ppc/spapr_pci.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 58afa46204..64b8591023 100644
--- a/hw/ppc/s
Preparation for multi-stage hotplug handlers.
Signed-off-by: David Hildenbrand
---
hw/acpi/pcihp.c | 11 ++-
hw/acpi/piix4.c | 7 +--
include/hw/acpi/pcihp.h | 3 +++
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
i
For now, the hotplug handler is not called for devices that are
being cold plugged. The hotplug handler is setup when the machine
initialization is fully done. Only bridges that were cold plugged are
considered.
Set the hotplug handler for the root piix bus directly when realizing.
Overwrite the h
Preparation for multi-stage hotplug handlers.
Signed-off-by: David Hildenbrand
---
hw/pci/pcie.c | 10 +-
hw/pci/pcie_port.c| 1 +
include/hw/pci/pcie.h | 2 ++
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 02a7bf3af5..74
Preparation for multi-stage hotplug handlers.
Signed-off-by: David Hildenbrand
---
hw/pci-bridge/pci_bridge_dev.c | 14 ++
hw/pci-bridge/pcie_pci_bridge.c | 14 ++
hw/pci/shpc.c | 11 ++-
include/hw/pci/shpc.h | 2 ++
4 files changed,
Move the checks to the pre_plug handler. I don't see a reason to check
for the PCI slot when unplugging.
Signed-off-by: David Hildenbrand
---
hw/pci-bridge/pci_bridge_dev.c | 11 --
hw/pci-bridge/pcie_pci_bridge.c | 11 --
hw/pci/shpc.c | 36 ++-
Increase the size of 'membership' holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.
(This change is related to f9c9cd63e3),
Signed-off-by: Philippe Mathieu-Daudé
---
disas/mips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 23/10/18 23:35, Eric Blake wrote:
A quick coredump on an incomplete command line:
./x86_64-softmmu/qemu-system-x86_64 -mon mode=control,pretty=on
#0 0x7723d9e4 in g_str_hash () at /lib64/libglib-2.0.so.0
#1 0x7723ce38 in g_hash_table_lookup () at /lib64/libglib-2.0.so.0
On 10/24/18 11:18 AM, Thomas Huth wrote:
> We don't use CONFIG_PARALLEL_ISA in any of our Makefiles, so this
> is just a dead config option which can be removed.
>
> Fixes: a4cb773928e047b137c6998209cf2eec857fac6b
> Signed-off-by: Thomas Huth
> ---
> default-configs/alpha-softmmu.mak | 1 -
> 1
On 10/24/18 11:57 AM, Philippe Mathieu-Daudé wrote:
> Increase the size of 'membership' holder size to 64 bits. This is
> needed for future extensions since existing bits are almost all used.
> (This change is related to f9c9cd63e3),
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> disas/mips.c
On 10/24/18 09:11, Li Qiang wrote:
> This can avoid setting a negative value to
> etc/boot-fail-wait.
>
> Signed-off-by: Li Qiang
> ---
> hw/nvram/fw_cfg.c | 15 ++-
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
> index f4a
On 24/10/2018 03:38, Max Filippov wrote:
> Stack pointer alignment code incorrectly adds stack_size to sp instead
> of subtracting it. It also does not take flat_argvp_envp_on_stack() into
> account when calculating stack_size. This results in initial stack
> pointer misalignment with certain set o
On Tue, Oct 23, 2018 at 10:35:59PM +0100, Eric Blake wrote:
> A quick coredump on an incomplete command line:
> ./x86_64-softmmu/qemu-system-x86_64 -mon mode=control,pretty=on
>
> #0 0x7723d9e4 in g_str_hash () at /lib64/libglib-2.0.so.0
> #1 0x7723ce38 in g_hash_table_lookup (
On 10/24/18 07:12, Li Qiang wrote:
> Also remove unnecessary 'res' variable.
>
> Signed-off-by: Li Qiang
> ---
> hw/nvram/fw_cfg.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
> index 946f765..f4a52d8 100644
> --- a/hw/nvr
On Wed, Oct 24, 2018 at 07:21:17AM +0100, Peter Maydell wrote:
> > dtc | 2 +-
>
> Hi. This pull request seems to include an accidental update
> to the dtc submodule. It's in the "intel_iommu: move ce fetching out
> when sync shadow" commit, and it's not mentione
On Wed, Oct 24, 2018 at 10:56:02AM +0200, Eric Auger wrote:
> We are missing the VIRT_COMPAT_3_0 definition and setting.
> Let's add them.
>
> Signed-off-by: Eric Auger
> ---
> hw/arm/virt.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 9f677
Assert that the value to be written is the correct size.
No change in functionality here, just mirroring the same
function from kvm64.
Signed-off-by: Richard Henderson
---
target/arm/kvm32.c | 41 -
1 file changed, 16 insertions(+), 25 deletions(-)
diff -
Signed-off-by: Richard Henderson
---
target/arm/kvm32.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index da08f7aab8..f23cc77d9e 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -44,7 +44
Signed-off-by: Richard Henderson
---
target/arm/kvm64.c | 63 --
1 file changed, 61 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 5de8ff0ac5..6ed80eadc2 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
The ID registers are replacing (some of) the feature bits.
We need (some of) these values to determine the set of data
to be handled during migration.
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 1 +
target/arm/kvm.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/targe
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 +-
linux-user/elfload.c | 2 +-
target/arm/cpu.c | 4
target/arm/helper.c | 2 +-
target/arm/kvm32.c | 3 ---
target/arm/machine.c | 3 +--
6 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/target/arm/cpu
My previous patch set for replacing feature bits with id registers
failed to consider that these id registers are beginning to control
migration, and thus we must fill them in for KVM as well.
Thus, we want to initialize these values within CPU from the host.
Finally, re-send the T32EE conversion
On 21/10/2018 17:55, Max Filippov wrote:
> bFLT format header doesn't have enough information to register a handler
> for a specific architecture. Add switch -f / --flat that registers one
> of the qemu binaries as a handler for bFLT executable images.
>
> Signed-off-by: Max Filippov
> ---
> Chan
From: Craig Janeczek
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.
Reviewed-by: Richard Henderson
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar M
From: Aleksandar Markovic
This patch set begins to add MXU ASE instruction support.
v6->v7:
- move MXU_EN check to the main MXU decoding function
- amend MXU ASE overview note
v5->v6:
- added bit definitions for 'aptn1' and 'eptn2'.
- pool04 eliminated, since it is covered by a singl
From: Aleksandar Markovic
Provide the placeholder and add the invocation logic for MXU
decoding engine.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fefe9ac..12
From: Aleksandar Markovic
Add MXU decoding engine: add handlers for all instruction pools,
and main decode handler. The handlers, for now, for the purpose
of this patch, contain only sceleton in the form of a single
switch statement.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate
From: Aleksandar Markovic
Add bit encoding for MXU accumulate add/subtract 1-bit pattern
'aptn1'.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ed72b32..f274ac1 10
From: Craig Janeczek
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/mips-defs.h | 1
From: Aleksandar Markovic
Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 142 +---
From: Craig Janeczek
Add bit encoding for MXU operand getting pattern 'optn2'.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 665a584
From: Craig Janeczek
Add bit encoding for MXU accumulate add/subtract 2-bit pattern
'aptn2'.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
From: Aleksandar Markovic
Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 41 +++--
1 file changed, 23 insertions(+), 18
From: Aleksandar Markovic
Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 97fb2e0..665a584 10064
From: Craig Janeczek
Add support for emulating the S8LDD MXU instruction.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 90 +++--
1 file changed, 87 insertions(+), 3 deletions(-)
diff --git a/target/
From: Craig Janeczek
Add support for emulating the D16MAC MXU instruction.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 90 +++--
1 file changed, 87 insertions(+), 3 deletions(-)
diff --git a/target
From: Craig Janeczek
Add bit encoding for MXU operand getting pattern 'optn3'.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f
From: Craig Janeczek
Add support for emulating the S32LDD and S32LDDR MXU instructions.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 54 ++---
1 file changed, 47 insertions(+), 7 deletions(-)
diff -
From: Craig Janeczek
Add emulation of non-MXU MULL within MXU decoding engine.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/
From: Aleksandar Markovic
Add prefix, suffix, operation descriptions, and other corrections
and amendments to the comment that describes MXU ASE.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 84 +++--
1 file changed, 74 insertions
From: Craig Janeczek
Add support for emulating the S32I2M and S32M2I MXU instructions.
This commit also contains utility functions for reading/writing
to MXU registers. This is required for overall MXU instruction
support.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
t
From: Craig Janeczek
Adds support for emulating the Q8MUL and Q8MULSU MXU instructions.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 101
1 file changed, 94 insertions(+), 7 deletions(-)
diff -
From: Craig Janeczek
Add support for emulating the D16MUL MXU instruction.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 66 ++---
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/target
From: Aleksandar Markovic
Move MXU_EN check to the main MXU decoding function, to avoid code
repetition.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 509 ++--
1 file changed, 238 insertions(+), 271 deletions(-)
diff --git a/targ
Hi，everybody。
Now I have installed QEMU3.0.0. I want to launch wine by QEMU. But I can't find
qemu-runtime-i386-XXX.tar.gz and qemu-XXX-i386-wine.tar.gz on the QEMU web page.
Please tell me how I can get them and use the wine by QEMU? Thank you very
much.
On 10/24/18 12:37 PM, Richard Henderson wrote:
> -int i, ret, fdarray[3];
> +int i, err = 0, fdarray[3];
Bah. The bit about having compile-tested for arm32 was fake news -- "i" is now
unused. Ho hum.
> @@ -77,16 +69,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
> *ahcf)
>
On Wed, 24 Oct 2018 12:19:30 +0200
David Hildenbrand wrote:
> Preparation for multi-stage hotplug handlers.
>
> Signed-off-by: David Hildenbrand
> ---
Reviewed-by: Greg Kurz
> hw/ppc/spapr_pci.c | 33 +
> 1 file changed, 21 insertions(+), 12 deletions(-)
>
>
** Tags added: tcg x86
--
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https://bugs.launchpad.net/bugs/1759333
Title:
Illegal Instruction with HVF when encountering SSE instructions in the
emulator
Status in QEMU:
New
Bug des
On 16.10.18 15:56, Igor Mammedov wrote:
> On Tue, 16 Oct 2018 15:33:40 +0200
> Igor Mammedov wrote:
>
>> When [2] was fixed it was agreed that adding and calling post_plug()
>> callback after device_reset() was low risk approach to hotfix issue
>> right before release. So it was merged instead of
'Setup' section of https://wiki.qemu.org/Features/HelperNetworking says
that setuid attribute needs to be turned on for 'qemu-bridge-helper'
binary, but it forgets to mention that owner of this file must be root
user. Otherwise, setuid bit makes no sense.
Looks like in most scenarios this binary al
On 10/23/2018 6:31 PM, Paolo Bonzini wrote:
On 24/10/2018 00:11, George Kennedy wrote:
What about "req->hba_private != s->current"? That should cause a call
to lsi_queue_req, and then you can check s->want_resel in lsi_queue_req.
For the extended period of time where lsi_queue_req() is not
From: Aleksandar Markovic
The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into
staging (2018-10-23 17:20:23 +0100)
are available in the git repository at:
https://github.com/AMarkovic/qem
From: Fredrik Noring
The R5900 implements the 64-bit MIPS III instruction set except
DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV
instructions MOVN, MOVZ and PREF are implemented. It has the
R5900-specific three-operand instructions MADD, MADDU, MULT and
MULTU as well as pipeline
From: Fredrik Noring
Define MMI0, MMI1, MMI2, MMI3 subclass opcodes, and other opcodes of
instructions in MMI class.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 51
From: Fredrik Noring
Define MMI class, LQ, and SQ R5900 opdoces.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 40
1 file changed, 40 insertions(+)
diff --git a/target/
From: Fredrik Noring
Add placeholder for SQ instruction, handle RDHWR.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 53 -
1 file changed, 52 insertions(+), 1 del
From: Fredrik Noring
Add a test for DIVU1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/divu1.c | 48 +++
2 files changed, 49 inser
From: Fredrik Noring
The three-operand MULT and MULTU are the only R5900-specific
instructions emitted by GCC 7.3. The R5900 also implements the three-
operand MADD and MADDU instructions, but they are omitted in QEMU for
now since they are absent in programs compiled by current GCC versions.
Li
From: Fredrik Noring
Add a comment on R5900 MMI ASE (short overview).
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 161
1 file changed, 161 insertions(+)
diff
From: Fredrik Noring
Add a placeholder for MMI class. This is the main palceholder for
MMI ASE.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 45 -
1 file changed, 44
From: Fredrik Noring
Add a test for MULT1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mipsr5900/mult.c | 45 +
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/test
From: Fredrik Noring
Add a placeholder for MM1 subclass.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/targ
From: Fredrik Noring
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 44
1 file changed, 44 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.
From: Fredrik Noring
Add support for MULT1 and MULTU1 instructions.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/target/mips
From: Fredrik Noring
Add a test for MFLO1 and MFHI1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mipsr5900/Makefile | 3 ++-
tests/tcg/mips/mipsr5900/mflohi1.c | 35 +++
2 files changed
From: Fredrik Noring
Add a placeholder for MMI2 subclass.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a
From: Fredrik Noring
Add a placeholder for MMI0 subclass.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 43 ++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --gi
From: Fredrik Noring
Add support for MFLO1, MTLO1, MFHI1 and MTHI1 instructions.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Fredrik Noring
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff
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