On Fri, 08/17 19:02, Kevin Wolf wrote:
> All callers in QEMU proper hold the AioContext lock when calling
> job_finish_sync(). The tests should do the same.
>
> Signed-off-by: Kevin Wolf
A similar patch is needed for job_finalize() too, I think.
Fam
> ---
> include/qemu/job.h | 6 ++
On Fri, 08/17 19:02, Kevin Wolf wrote:
> Simimlar to AIO_WAIT_WHILE(), job_finish_sync() needs to release the
> AioContext lock of the job before calling aio_poll(). Otherwise,
> callbacks called by aio_poll() would possibly take the lock a second
> time and run into a deadlock with a nested AIO_WA
On Fri, 08/17 19:02, Kevin Wolf wrote:
> Simimlar to AIO_WAIT_WHILE(), bdrv_drain_poll_top_level() needs to
> release the AioContext lock of the node to be drained before calling
> aio_poll(). Otherwise, callbacks called by aio_poll() would possibly
> take the lock a second time and run into a dead
From: Daniel P. Berrangé
Per supported platforms doc[1], the various min GTK3 on relevant distros is:
RHEL-7.0: 3.8.8
RHEL-7.2: 3.14.13
RHEL-7.4: 3.22.10
RHEL-7.5: 3.22.26
Debian (Stretch): 3.22.11
Debian (Jessie): 3.14.5
OpenBSD (Ports): 3.22.30
FreeBSD (Ports): 3.22.29
OpenSU
From: Daniel P. Berrangé
SDL1.2 was deprecated in the 2.12.0 release with:
commit e52c6ba34149b4f39c3fd60e59ee32b809db2bfa
Author: Daniel P. Berrange
Date: Mon Jan 15 14:25:33 2018 +
ui: deprecate use of SDL 1.2 in favour of 2.0 series
The SDL 2.0 release was made in Aug,
The following changes since commit 5ccac548faf041ff5229a8e8342e3be14a34c8af:
Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into
staging (2018-08-23 17:35:48 +0100)
are available in the git repository at:
git://git.kraxel.org/qemu tags/ui2-20180824-pull-re
From: Daniel P. Berrangé
GTK2 was deprecated in the 2.12.0 release with:
commit b7715af2b31f47060cc5b4be930d16c13be93fa9
Author: Daniel P. Berrange
Date: Tue Dec 12 11:34:40 2017 +
ui: deprecate use of GTK 2.x in favour of 3.x series
The GTK 3.0 release was made in Feb, 20
Marc-André Lureau writes:
> This is mostly for readability of the code. Let's make it clear which
> callers can create an implicit monitor when the chardev is muxed.
>
> This will also enforce a safer behaviour, as we don't really support
> creating monitor anywhere/anytime at the moment.
>
> The
Marc-André Lureau writes:
> Some time ago, I proposed to use an (eval) in .dir-locals.el to set
> the mode for all json files and Makefile. Unfortunately, this isn't
> safe, and emacs will prompt the user, which isn't very friendly.
>
> Fortunately, editorconfig provides a special config key whic
On Thu, Aug 23, 2018 at 02:34:31PM +0200, Igor Mammedov wrote:
> On Thu, 23 Aug 2018 17:01:33 +0800
> Yu Zhang wrote:
>
> > On 8/23/2018 2:01 AM, Eduardo Habkost wrote:
> > > On Wed, Aug 22, 2018 at 03:05:36PM +0200, Igor Mammedov wrote:
> > >> On Wed, 22 Aug 2018 12:06:26 +0200
> > >> Laszlo E
On Thu, 23 Aug 2018 14:25:01 -0300
Eduardo Habkost wrote:
> On Thu, Aug 23, 2018 at 10:14:06AM +0200, Igor Mammedov wrote:
> > On Wed, 22 Aug 2018 15:01:12 -0300
> > Eduardo Habkost wrote:
> [...]
> > > However, have you considered keeping adding separate entries for
> > > NVDIMM devices only
Marc-André Lureau writes:
> Add a new function qdict_steal(), that deletes a key from a dict, and
> returns the associated value, if any. Simplify related code.
>
> Signed-off-by: Marc-André Lureau
> ---
> include/qapi/qmp/qdict.h | 1 +
> monitor.c| 3 +--
> qobject/block-qdi
Marc-André Lureau writes:
> While it may be convenient to accept NULL value in
> qobject_unref() (for similar reasons as free() accepts NULL), it is
> not such a good idea for qobject_ref(): now assert() on NULL.
Why is it not such a good idea?
Is it unsafe? Unclean? Ugly?
If unsafe, can you
Gerd Hoffmann writes:
> This allows to set the option on the command line, i.e. "-display
> gtk,zoom-to-fit={on,off}", overriding the default choosen by qemu.
>
> Signed-off-by: Gerd Hoffmann
> ---
> ui/gtk.c | 8
> qapi/ui.json | 3 ++-
> 2 files changed, 10 insertions(+), 1 delet
On Fri, Aug 24, 2018 at 09:21:26AM +0800, Fam Zheng wrote:
> Upgrade OpenBSD to 6.3 using auto_install. Especially, drop SDL1,
> include SDL2.
>
> One limitation of this patch is that we need a temporary HTTP server on
> host 80 port for auto_install, because slirp cannot do guest forward on
> "ho
QEMU is already capable of exposing the new CPU features to guests, so
possibly a mis-configuration. Please provide the full QEMU command line
args you are using for this guest too.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
http
Hi
On Fri, Aug 24, 2018 at 10:12 AM Markus Armbruster wrote:
>
> Marc-André Lureau writes:
>
> > While it may be convenient to accept NULL value in
> > qobject_unref() (for similar reasons as free() accepts NULL), it is
> > not such a good idea for qobject_ref(): now assert() on NULL.
>
> Why is
On Fri, Aug 24, 2018 at 10:32:58AM +0200, Marc-André Lureau wrote:
> Hi
>
> On Fri, Aug 24, 2018 at 5:45 AM, Peter Xu wrote:
> > On Thu, Aug 23, 2018 at 04:31:20PM +0200, Marc-André Lureau wrote:
> >> Hi,
> >>
> >> In commit 25679e5d58e "chardev: tcp: postpone async connection setup"
> >> (and it
On 22.08.2018 09:57, David Hildenbrand wrote:
> The DXC is to be stored in the low core, and only in the FPC in case AFP
> is enabled in CR0.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/cpu.h | 1 +
> target/s390x/excp_helper.c | 28
> target/s
Hi
On Fri, Aug 24, 2018 at 10:05 AM Markus Armbruster wrote:
>
> Marc-André Lureau writes:
>
> > Add a new function qdict_steal(), that deletes a key from a dict, and
> > returns the associated value, if any. Simplify related code.
> >
> > Signed-off-by: Marc-André Lureau
> > ---
> > include/q
Hi
On Fri, Aug 24, 2018 at 5:45 AM, Peter Xu wrote:
> On Thu, Aug 23, 2018 at 04:31:20PM +0200, Marc-André Lureau wrote:
>> Hi,
>>
>> In commit 25679e5d58e "chardev: tcp: postpone async connection setup"
>> (and its follow up 99f2f54174a59), Peter moved chardev socket
>> connection to machine_don
Hi
On Fri, Aug 24, 2018 at 10:45 AM Peter Xu wrote:
>
> On Fri, Aug 24, 2018 at 10:32:58AM +0200, Marc-André Lureau wrote:
> > Hi
> >
> > On Fri, Aug 24, 2018 at 5:45 AM, Peter Xu wrote:
> > > On Thu, Aug 23, 2018 at 04:31:20PM +0200, Marc-André Lureau wrote:
> > >> Hi,
> > >>
> > >> In commit 2
On Fri, 08/24 09:22, Daniel P. Berrangé wrote:
> On Fri, Aug 24, 2018 at 09:21:26AM +0800, Fam Zheng wrote:
> > Upgrade OpenBSD to 6.3 using auto_install. Especially, drop SDL1,
> > include SDL2.
> >
> > One limitation of this patch is that we need a temporary HTTP server on
> > host 80 port for a
This allows to set the option on the command line, i.e. "-display
gtk,zoom-to-fit={on,off}", overriding the default choosen by qemu.
Signed-off-by: Gerd Hoffmann
---
ui/gtk.c | 8
qapi/ui.json | 6 +-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/ui/gtk.c b/ui/g
Original implementation for setsockopt by Chen Gang[1]; all bugs mine,
including removing assignment for optname which hopefully makes the
logic easier to follow and moving some variables to make the code
more selfcontained.
[1] http://patchwork.ozlabs.org/patch/565659/
Signed-off-by: Carlo Marce
On Wed, 22 Aug 2018 10:40:37 -0400
Pavel Zbitskiy wrote:
> In a few places translate.c contains non-breaking spaces (0xc2 0xa0)
> instead of regular ones (0x20):
>
> 7c 7c c2 a0 63 63
> 7c 7c 2063 63
> | |c c
>
> This confuses some text editors.
Fun :)
>
> Signed-off-by:
On Fri, Aug 24, 2018 at 04:52:20PM +0800, Fam Zheng wrote:
> On Fri, 08/24 09:22, Daniel P. Berrangé wrote:
> > On Fri, Aug 24, 2018 at 09:21:26AM +0800, Fam Zheng wrote:
> > > Upgrade OpenBSD to 6.3 using auto_install. Especially, drop SDL1,
> > > include SDL2.
> > >
> > > One limitation of this
This is a RFC series. It majorly did these things:
(1) move the monitor iothread management from monitor code to chardev
code somehow,
(2) decide which context/iothread to use for the chardev before
chardev creates, by parsing monitor options earlier (not init, but
only parsing) sinc
On 24 August 2018 at 09:52, Fam Zheng wrote:
> On Fri, 08/24 09:22, Daniel P. Berrangé wrote:
>> On Fri, Aug 24, 2018 at 09:21:26AM +0800, Fam Zheng wrote:
>> > Upgrade OpenBSD to 6.3 using auto_install. Especially, drop SDL1,
>> > include SDL2.
>> >
>> > One limitation of this patch is that we ne
Now after we have chardev maintained iothread, we switch to that one by
adding a parsing phase for monitors even before chardevs start to
initialize. Then chardevs will use a constant gcontext since the
creation of the object and it should never change.
Remove the context setup in qemu_chr_be_upd
Introduce contexts in chardev layer. Normally chardevs are running with
the main context except the monitors. Let's create the first standalone
context for the monitors. Note that this does not mean the chardev
backend will depend on the monitor code, but it's just a naming that let
people know
Just to put the flag parsing part into a standalone function, which will
be used in follow up patches. No functional change.
Signed-off-by: Peter Xu
---
vl.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/vl.c b/vl.c
index 16b913f9d5..25e156c020 100644
--- a
On Fri, Aug 24, 2018 at 10:51:18AM +0200, Marc-André Lureau wrote:
> Hi
>
> On Fri, Aug 24, 2018 at 10:45 AM Peter Xu wrote:
> >
> > On Fri, Aug 24, 2018 at 10:32:58AM +0200, Marc-André Lureau wrote:
> > > Hi
> > >
> > > On Fri, Aug 24, 2018 at 5:45 AM, Peter Xu wrote:
> > > > On Thu, Aug 23, 20
On Thu, 23 Aug 2018 18:32:41 +0200
Paolo Bonzini wrote:
> On 23/08/2018 16:51, Igor Mammedov wrote:
> > Topology (threads*cores*sockets) must match maxcpus to be valid,
> > otherwise we could start QEMU with invalid topology that throws
> > a error on migration destination side, that should not b
On Thu, 23 Aug 2018 15:03:07 -0300
Eduardo Habkost wrote:
> On Thu, Aug 23, 2018 at 06:32:41PM +0200, Paolo Bonzini wrote:
> > On 23/08/2018 16:51, Igor Mammedov wrote:
> > > Topology (threads*cores*sockets) must match maxcpus to be valid,
> > > otherwise we could start QEMU with invalid topolo
> On Fri, Aug 24, 2018 at 12:14:47AM +0800, Peng Hao wrote:
> > Signed-off-by: Peng Hao
> > ---
> > accel/kvm/kvm-all.c | 58
> > -
> > include/exec/memattrs.h | 2 +-
> > 2 files changed, 53 insertions(+), 7 deletions(-)
> >
>> @@ -536,7 +5
> On 23-Aug-2018, at 7:59 PM, Juan Quintela wrote:
>
> External Email
>
> "Jaggi, Manish" wrote:
>> Hi,
>
> Hi
>
> [Note that I was confused about what do you mean with problems with
> processorID. There is no processorID on the migration stream, so I
> didn't understood what you were talk
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20180814002653.12828-5-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 101 ++--
1 file changed, 51 insertions(+), 50 del
/git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20180824
for you to fetch changes up to 30a719e3cb5c5367f3651eba8fa935634bfee286:
hw/arm/mps2: Fix ID register errors on AN511 and AN385 (2018-08-24 10:22:44
+0100)
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20180814002653.12828-4-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 29 +
1 file changed, 5 insertions(+), 24 deletions(-)
diff -
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20180814002653.12828-2-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/fpu/softfloat.h | 56
fpu/softfloat.c | 188 +-
Reduce the size of the per-cpu GICH memory regions from 0x1000
to 0x200. The registers only cover 0x200 bytes, and the Cortex-A15
wants to map them at a spacing of 0x200 bytes apart. Having the
region be too large interferes with mapping them like that, so
reduce it.
Signed-off-by: Peter Maydell
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20180814002653.12828-3-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/fpu/softfloat.h | 85 ++---
fpu/softfloat.c | 391
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
Message-id: 20180821132811.17675-5-peter.ma
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
Message-id: 20180821132811.17675-4-peter.ma
The v8 AArch32 HACTLR2 register maps to bits [63:32] of ACTLR_EL2.
We implement ACTLR_EL2 as RAZ/WI, so make HACTLR2 also RAZ/WI.
(We put the regdef next to ACTLR_EL2 as a reminder in case we
ever make ACTLR_EL2 something other than RAZ/WI).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hende
Don't request that the arm_load_kernel() code should boot in secure
state if the CPU doesn't have a secure state. Currently this
doesn't make a difference because the boot.c code only examines
the secure_boot flag in code guarded by an ARM_FEATURE_EL3 check,
but upcoming changes for supporting boot
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
Message-id: 20180821132811.17675-6-peter.ma
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
Message-id: 20180821132811.17675-7-peter.ma
Factor out the code which changes the CPU state so as to
actually take an exception to AArch32. We're going to want
to use this for handling exception entry to Hyp mode.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
Message-i
In the MPS2 FPGAIO, PSCNTR is a free-running downcounter with
a reload value configured via the PRESCALE register, and
COUNTER counts up by 1 every time PSCNTR reaches zero.
Implement these counters.
We can just increment the counters migration subsection's
version ID because we only added it in t
Now we have a model of the CMSDK dual timer, we can wire it
up in the IoTKit.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118-5-peter.mayd...@linaro.org
---
include/hw/arm/iotkit.h | 3 ++-
hw/arm/iotkit.c
For the A15MPCore internal peripheral object, we handle GIC
security extensions support by checking whether the CPUs
have EL3 enabled; if so then we enable it also on the GIC.
Handle the virtualization extensions in the same way: if the
CPU has EL2 then enable it on the GIC and wire up the
virtuali
The Arm Cortex-M System Design Kit includes a "dual-input timer module"
which combines two programmable down-counters. Implement a model
of this device.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118-4-peter.mayd...@linaro.org
---
hw/timer/Makefile.o
The MPS2 FPGA images for the Cortex-M3 (mps2-an385 and mps2-511)
both include a CMSDK dual-timer module. Wire this up.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118-6-peter.mayd...@linaro.org
---
hw/arm/mps2.c |
The kernel booting specification for an AArch32 kernel requires that
it is booted in Hyp mode if available; otherwise the kernel can't
enable KVM. We were incorrectly leaving the kernel in SVC mode.
If we're booting an AArch32 kernel in the Nonsecure state and Hyp
mode is available, start in it.
S
Add a "virtualization" property to the vexpress-a15 board,
controlling presence of EL2. As with EL3, we default to
enabling it, but the user can disable it if they have an
older guest which can't cope with it being present.
Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
Message-id: 2018082
The MPS2 FPGAIO block includes some simple free-running counters.
Implement these.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118-2-peter.mayd...@linaro.org
---
include/hw/misc/mps2-fpgaio.h | 4 +++
hw/misc/mps2-fpgaio.c | 53 ++
Implement the IoTKit system control element's system information
block; this is just a pair of read-only version/config registers,
plus the usual PID/CID ID registers.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118
The Arm IoTKit includes a system control element which
provides a block of read-only ID registers and a block
of read-write control registers. Implement a minimal
version of this.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118-9-peter.mayd...@linaro.o
The AArch32 HCR and HCR2 registers alias HCR_EL2
bits [31:0] and [63:32]; implement them.
Since HCR2 exists in ARMv8 but not ARMv7, we need new
regdef arrays for "we have EL3, not EL2, we're ARMv8"
and "we have EL2, we're ARMv8" to hold the definitions.
Signed-off-by: Peter Maydell
Reviewed-by:
The IoTKit includes three different instances of the
CMSDK APB watchdog; create and wire them up.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118-7-peter.mayd...@linaro.org
---
include/hw/arm/iotkit.h | 6 +
h
Wire up the system control element's register banks
(sysctl and sysinfo).
This is the last of the previously completely unimplemented
components in the IoTKit.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118-11-pet
Create a new include file for the pl022's device struct,
type macros, etc, so that it can be instantiated using
the "embedded struct" coding style.
While we're adding the new file to MAINTAINERS, add
also the .c file, which was missing an entry.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe
Implement the necessary support code for taking exceptions
to Hyp mode in AArch32.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
Message-id: 20180820153020.21478-5-peter.mayd...@linaro.org
---
target/arm/helper.c | 82 ++
Implement a model of the TrustZone Master Securtiy Controller,
as documented in the Arm CoreLink SIE-200 System IP for
Embedded TRM (DDI0571G):
https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
The MSC is intended to sit in front of a device which can
be a bus master (eg
The IoTKit has a CMSDK timer device that runs on the S32KCLK.
Create this and wire it up.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20180820141116.9118-8-peter.mayd...@linaro.org
---
include/hw/arm/iotkit.h | 2 +-
hw/arm/iotkit
Refactor the fb property setting code so that rather than
using a set of pointers to local variables to track
whether a config value has been updated in the current
mbox and if so what its new value is, we just copy
all the current settings of the fb at the start, and
then update that copy as we go
On 32-bit exception entry, CPSR.J must always be set to 0
(see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also
be cleared on 32-bit exception entry (see v8A Arm ARM
DDI0487C.a G1.10).
Clear these bits. (This fixes a bug which will never be noticed
by non-buggy guests.)
Signed-off-by: Peter Mayd
Currently the PL022 calls pl022_reset() from its class init
function. Make it register a DeviceState reset method instead,
so that we reset the device on system reset.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20180820141116.9118-17-peter.mayd...@linaro.org
Rev
The IoTKit doesn't have any MSCs itself but it does need
some wiring to connect the external signals from MSCs
in the outer board model up to the registers and the
NVIC IRQ line.
We also need to expose a MemoryRegion corresponding to
the AHB bus, so that MSCs in the outer board model can
use that
The IoTKit does not have any Master Security Contollers itself,
but it does provide registers in the secure privilege control
block which allow control of MSCs in the external system.
Add support for these registers.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20
Abstract out the calculation of the pitch and size of the
framebuffer into functions that operate on the BCM2835FBConfig
struct -- these are about to get a little more complicated
when we add support for virtual and physical sizes differing.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hende
On Fri, 08/24 10:06, Peter Maydell wrote:
> On 24 August 2018 at 09:52, Fam Zheng wrote:
> > On Fri, 08/24 09:22, Daniel P. Berrangé wrote:
> >> On Fri, Aug 24, 2018 at 09:21:26AM +0800, Fam Zheng wrote:
> >> > Upgrade OpenBSD to 6.3 using auto_install. Especially, drop SDL1,
> >> > include SDL2.
The AN505 FPGA image includes four PL081 DMA controllers, each
of which is gated by a Master Security Controller that allows
the guest to prevent a non-secure DMA controller from accessing
memory that is used by secure guest code. Create and wire
up these devices.
Signed-off-by: Peter Maydell
Rev
The PL022 interrupt registers have bits allocated as:
0: ROR (receive overrun)
1: RT (receive timeout)
2: RX (receive FIFO half full or less)
3: TX (transmit FIFO half full or less)
A cut and paste error meant we had the wrong value for
the PL022_INT_RT constant. This bug doesn't affect device
The SPI controllers in the MPS2 AN505 board are PL022s.
We have a model of the PL022, so create these devices.
We don't currently model the LCD controller that sits behind
one of the PL022s; the others are intended to control devices
that sit on the FPGA's general purpose SPI connector or
"shield"
Fix MPS2 SCC config register values for the mps2-an511
and mps2-an385 boards:
* the SCC_AID bits [23:20] specify the FPGA build target board revision,
and the SCC_CFG4 register specifies the actual board revision, so
these should have matching values. Claim to be board revision C,
consist
In the PL022, register offset 0x20 is the ICR, a write-only
interrupt-clear register. Register offset 0x24 is DMACR, the DMA
control register. We were incorrectly implementing (a stub version
of) DMACR at 0x20, and not implementing anything at 0x24. Fix this
bug.
Signed-off-by: Peter Maydell
M
Following the bulk conversion of the iwMMXt code, there are
just a handful of hard coded tabs in target/arm; fix them.
This is a whitespace-only patch.
Signed-off-by: Peter Maydell
Message-id: 20180821165215.29069-4-peter.mayd...@linaro.org
---
target/arm/cpu.h | 16
target
Cornelia Huck wrote:
> On Thu, 23 Aug 2018 14:25:20 +0200
> Thomas Huth wrote:
>
>> We can re-use the s390-ccw bios code to implement a small firmware
>> for a s390x guest which prints out the "A" and "B" characters and
>> modifies the memory, as required for the migration test.
>>
>> Signed-off
Move from the legacy SysBusDevice::init method to using
DeviceState::realize.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20180820141116.9118-19-peter.mayd...@linaro.org
Reviewed-by: Richard Henderson
---
hw/ssi/pl022.c | 8 +++-
1 file changed, 3 insertion
Untabify the arm iwmmxt_helper.c. This affects only the iwMMXt code.
We've never touched that code in years, so it's not going to get
fixed up by our "change when touched" process, and a bulk change is
not going to be too disruptive.
This commit was produced using Emacs "untabify" (plus one
by-ha
Untabify the arm translate.c. This affects only some lines,
mostly comments, in the iwMMXt code. We've never touched
that code in years, so it's not going to get fixed up
by our "change when touched" process, and a bulk change
is not going to be too disruptive.
This commit was produced using Emacs
Well, then something isn't right here.
"Zoom to Fit" disabled: qemu starts with a small window (1:1 scale) and
resizes the window when the xserver/window manager starts (1:1 scale).
This is the sane and wanted behavior.
"Zoom to Fit" enabled: qemu starts with a small window and doesn't
resizes th
Some of the config register values we were setting for the MPS2 SCC
weren't correct:
* the SCC_AID bits [23:20] specify the FPGA build target board revision,
and the SCC_CFG4 register specifies the actual board revision, so
these should have matching values. Claim to be board revision C,
The handling of framebuffer properties in the bcm2835_property code
is a bit clumsy, because for each of the many fb related properties
we try to track the value we're about to set and whether we're going
to be setting a value, and then we hand all the new values off
to the framebuffer via a functi
Use the DeviceState vmsd pointer rather than calling vmstate_register()
directly.
Signed-off-by: Peter Maydell
Message-id: 20180820141116.9118-18-peter.mayd...@linaro.org
Reviewed-by: Richard Henderson
---
hw/ssi/pl022.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ssi
The bcm2835_fb's initial resolution and other parameters are set
via QOM properties. We should reset to those initial values on
device reset, which means we need to save the QOM property
values somewhere that they are not overwritten by guest
changes to the framebuffer configuration.
Signed-off-by
Validate the config settings that the guest tries to set.
The wiki page documentation is not really accurate here:
generally rather than failing requests to set bad parameters,
the hardware will just clip them to something sensible.
Validate the most important parameters: sizes and
the viewport o
The BCM2835FBState struct has a 'pitch' field which is a
cached copy of xres * (bpp >> 3), and a 'size' field which is
a cached copy of pitch * yres. However we don't actually do
anything with these fields; delete them. We retain the
now-unused slots in the VMState struct for migration
compatibilit
The raspi framebuffir in bcm2835_fb supports the definition
of a virtual "viewport", which is smaller than the full
physical framebuffer size and at an adjustable offset within
it. Only the viewport area is sent to the screen. This allows
the guest to do things like double buffering, or scrolling
b
Refactor bcm2835_fb_mbox_push() to work by calling
bcm2835_fb_validate_config() and bcm2835_fb_reconfigure(),
so that config set this way is also validated.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20180814144436.679-9-peter.mayd...@linaro.org
---
hw/display/bcm28
On 23 August 2018 at 17:47, Paolo Bonzini wrote:
> The following changes since commit 659b11e7a7239529cfdb4968418268ff9aa22d88:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/linux-user-for-3.1-pull-request' into staging
> (2018-08-21 11:36:15 +0100)
>
> are available in the Git repo
On 2018/8/24 0:52, Peter Maydell wrote:
> On 23 August 2018 at 16:45, Dongjiu Geng wrote:
>> This patch extends the qemu-kvm state sync logic with support for
>> KVM_GET/SET_VCPU_EVENTS, giving access to yet missing SError exception.
>> And also it can support the exception state migration.
>>
>>
On 24 August 2018 at 11:28, gengdongjiu wrote:
> On 2018/8/24 0:52, Peter Maydell wrote:
>> On 23 August 2018 at 16:45, Dongjiu Geng wrote:
>>> +static int kvm_put_vcpu_events(ARMCPU *cpu)
>>> +{
>>> +CPUARMState *env = &cpu->env;
>>> +struct kvm_vcpu_events events = {};
>>> +
>>> +if
On Fri, Aug 24, 2018 at 05:18:45PM +0800, peng.h...@zte.com.cn wrote:
[...]
> > > -cpu_physical_memory_write(ent->phys_addr, ent->data,
> > > ent->len);
> > > +if (ent->pio == 1) {
> > > +address_space_rw(&address_space_io, ent->phys_addr,
> > > +
On Fri, Aug 24, 2018 at 10:03:05AM +0200, Igor Mammedov wrote:
> On Thu, 23 Aug 2018 14:25:01 -0300
> Eduardo Habkost wrote:
>
> > On Thu, Aug 23, 2018 at 10:14:06AM +0200, Igor Mammedov wrote:
> > > On Wed, 22 Aug 2018 15:01:12 -0300
> > > Eduardo Habkost wrote:
> > [...]
> > > > However, hav
On 2018/8/24 18:38, Peter Maydell wrote:
> On 24 August 2018 at 11:28, gengdongjiu wrote:
>> On 2018/8/24 0:52, Peter Maydell wrote:
>>> On 23 August 2018 at 16:45, Dongjiu Geng wrote:
+static int kvm_put_vcpu_events(ARMCPU *cpu)
+{
+CPUARMState *env = &cpu->env;
+s
From: Andrey Smirnov
IP block found on several generations of i.MX family does not use
vanilla SDHCI implementation and it comes with a number of quirks.
Introduce i.MX SDHCI subtype of SDHCI block to add code necessary to
support unmodified Linux guest driver.
Cc: Peter Maydell
Cc: Jason Wang
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