On 21.06.2018 19:01, Christian Borntraeger wrote:
> kexec/kdump as well as the bootloader use a subcode of diagnose 308
> that is supposed to reset the subsystem but not comprise a full
> "reboot". With the latest refactoring this is now broken when
> -no-reboot is used. This for example breaks vir
Hi Eric
On 6/22/2018 2:39 PM, Auger Eric Wrote:
> Hello Jia,
>
> On 06/22/2018 03:44 AM, Jia He wrote:
>> Hi Eric
>> I want to test your smmu emulation patchset with vfio-pci ethernet device.
>> Could you kindly give me the NIC type information.
>> In my test, there is vf probe error for menallox
Public bug reported:
QEMU v2.12.0, Ubuntu 18.04 host.
Build QEMU and the bare metal image exactly as described at:
https://raspberrypi.stackexchange.com/revisions/85135/4 with:
Then cd into example 09_framebuffer.
Now if I do:
../../qemu/aarch64-softmmu/qemu-system-aarch64 -M raspi3 -kernel
ke
Things that work:
-
https://github.com/cirosantilli/linux-kernel-module-cheat/tree/741f5215e9515c0d7179671f49fe1781f94e70e3#graphic-mode-arm
which shows the Penguin with the Linux kernel, after hacking that repo up to
use the exact same QEMU executable as reported here
- the UART examples on th
H
On 6/21/2018 7:16 PM, Eric Auger Wrote:
> On TLB invalidation commands, let's call registered
> IOMMU notifiers. Those can only be UNMAP notifiers.
> SMMUv3 does not support notification on MAP (VFIO).
>
> This patch allows vhost use case where IOTLB API is notified
> on each guest IOTLB invali
Hello Jia,
On 06/22/2018 09:15 AM, Jia He wrote:
> H
>
> On 6/21/2018 7:16 PM, Eric Auger Wrote:
>> On TLB invalidation commands, let's call registered
>> IOMMU notifiers. Those can only be UNMAP notifiers.
>> SMMUv3 does not support notification on MAP (VFIO).
>>
>> This patch allows vhost use c
Starting qemu with and querying some outputs:
[...]
-m 4G,maxmem=20G,slots=2 \
-numa node,nodeid=0,cpus=0-1 -numa node,nodeid=1,cpus=2-3 \
[...]
-device virtio-balloon \
-object memory-backend-ram,id=mem0,size=8G \
-device pc-dimm,id=dimm0,memdev=mem0 \
-object memory-backend-ram,id=mem1,size=8G \
This series brings translation configuration caching and IOTLB
emulation. The last patch implements VHOST integration and
allows to run VSMMUv3 along with VHOST emulated end points.
The first patch fixes the passthrough mode bug reported by Jia.
It reworks the translate function and this series n
From: Jia He
In case the STE's config is "Bypass" we currently don't set the
IOMMUTLBEntry perm flags and the access does not succeed. Also
if the config is 0b0xx (Aborted/Reserved), decode_ste and
smmuv3_decode_config currently returns -EINVAL and we don't enter
the expected code path: we record
Let's cache config data to avoid fetching and parsing STE/CD
structures on each translation. We invalidate them on data structure
invalidation commands.
We put in place a per-smmu mutex to protect the config cache. This
will be useful too to protect the IOTLB cache. The caches can be
accessed with
On TLB invalidation commands, let's call registered
IOMMU notifiers. Those can only be UNMAP notifiers.
SMMUv3 does not support notification on MAP (VFIO).
This patch allows vhost use case where IOTLB API is notified
on each guest IOTLB invalidation.
Signed-off-by: Eric Auger
Reviewed-by: Peter
We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256.
It is implemented as a hash table whose key is a combination
of the 16b asid and 48b IOVA (Jenkins hash).
Entries are invalidated on TLB invalidation commands, either
globally, or per asid, or per asid/iova.
Signed-off-by: Eric Auger
---
v
Hello,
Thanks for the feedback, really appreciated.
On Fri, 22 Jun 2018, David Gibson wrote:
On Thu, Jun 21, 2018 at 09:47:51PM -0700, Guenter Roeck wrote:
sam4660ex (or at least this emulation) does not support the "ibm,cpm" power
management. As a result, Linux crashes when trying to access i
The timer controller can be driven by either an external 1MHz clock or
by the APB clock. Today, the model makes the assumption that the APB
frequency is always set to 24MHz but this is incorrect.
The AST2400 SoC on the palmetto machines uses a 48MHz input clock
source and the APB can be set to 48M
Hello,
The Aspeed SoC clocks are driven by an input source clock which can
have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a calculation
using parameters in the H-PLL Parameter register or from a predefined
set of frequ
All Aspeed SoC clocks are driven by an input source clock which can
have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a
calculation using parameters in the H-PLL Parameter register or from a
predefined set of frequencies i
This enables us to apply the same filter in DEBUG_DBDMA_CHANMASK to the
DBDMA command execution debug output.
Signed-off-by: Mark Cave-Ayland
---
hw/misc/macio/mac_dbdma.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/m
Commit 84051eb400 "adb: add property to disable direct reg 3 writes" added a
workaround for MacOS 9 incorrectly setting the mouse address during boot of
PMU machines.
Further testing has shown that since fb6649f172 "adb: fix read reg 3 byte
ordering" this can still sometimes happen with the CUDA m
The System Control Unit should be initialized first as it drives all
the configuration of the SoC and other device models.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
---
hw/arm/aspeed_soc.c | 40
1 file changed, 20 insertions(+), 20 deleti
This feature is intended to distinguish ARMv8-M variants: Baseline and
Mainline. ARMv7-M compatibility requires the Main Extension. ARMv6-M
compatibility is provided by all ARMv8-M implementations.
Signed-off-by: Julia Suvorova
---
target/arm/cpu.c | 3 +++
target/arm/cpu.h | 1 +
2 files change
Here are a couple of minor fixes for things discovered during further
testing of the recent Mac changes.
Signed-off-by: Mark Cave-Ayland
Mark Cave-Ayland (2):
mac_dbdma: only dump commands for debug enabled channels
mac_newworld: always enable disable_direct_reg3_writes for ADB
machines
Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally
aligned memory accesses for load/store instructions.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/targ
On Fri, 22 Jun 2018, David Gibson wrote:
On Thu, Jun 21, 2018 at 09:17:11AM +0200, BALATON Zoltan wrote:
On Wed, 20 Jun 2018, David Gibson wrote:
On Tue, Jun 19, 2018 at 10:52:15AM +0200, BALATON Zoltan wrote:
As well as being able to generate its own i2c transactions, the ppc4xx
i2c controlle
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/input/pckbd.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
> index f33e3fc63d..1102d2a31b 100644
> --- a/hw/input/pckbd.c
> +++
Subject: explicitly
Marc-André Lureau writes:
> The C standard has the initial value at 0 and the subsequent values
> incremented by 1. No need to set this explicitely.
>
> This will prevent from artificial "gaps" when compiling out some enum
> values and having unnecessarily large MAX values &
v2:
* Added feature bit for the Main Extention
* Alignment patch is modified to use ARM_FEATURE_M_MAIN
Julia Suvorova (2):
target/arm: Introduce ARM_FEATURE_M_MAIN
target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline
target/arm/cpu.c | 3 +++
target/arm/cpu.h |
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/dma/omap_dma.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
> index abd18c67ea..ab3a1b0451 100644
> --- a/hw/dma/omap_dma.
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/dma/omap_dma.c | 66 ++-
> 1 file changed, 42 insertions(+), 24 deletions(-)
[...]
> case 0x78: /* DMA4_GCR */
> s->gcr = value & 0
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/sd/omap_mmc.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
> index 5b47cadf11..aa2a816f76 100644
> --- a/hw/sd/omap_
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i2c/omap_i2c.c | 23 +++
> 1 file changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
> index 26e3e5ebf6..e6f34fe31f 100644
> ---
Marc-André Lureau writes:
> Wrap generated code with #if/#endif using an 'ifcontext' on
> QAPIGenCSnippet objects.
>
> Signed-off-by: Marc-André Lureau
> ---
> scripts/qapi/commands.py | 19 ++-
> tests/test-qmp-cmds.c| 4 ++--
> 2 files changed, 12 insertions(+), 11 deleti
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/arm/omap.h | 20
> 1 file changed, 12 insertions(+), 8 deletions(-)
[...]
> @@ -997,14 +998,17 @@ enum {
>
> # ifdef TCMI_VERBOSE
> # define OMAP_8B_REG(paddr)
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/stellaris.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index a8f1f6a912..d06e366402 100644
> --- a/hw/arm/stellaris.c
On Thu, Jun 21, 2018 at 06:36:19PM +0200, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Thu, Jun 21, 2018 at 10:28:23AM -0500, Eric Blake wrote:
> >> On 06/15/2018 10:42 AM, Daniel P. Berrangé wrote:
> >> > From: "Daniel P. Berrange"
> >> >
> >> > Add a QAuthZList object type t
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> hw_error() finally calls abort(), but there is no need to abort here.
Additionally, hw_error() is also only meant for CPU errors (since it
dumps the CPU state). We should really rename that function to
"cpu_hw_error" one day to avoid that people
On 21.06.2018 20:02, Philippe Mathieu-Daudé wrote:
> hw_error() finally calls abort(), but there is no need to abort here.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/smc91c111.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/hw/net/smc91c111.c b/
We finally managed to reproduce this issue in our test environment. 2
out of 3 VMs froze within 12 hours of constant migrations.
All migrations took place between Skylake Gold => non-Skylake Gold and
non-Skylake Gold => Skylake Gold. Test environment hypervisors are
running Debian 9, Qemu 2.11 and
On Thu, 21 Jun 2018, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 06/21/2018 05:08 AM, BALATON Zoltan wrote:
These are fixes to sm501 emulation that were found while testing with
AmigaOS 4.1FE (AmigaOS 4 is known to work on real hardware but we have
no way to verify it against hardware). While t
(Berto, I'm CCing you just because this is about reopen, so you might
have thoughts about it. But it's not really related to what you're
currently working on.)
Am 21.06.2018 um 19:44 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 21.06.2018 20:17, Kevin Wolf wrote:
> > Am 21.06.2018 um 17:55 hat
On 21/06/2018 22:06, John Snow wrote:
>
> On 06/20/2018 09:25 AM, Paolo Bonzini wrote:
>> +pio_fis_i = is_atapi ? ad->done_atapi_packet : !is_write;
> Per DPIOO1, does this go to false for the first DRQ block, or did I
> misunderstand? Currently my understanding:
DPIOO1 is the !is_atapi && is
Am 22.06.2018 um 04:25 hat Fam Zheng geschrieben:
> On Thu, 06/21 15:21, Nishanth Aravamudan wrote:
> > When the AioContext changes, we need to associate a LinuxAioState with
> > the new AioContext. Use the bdrv_attach_aio_context callback and call
> > the new aio_setup_linux_aio(), which will allo
On 21 June 2018 at 15:37, Richard Henderson
wrote:
> Re-issuing the v2 pull request with the proper form.
>
>
> r~
>
>
> The following changes since commit 42747d6abb5035473e5585fa17620c1e8983a70b:
>
> Merge remote-tracking branch
> 'remotes/edgar/tags/edgar/xilinx-next-2018-06-15.for-upstream'
On Thu, 21 Jun 2018 16:11:16 -0400
Stefan Berger wrote:
> On 06/21/2018 07:55 AM, Marc-André Lureau wrote:
> > From: Stefan Berger
> >
> > The TPM Physical Presence interface consists of an ACPI part, a shared
> > memory part, and code in the firmware. Users can send messages to the
> > firmware
Marc-André Lureau writes:
> Wrap generated code with #if/#endif using an 'ifcontext' on
> QAPIGenCSnippet objects.
>
> Signed-off-by: Marc-André Lureau
> ---
> scripts/qapi/events.py | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/scripts/qapi/events.py b/scripts/q
Max Filippov writes:
> On Thu, Jun 21, 2018 at 11:41 AM, Alex Bennée wrote:
>> Signed-off-by: Alex Bennée
>> ---
>> _posts/2018-06-21-tcg-testing.md | 129 +++
>> 1 file changed, 129 insertions(+)
>> create mode 100644 _posts/2018-06-21-tcg-testing.md
>>
>> diff
Marc-André Lureau writes:
> Hi
>
> On Thu, Jun 21, 2018 at 6:47 PM, Markus Armbruster wrote:
>> I think we can bite off a digestible part of this series:
>> target-independent top-level conditionals. I think that's PATCH
>> 01-14,31 and applicable parts of 35-37. The idea is to merge that part
Philippe Mathieu-Daudé writes:
> Builds only require:
> - dtc
> - keycodemapdb
> - capstone
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Some tests might require ROMs. Can they clone submodules only when required?
> ---
> .travis.yml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-
On 22 June 2018 at 03:15, Philippe Mathieu-Daudé wrote:
> Builds only require:
> - dtc
> - keycodemapdb
> - capstone
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Some tests might require ROMs. Can they clone submodules only when required?
In general the ROM blobs should be in the main git r
On Thu, Jun 21, 2018 at 10:37:10PM -0300, Philippe Mathieu-Daudé wrote:
> Cc'ing Gerd who maintains many hw/display/ files.
>
> On 06/21/2018 09:51 PM, David Gibson wrote:
> > On Thu, Jun 21, 2018 at 10:08:21AM +0200, BALATON Zoltan wrote:
> >> These are fixes to sm501 emulation that were found wh
Hi David,
I'm a bit confused by this massive post... it doesn't have any cover letter, but
it contains all the patches you recently pushed to ppc-for-3.0. Was it supposed
to be a pull request ?
Cheers,
--
Greg
On Fri, 22 Jun 2018 14:24:15 +1000
David Gibson wrote:
> From: Cédric Le Goater
>
On Thu, 21 Jun 2018, BALATON Zoltan wrote:
Display updates and drawing hardware cursor did not work when frame
buffer address was non-zero. Fix this by taking the frame buffer
address into account in these cases. This fixes screen dragging on
AmigaOS. Based on patch by Sebastian Bauer.
Signed-of
From: Sai Pavan Boddu
Qspi dma has a burst length of 64 bytes, So limit the transactions w.r.t
dma-burst-size property.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Edgar E. Iglesias
---
Changes for V2:
Remove dynamic allocation of dma_buf and limit burst size to 2k
Changes for V3:
Inste
On Thu, 21 Jun 2018 22:34:49 +0200
Christian Borntraeger wrote:
> On 06/21/2018 07:08 PM, Paolo Bonzini wrote:
> > On 21/06/2018 19:01, Christian Borntraeger wrote:
> >> kexec/kdump as well as the bootloader use a subcode of diagnose 308
> >> that is supposed to reset the subsystem but not comp
On 21 June 2018 at 15:57, Eric Blake wrote:
> The following changes since commit 46012db666990ff2eed1d3dc199ab8006439a93b:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180619' into
> staging (2018-06-20 09:51:30 +0100)
>
> are available in the Git repository at:
>
> git://rep
On 22/06/2018 11:46, Cornelia Huck wrote:
>>> Ok, then my suggestion made even more sense. :) No other objections
>>> apart from the name of the constant.
>>>
>>> Paolo
>> SHUTDOWN_CAUSE_S390_PARTIAL ?
> Don't like that one much.
>
>> SHUTDOWN_CAUSE_S390_SUBSYS_RESET?
> Either that, or drop the
On 20 June 2018 at 14:20, Peter Maydell wrote:
> Hi; this is v3 of my iommu patchset. All the IOMMU stuff is now
> in master, so the remaining part is just implementing and using
> the Trustzone Memory Protection Controller in the mps2-an505.
>
> Changes from v2 to v3 (all fairly minor):
> * add
On 06/22/2018 11:59 AM, Paolo Bonzini wrote:
> On 22/06/2018 11:46, Cornelia Huck wrote:
Ok, then my suggestion made even more sense. :) No other objections
apart from the name of the constant.
Paolo
>>> SHUTDOWN_CAUSE_S390_PARTIAL ?
>> Don't like that one much.
>>
>>> SHU
On 22 June 2018 at 09:01, Julia Suvorova wrote:
> v2:
> * Added feature bit for the Main Extention
> * Alignment patch is modified to use ARM_FEATURE_M_MAIN
>
> Julia Suvorova (2):
> target/arm: Introduce ARM_FEATURE_M_MAIN
> target/arm: Strict alignment for ARMv6-M and ARMv8-M Baselin
On 22.06.2018 12:10, Christian Borntraeger wrote:
>
>
> On 06/22/2018 11:59 AM, Paolo Bonzini wrote:
>> On 22/06/2018 11:46, Cornelia Huck wrote:
> Ok, then my suggestion made even more sense. :) No other objections
> apart from the name of the constant.
>
> Paolo
SHUTDOWN
On 12 June 2018 at 01:51, Richard Henderson
wrote:
> There is no point in listing a syscall if you want the same effect as
> not listing it. In one less trivial case, the goto was demonstrably
> not reachable.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/syscall.c | 144 +
We define a new hotpluggable RAM region (aka. device memory).
Its base is 2TB GPA. This obviously requires 42b IPA support
in KVM/ARM, FW and guest kernel. At the moment the device
memory region is max 2TB.
This is largely inspired of device memory initialization in
pc machine code.
Signed-off-by
From: Shameer Kolothum
We introduce an helper to create a memory node. Also we nop
existing /memory node in numa and non numa case.
Signed-off-by: Eric Auger
Signed-off-by: Shameer Kolothum
---
the nop related change should disappear if the following series
lands upstream:
[PATCH v2 0/3] ARM
From: Shameer Kolothum
This patch adds the the PC-DIMM hot-plug/hot-unplug infrastructure
in machvirt.
Signed-off-by: Eric Auger
Signed-off-by: Shameer Kolothum
Signed-off-by: Kwangwoo Lee
---
default-configs/arm-softmmu.mak | 2 ++
hw/arm/virt.c | 53 +
This series aims at supporting PC-DIMM in machvirt. The device_memory
is set at 2TB. While its max capacity is currently limited to 2TB,
the actual size depends on the initial guest RAM size and maxmem
parameter. Using memory beyond 2TB is possible if KVM, the FW and the
guest supports up to 42 bit
From: Shameer Kolothum
This patch add memory nodes corresponding to PC-DIMM
regions.
Signed-off-by: Shameer Kolothum
Signed-off-by: Eric Auger
---
hw/arm/boot.c | 40
1 file changed, 40 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index cc
From: Shameer Kolothum
Generate Memory Affinity Structures for PC-DIMM ranges.
Signed-off-by: Shameer Kolothum
Signed-off-by: Eric Auger
---
hw/arm/virt-acpi-build.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-
kexec/kdump as well as the bootloader use a subcode of diagnose 308
that is supposed to reset the I/O subsystem but not comprise a full
"reboot". With the latest refactoring this is now broken when
-no-reboot is used or when libvirt acts on a reboot QMP event, for
example a virt-install from iso im
On 12 June 2018 at 01:51, Richard Henderson
wrote:
> Defines a unified structure for implementation and strace.
> Supplies a generator script to build the declarations and
> the lookup function.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/syscall.h | 178 +++
>
On Fri, Jun 22, 2018 at 09:00:08AM +0100, Mark Cave-Ayland wrote:
> This enables us to apply the same filter in DEBUG_DBDMA_CHANMASK to the
> DBDMA command execution debug output.
>
> Signed-off-by: Mark Cave-Ayland
Applied to ppc-for-3.0, thanks.
> ---
> hw/misc/macio/mac_dbdma.c | 21 +++
The following changes since commit 46012db666990ff2eed1d3dc199ab8006439a93b:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180619' into
staging (2018-06-20 09:51:30 +0100)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-3.0-201
Previously, the effective values of the various spapr capability flags
were only determined at machine reset time. That was a lazy way of making
sure it was after cpu initialization so it could use the cpu object to
inform the defaults.
But we've now improved the compat checking code so that we d
On Fri, Jun 22, 2018 at 11:44:39AM +0200, Greg Kurz wrote:
> Hi David,
>
> I'm a bit confused by this massive post... it doesn't have any cover letter,
> but
> it contains all the patches you recently pushed to ppc-for-3.0. Was it
> supposed
> to be a pull request ?
Gah. Yes, it was. I'm not
spapr capabilities have an apply hook to actually activate (or deactivate)
the feature in the system at reset time. However, a number of capabilities
affect the setup of cpus, and need to be applied to each of them -
including hotplugged cpus for extra complication. To make this simpler,
add an o
From: Greg Kurz
A per-CPU machine data pointer was recently added to PowerPCCPU. The
motivation is to to hide platform specific details from the core CPU
code. This per-CPU data can hold state which is relevant to the guest
though, eg, Virtual Processor Areas, and we should migrate this state.
T
On Fri, Jun 22, 2018 at 09:00:09AM +0100, Mark Cave-Ayland wrote:
> Commit 84051eb400 "adb: add property to disable direct reg 3 writes" added a
> workaround for MacOS 9 incorrectly setting the mouse address during boot of
> PMU machines.
>
> Further testing has shown that since fb6649f172 "adb: f
From: Cédric Le Goater
On Power9, the thread interrupt presenter has a different type and is
linked to the chip owning the cores.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 21 +++--
hw/ppc/pnv_core.c| 18 +-
incl
From: John Arbuckle
Fix the helper_fpscr_clrbit() function so it correctly sets the FEX
and VX bits.
Determining the value for the Floating Point Status and Control
Register's (FPSCR) FEX bit is suppose to be done like this:
FEX = (VX & VE) | (OX & OE) | (UX & UE) | (ZX & ZE) | (XX & XE))
It i
From: Greg Kurz
QEMU implements the "Shared Processor LPAR" (SPLPAR) option, which allows
the hypervisor to time-slice a physical processor into multiple virtual
processor. The intent is to allow more guests to run, and to optimize
processor utilization.
The guest OS can cede idle VCPUs, so that
From: Cédric Le Goater
This moves the details of the ISA bus creation under the LPC model but
more important, the new PnvChip operation will let us choose the chip
class to use when we introduce the different chip classes for Power9
and Power8. It hides away the processor chip controllers from th
From: Cédric Le Goater
The device tree node of the ISA bus was being partially done in
different places. Move all the nodes creation under the same routine.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 51 +++
1
ppc_check_compat() is used in a number of places to check if a cpu object
supports a certain compatiblity mode, subject to various constraints.
It takes a PowerPCCPU *, however it really only depends on the cpu's class.
We have upcoming cases where it would be useful to make compatibility
checks b
From: Cédric Le Goater
spapr_irq_alloc_block and spapr_irq_alloc() are now deprecated.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 80 +-
include/hw/ppc/spapr.h | 4 ---
2 files ch
From: BALATON Zoltan
According to PPC440 User Manual PPC440 has multiple opcodes for icbt
instruction: one for compatibility with older cores and two 440
specific opcodes one of which is defined in BookE. QEMU only
implements two of these, add the missing one.
Signed-off-by: BALATON Zoltan
Sign
From: Sebastian Bauer
According to the sm501 specs the hardware cursor colors are to be given in
the rgb565 format, but the code currently interprets them as bgr565.
Therefore, the colors of the hardware cursors are wrong in the QEMU
display, e.g., the standard mouse pointer of AmigaOS appears b
From: Cédric Le Goater
Today, when a device requests for IRQ number in a sPAPR machine, the
spapr_irq_alloc() routine first scans the ICSState status array to
find an empty slot and then performs the assignement of the selected
numbers. Split this sequence in two distinct routines : spapr_irq_fin
The way we used to handle KVM allowable guest pagesizes for PAPR guests
required some convoluted checking of memory attached to the guest.
The allowable pagesizes advertised to the guest cpus depended on the memory
which was attached at boot, but then we needed to ensure that any memory
later hotp
KVM HV has a restriction that for HPT mode guests, guest pages must be hpa
contiguous as well as gpa contiguous. We have to account for that in
various places. We determine whether we're subject to this restriction
from the SMMU information exposed by KVM.
Planned cleanups to the way we handle t
From: BALATON Zoltan
We don't emulate slave mode so related registers are not needed.
[lh]sadr are only retained to avoid too many warnings and simplify
debugging but sdata is not even correct because device has a 4 byte
FIFO instead so just remove this unimplemented register for now.
The intr r
From: Mark Cave-Ayland
This enables us to apply the same filter in DEBUG_DBDMA_CHANMASK to the
DBDMA command execution debug output.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
hw/misc/macio/mac_dbdma.c | 21 +++--
1 file changed, 11 insertions(+), 10 delet
From: BALATON Zoltan
As well as being able to generate its own i2c transactions, the ppc4xx
i2c controller has a DIRECTCNTL register which allows explicit control
of the i2c lines.
Using this register an OS can directly bitbang i2c operations. In
order to let emulated i2c devices respond to this
From: Cédric Le Goater
It introduces a base PnvChip class from which the specific processor
chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to
define an init and a realize routine which will create the controllers
of the target processor. For the moment, the base PnvChip class
ha
When QEMU_PSCI_CONDUIT_DISABLED is set, it doesn't mean all the PSCI
conduits are totally disabled, it only mean the QEMU built-in PSCI
support is disabled, in such a case, e.g. EL3 is enabled and external
firmware (it is usually Arm Trusted Firmware) is loaded, SMC should be
used for the guest to
From: Mark Cave-Ayland
Commit 84051eb400 "adb: add property to disable direct reg 3 writes" added a
workaround for MacOS 9 incorrectly setting the mouse address during boot of
PMU machines.
Further testing has shown that since fb6649f172 "adb: fix read reg 3 byte
ordering" this can still sometim
The way the POWER Hash Page Table (HPT) MMU is virtualized by KVM HV means
that every page that the guest puts in the pagetables must be truly
physically contiguous, not just GPA-contiguous. In effect this means that
an HPT guest can't use any pagesizes greater than the host page size used
to back
KVM HV has some limitations (deriving from the hardware) that mean not all
host-cpu supported pagesizes may be usable in the guest. At present this
means that KVM guests and TCG guests may see different available page sizes
even if they notionally have the same vcpu model. This is confusing and
a
On 12 June 2018 at 01:51, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> linux-user/syscall.h | 51
> linux-user/strace.c| 35 ---
> linux-user/syscall.c | 402 +--
> linux-user/syscall_file.c | 423
Currently during KVM initialization on POWER, kvm_fixup_page_sizes()
rewrites a bunch of information in the cpu state to reflect the
capabilities of the host MMU and KVM. This overwrites the information
that's already there reflecting how the TCG implementation of the MMU will
operate.
This means
The paravirtualized PAPR platform sometimes needs to restrict the guest to
using only some of the page sizes actually supported by the host's MMU.
At the moment this is handled in KVM specific code, but for consistency we
want to apply the same limitations to all accelerators.
This makes a start o
On 12 June 2018 at 01:51, Richard Henderson
wrote:
> Version 3 does not attempt the whole thing in one go,
> and does attempt to incorporate strace into the reorg.
>
> Thoughts?
This approach works for me. I won't bother to review the
rest of the patchset for the moment, until Laurent weighs
in o
On 22 June 2018 at 11:37, Hongbo Zhang wrote:
> When QEMU_PSCI_CONDUIT_DISABLED is set, it doesn't mean all the PSCI
> conduits are totally disabled, it only mean the QEMU built-in PSCI
> support is disabled, in such a case, e.g. EL3 is enabled and external
> firmware (it is usually Arm Trusted Fi
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