On 21 May 2018 at 07:35, Fam Zheng wrote:
> Coverity doesn't like the tests under fail label (report CID 1385847).
> Reset the fields so the clean up order is more apparent.
>
> Signed-off-by: Fam Zheng
> ---
> block/nvme.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/block/nv
We turned Out-Of-Band feature of monitors off for 2.12 release. Now we
try to turn that on again.
Signed-off-by: Peter Xu
--
Now OOB should be okay with all known tests (except iotest qcow2, since
it is still broken on master), and AFAIK now we should also be okay with
ARM+Libvirt (not testsed,
On Fri, May 18, 2018 at 06:54:48PM +0100, Peter Maydell wrote:
> On 14 May 2018 at 18:19, Daniel P. Berrangé wrote:
> > The logic for parsing the multiboot initrd modules was messed up in
> >
> > commit 950c4e6c94b15cd0d8b638917a8dbf458e6a
> > Author: Daniel P. Berrangé
> > Date: Mon
On Mon, 05/21 09:35, Peter Maydell wrote:
> On 21 May 2018 at 07:35, Fam Zheng wrote:
> > Coverity doesn't like the tests under fail label (report CID 1385847).
> > Reset the fields so the clean up order is more apparent.
> >
> > Signed-off-by: Fam Zheng
> > ---
> > block/nvme.c | 7 +++
> >
Coverity doesn't like the tests under fail label (report CID 1385847).
Reset the fields so the clean up order is more apparent.
Signed-off-by: Fam Zheng
---
v2: Don't play stupid. [Peter]
---
block/nvme.c | 4
1 file changed, 4 insertions(+)
diff --git a/block/nvme.c b/block/nvme.c
index
On Mon, May 21, 2018 at 04:42:49PM +0800, Peter Xu wrote:
> We turned Out-Of-Band feature of monitors off for 2.12 release. Now we
> try to turn that on again.
>
> Signed-off-by: Peter Xu
> --
> Now OOB should be okay with all known tests (except iotest qcow2, since
> it is still broken on maste
On 19 May 2018 at 10:29, Laurent Vivier wrote:
> Change conditional #ifdef part by #undef of the symbols
> redefined for PPC relative to generic/socket.h
>
> Signed-off-by: Laurent Vivier
Reviewed-by: Peter Maydell
thanks
-- PMM
On 19 May 2018 at 10:29, Laurent Vivier wrote:
> to be like in the kernel and rename it TARGET_ARCH_HAS_SOCKET_TYPES
You could note in the commit message that this fixes our
incorrect definition of TARGET_SOCK_CLOEXEC for SPARC.
> Signed-off-by: Laurent Vivier
> ---
> linux-user/alpha/sockbits
On 18 May 2018 at 22:57, Richard Henderson wrote:
> With Peter's new patch for "-d fpu", it makes sense to honor
> this setting in as many targets as currently dump the fpu.
>
>
> r~
>
>
> The following changes since commit 5bcf917ee37a5efbef99f091a96db54a5276becb:
>
> Merge remote-tracking bran
If the user doesn't specify a TARGET_LIST they get the current
configuration but with spaces and hilarity ensues. This adds some make
magic to turn the TARGET_LIST back into a comma separated list.
Signed-off-by: Alex Bennée
---
v2
- use common $(SPACE) and $(COMMA) in rules.mak
---
rules.mak
On Mon, May 21, 2018 at 09:59:07AM +0100, Daniel P. Berrangé wrote:
> On Mon, May 21, 2018 at 04:42:49PM +0800, Peter Xu wrote:
> > We turned Out-Of-Band feature of monitors off for 2.12 release. Now we
> > try to turn that on again.
> >
> > Signed-off-by: Peter Xu
> > --
> > Now OOB should be o
Hi Zihan,
On 05/20/2018 10:28 AM, Zihan Yang wrote:
Thank you for posting the patches!
For the next version please add a cover letter so we can discuss cross
patchesideas.
To put each pxb into separate pci domain, we need to reserve enough MCFG space
for each pxb host in the main memory.
R
On 05/20/2018 10:28 AM, Zihan Yang wrote:
QLIST will place the original q35 host bridge at the end of list because it is
added first. Replace it with QTAILQ to make q35 at the first of queue, which
makes it convinient and compatible when there are pxb hosts other than q35 hosts
I have no obje
Hello,
Since version 2.12.0 AF_UNIX socket created for QMP exchange is not
deleted on instance shutdown.
This is due to the fact that function qio_channel_socket_finalize() is
called after qio_channel_socket_close().
Signed-off-by: Pavel Balaev
---
include/qemu/sockets.h | 1 -
io/channel-so
On Wed, May 16, 2018 at 5:36 PM, 858585 jemmy wrote:
> On Tue, May 15, 2018 at 10:54 PM, Paolo Bonzini wrote:
>> On 05/05/2018 16:35, Lidong Chen wrote:
>>> @@ -2635,12 +2637,20 @@ static ssize_t qio_channel_rdma_writev(QIOChannel
>>> *ioc,
>>> {
>>> QIOChannelRDMA *rioc = QIO_CHANNEL_RDMA
On 05/20/2018 10:28 AM, Zihan Yang wrote:
Currently only q35 host bridge us allocated space in MCFG table. To put pxb host
into sepratate pci domain, each of them should have its own configuration space
int MCFG table
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c | 83 +
Changing the IP/IM registers may cause interrupts, so hold the BQL.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Michael Walle
---
target/lm32/gdbstub.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/lm32/gdbstub.c b/target/lm32/gdbstub.c
index cf929dd392..2cdeef8f5e 100644
--- a/ta
I'll send a pull request next week if there are no comments on the
patches.
Michael Walle (2):
lm32: take BQL before writing IP/IM register
target/lm32: hold BQL in gdbstub
target/lm32/gdbstub.c | 4
target/lm32/op_helper.c | 4
2 files changed, 8 insertions(+)
--
2.11.0
Writing to these registers may raise an interrupt request. Actually,
this prevents the milkymist board from starting.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Michael Walle
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
target/lm32/op_helper.c | 4
1 file changed, 4 inser
Changing the IP/IM registers may cause interrupts, so hold the BQL.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Michael Walle
---
target/lm32/gdbstub.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/lm32/gdbstub.c b/target/lm32/gdbstub.c
index cf929dd392..dac9418a2b 100644
--- a/t
Writing to these registers may raise an interrupt request. Actually,
this prevents the milkymist board from starting.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Michael Walle
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
target/lm32/op_helper.c | 4
1 file changed, 4 inser
Whoops, forget the include patch chunk for the second patch.
I'll send a pull request next week if there are no comments on the
patches.
since v1:
add missing #include
Michael Walle (2):
lm32: take BQL before writing IP/IM register
target/lm32: hold BQL in gdbstub
target/lm32/gdbstub.c
On 20 May 2018 at 07:14, Michael Tokarev wrote:
> Hello!
>
> This is a next trivial-patches pull request. It's been a while
> since the last pull, and quite some changes has been accumulated.
>
> Please consider pulling/applying.
>
> Thanks,
>
> /mjt
>
> The following changes since commit 5bcf917e
On 21 May 2018 at 13:21, Michael Walle wrote:
> Changing the IP/IM registers may cause interrupts, so hold the BQL.
>
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Michael Walle
> ---
> target/lm32/gdbstub.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/lm32/gdbstub.c b/ta
On 21 May 2018 at 13:25, Peter Maydell wrote:
> On 21 May 2018 at 13:21, Michael Walle wrote:
>> Changing the IP/IM registers may cause interrupts, so hold the BQL.
>>
>> Cc: qemu-sta...@nongnu.org
>> Signed-off-by: Michael Walle
>> ---
>> target/lm32/gdbstub.c | 5 +
>> 1 file changed, 5 i
Am 2018-05-09 05:46, schrieb Philippe Mathieu-Daudé:
Since not all modelled controllers use the CRC verification (which is
somehow expensive), let the controller have a configurable property
to enable verification.
So far only the Milkymist controller uses it.
This silent the Coverity warning:
On 18/05/2018 21:16, Julian Brown wrote:
On Fri, 18 May 2018 21:50:55 +0200
Marek Vasut wrote:
On 05/18/2018 09:23 PM, Julian Brown wrote:
This patch adds support for a generic MMU-less Nios II board that
can be used e.g. for bare-metal compiler testing. Nios II booting
is also tweaked so th
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate_iommu().
Signed-off-by: Peter Maydell
---
exec.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
index af2b82d154..c3baadc349 10
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to memory_region_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
The callsite in flatview_access_valid() is part of a recursive
loop fl
Implement the missing registers for the TZ MPC.
Signed-off-by: Peter Maydell
---
include/hw/misc/tz-mpc.h | 10 +++
hw/misc/tz-mpc.c | 137 ++-
2 files changed, 144 insertions(+), 3 deletions(-)
diff --git a/include/hw/misc/tz-mpc.h b/include/hw/misc
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell
---
include/exec/exec-all.h | 5 +++--
a
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_get_iotlb_entry().
Signed-off-by: Peter Maydell
---
include/exec/memory.h | 2 +-
exec.c| 2 +-
hw/virtio/vhost.c | 3 ++-
3 files changed, 4 insertions(+), 3 del
Add more detail to the documentation for memory_region_init_iommu()
and other IOMMU-related functions and data structures.
Signed-off-by: Peter Maydell
---
v2->v3 changes:
* minor wording tweaks per Eric's review
* moved the bit about requirements to notify out from the translate
method docs
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_extend_translation().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell
---
exec.c | 15 ++-
1 fil
If an IOMMU supports mappings that care about the memory
transaction attributes, then it no longer has a unique
address -> output mapping, but more than one. We can
represent these using an IOMMU index, analogous to TCG's
mmu indexes.
Signed-off-by: Peter Maydell
---
include/exec/memory.h | 52 +
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_map().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell
---
include/exec/memory.h | 3 ++-
include/sys
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
callback. We'll need this for subpage_accepts().
We could take the approach we used with the read and write
callbacks and add new a new _with_attrs version, but since
For the IoTKit MPC support, we need to wire together the
interrupt outputs of 17 MPCs; this exceeds the current
value of MAX_OR_LINES. Increase MAX_OR_LINES to 32 (which
should be enough for anyone).
The tricky part is retaining the migration compatibility for
existing OR gates; we add a subsectio
The interrupt outputs from the MPC in the IoTKit and the expansion
MPCs in the board must be wired up to the security controller, and
also all ORed together to produce a single line to the NVIC.
Signed-off-by: Peter Maydell
---
include/hw/arm/iotkit.h | 6
hw/arm/iotkit.c | 74
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell
---
include/exec/memory.h | 4 +++-
Add an IOMMU index argument to the translate method of
IOMMUs. Since all of our current IOMMU implementations
support only a single IOMMU index, this has no effect
on the behaviour.
Signed-off-by: Peter Maydell
---
include/exec/memory.h| 3 ++-
exec.c | 11 +--
hw/
Wire up the one MPC that is part of the IoTKit itself. For the
moment we don't wire up its interrupt line.
Signed-off-by: Peter Maydell
---
include/hw/arm/iotkit.h | 2 ++
hw/arm/iotkit.c | 38 +++---
2 files changed, 29 insertions(+), 11 deletions(-)
di
Add support for multiple IOMMU indexes to the IOMMU notifier APIs.
When initializing a notifier with iommu_notifier_init(), the caller
must pass the IOMMU index that it is interested in. When a change
happens, the IOMMU implementation must pass
memory_region_notify_iommu() the IOMMU index that has
The MPC is guest-configurable for whether blocked accesses:
* should be RAZ/WI or cause a bus error
* should generate an interrupt or not
Implement this behaviour in the blocked-access handlers.
Signed-off-by: Peter Maydell
---
hw/misc/tz-mpc.c | 50 +++
Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
and friends.
Signed-off-by: Peter Maydell
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index df463fd33d..59fc75e418 100644
--- a
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_access_valid().
Its callers now all have an attrs value to hand, so we can
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell
---
exec.c | 11 +-
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate()
and address_space_translate_cached(). Callers either have an
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell
---
inclu
Currently we don't support board configurations that put an IOMMU
in the path of the CPU's memory transactions, and instead just
assert() if the memory region fonud in address_space_translate_for_iotlb()
is an IOMMUMemoryRegion.
Remove this limitation by having the function handle IOMMUs.
This is
This patchset is a rather large one, but the first half is all
fairly simple plumbing. It does four things:
* support IOMMUs that are aware of memory transaction attributes and
may generate different translations for different attributes
* support TCG execution out of memory which is behind an
The final part of the Memory Protection Controller we need to
implement is actually using the BLK_LUT data programmed by the
guest to determine whether to block the transaction or not.
Since this means we now change transaction mappings when
the guest writes to BLK_LUT, we must also call the IOMMU
Instantiate and wire up the Memory Protection Controllers
in the MPS2 board itself.
Signed-off-by: Peter Maydell
---
hw/arm/mps2-tz.c | 71 ++--
1 file changed, 44 insertions(+), 27 deletions(-)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 8
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_do_translate().
Signed-off-by: Peter Maydell
---
exec.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
index 84f2c21ecb..af2b82d154 100644
--
Implement the SECMPCINTSTATUS register. This is the only register
in the security controller that deals with Memory Protection
Controllers, and it simply provides a read-only view of the
interrupt lines from the various MPCs in the system.
Signed-off-by: Peter Maydell
---
include/hw/misc/iotkit-
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_translate(); all its
callers now have attrs available.
Signed-off-by: Peter Maydell
---
include/exec/memory.h | 7 ---
exec.c| 17 +
2 files changed,
On 05/21/2018 03:42 AM, Peter Xu wrote:
We turned Out-Of-Band feature of monitors off for 2.12 release. Now we
try to turn that on again.
"try to turn" sounds weak, like you aren't sure of this patch. If you
aren't sure, then why should we feel safe in applying it? This text is
going in th
Implement the Arm TrustZone Memory Protection Controller, which sits
in front of RAM and allows secure software to configure it to either
pass through or reject transactions.
We implement the MPC as a QEMU IOMMU, which will direct transactions
either through to the devices and memory behind it or
On Mon, May 21, 2018 at 02:10:18PM +0300, Pavel Balaev wrote:
> Hello,
>
> Since version 2.12.0 AF_UNIX socket created for QMP exchange is not
> deleted on instance shutdown.
>
> This is due to the fact that function qio_channel_socket_finalize() is
> called after qio_channel_socket_close().
Hmm
On 21/05/2018 16:03, Peter Maydell wrote:
> + * VMState array; devices with more inputs than this need to
> + * migrate the extra lines via a subsection.
> + * The subsection migrates as much of the levels[] array as is needed
> + * (including repeating the first 16 elements), to avoid the awkwardn
On 21 May 2018 at 15:34, Paolo Bonzini wrote:
> Why do the levels have to be migrated at all? It should be enough if
> the IRQ level is either migrated manually, or restored (e.g. in
> post_save callbacks) through other data that is migrated.
This is standard behaviour for devices: they track th
Hi Zihan
On 05/20/2018 10:28 AM, Zihan Yang wrote:
You do have patch 0, sorry for not seeing it, please disregard my prev
comment.
Currently only q35 host bridge is allocated an item in MCFG table, all pxb
host bridges stay within pci domain 0. This series of patches put each pxb
host bridge
Hello,
This is third version of this patch set, rebased on current
master.
As I've received no answers to [1] (and I'd prefer to keep the
patch as is for now if possible) this doesn't include any changes
to address the comments to [2].
If there's anything else I can do to get these patches merge
It's the natural type for object sizes and matches the return value of
sizeof(buf).
Signed-off-by: Simon Ruderich
Reviewed-by: Eric Blake
---
cpus.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpus.c b/cpus.c
index 7fd8d3c32e..49d4d44916 100644
--- a/cpus.c
+++ b/cpu
Signed-off-by: Simon Ruderich
Reviewed-by: Eric Blake
---
cpus.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/cpus.c b/cpus.c
index d1f16296de..4b1609fe90 100644
--- a/cpus.c
+++ b/cpus.c
@@ -2316,8 +2316,9 @@ void qmp_memsave(int64_t addr, int64_t size, const char
The called function takes an uint64_t as size parameter and
qdict_get_int() returns an uint64_t. Don't truncate it needlessly to an
uint32_t.
Signed-off-by: Simon Ruderich
Reviewed-by: Eric Blake
---
hmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hmp.c b/hmp.c
ind
qemu_open() allows passing file descriptors to qemu which is used in
restricted environments like libvirt where open() is prohibited.
Suggested-by: Eric Blake
Signed-off-by: Simon Ruderich
Reviewed-by: Eric Blake
---
cpus.c | 20 ++--
1 file changed, 10 insertions(+), 10 deleti
Adapted patch from Baojun Wang [1] with the following commit message:
I found this could be useful to have qemu-softmmu as a cross
debugger (launch with -s -S command line option), then if we can
have a command to load guest physical memory, we can use cross gdb
to do some target d
Am 2018-05-21 14:25, schrieb Peter Maydell:
On 21 May 2018 at 13:21, Michael Walle wrote:
Changing the IP/IM registers may cause interrupts, so hold the BQL.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Michael Walle
---
target/lm32/gdbstub.c | 5 +
1 file changed, 5 insertions(+)
diff --g
Writing to these registers may raise an interrupt request. Actually,
this prevents the milkymist board from starting.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Michael Walle
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
target/lm32/op_helper.c | 4
1 file changed, 4 inser
The following changes since commit 81e9cbd0ca1131012b058df6804b1f626a6b730c:
lm32: take BQL before writing IP/IM register (2018-05-21 13:37:12 +0200)
are available in the git repository at:
git://github.com/mwalle/qemu.git tags/lm32-queue/20180521
for you to fetch changes up to
On Fri, May 18, 2018 at 04:37:10PM +, Elliott, Robert (Persistent Memory)
wrote:
>
>
> ...
> > Would it help to show them in hex?
> >
> > As of ACPI 6.2 Errata A, the following values are valid for the bottom
> > two bits:
> >
> > 0x2 - Memory Controller Flush to NVDIMM Durability on
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180521140402.23318-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH 00/27] iommu: support txattrs, support TCG
execution, implement TZ MPC
=== TEST SCRIPT BEGIN ===
This is a second attempt at sending this patch:
http://lists.nongnu.org/archive/html/qemu-devel/2018-05/msg04697.html
Signed-off-by: Pavel Balaev
---
io/channel-socket.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/io/channel-socket.c b/io/channel-socke
Changes since v3:
* Updated the text in docs/nvdimm.txt to make it clear that the value
being passed in on the command line in an integer made up of various
bit fields. (Rob Elliott)
* Updated the "Highest Valid Capability" byte to be dynamic based on
the highest valid bit in the user'
Add testing for the newly added NFIT Platform Capabilities Structure.
Signed-off-by: Ross Zwisler
Suggested-by: Igor Mammedov
---
tests/acpi-test-data/pc/NFIT.dimmpxm | Bin 224 -> 240 bytes
tests/acpi-test-data/q35/NFIT.dimmpxm | Bin 224 -> 240 bytes
tests/bios-tables-test.c |
After a "make check" we end up with the following:
$ git status
On branch master
Your branch is up-to-date with 'origin/master'.
Untracked files:
(use "git add ..." to include in what will be committed)
tests/test-block-backend
nothing added to commit but untracked files present (use
Signed-off-by: Ross Zwisler
Fixes: commit da6789c27c2e ("nvdimm: add a macro for property "label-size"")
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Igor Mammedov
Cc: Haozhong Zhang
Cc: Michael S. Tsirkin
Cc: Stefan Hajnoczi
---
hw/mem/nvdimm.c | 2 +-
include/hw/mem/nvdimm.h | 2 +-
2
Add a machine command line option to allow the user to control the Platform
Capabilities Structure in the virtualized NFIT. This Platform Capabilities
Structure was added in ACPI 6.2 Errata A.
Signed-off-by: Ross Zwisler
---
docs/nvdimm.txt | 27 +++
hw/acpi/nvdi
Hello,
It's been about a week since the last email to my patches, in case anyone would
like to review but missed them.
Patches are the following on patchwork:
http://patchwork.ozlabs.org/patch/912281/
http://patchwork.ozlabs.org/patch/912282/
And the following on patchew:
http://patchew.org/QEMU
On 05/21/2018 11:32 AM, Ross Zwisler wrote:
After a "make check" we end up with the following:
$ git status
On branch master
Your branch is up-to-date with 'origin/master'.
Untracked files:
(use "git add ..." to include in what will be committed)
tests/test-block-backend
nothing ad
Hi Alistair, Fam,
On 05/21/2018 12:16 AM, Fam Zheng wrote:
> On Fri, 05/18 11:34, Alistair Francis wrote:
>> Avocado is not trivial to setup on non-Fedora systems. To simplfying
>> future testing add a docker test image that runs Avocado tests.
Can you add an entry in the "make docker" help menu?
The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't
On 05/21/2018 01:41 PM, Eric Blake wrote:
> On 05/21/2018 11:32 AM, Ross Zwisler wrote:
>> After a "make check" we end up with the following:
>>
>> $ git status
>> On branch master
>> Your branch is up-to-date with 'origin/master'.
>>
>> Untracked files:
>> (use "git add ..." to include in what
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180519092956.15134-1-laur...@vivier.eu
Subject: [Qemu-devel] [PATCH v3 0/8] linux-user: move socket.h definitions to
CPU directories
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On Fri, May 18, 2018 at 10:48:31AM +0200, Markus Armbruster wrote:
> Cc'ing a few more people.
>
> Daniel Henrique Barboza writes:
>
> > When issuing the qmp/hmp 'system_wakeup' command, what happens in a
> > nutshell is:
> >
> > - qmp_system_wakeup_request set runstate to RUNNING, sets a wakeup
On 05/21/2018 12:32 PM, Philippe Mathieu-Daudé wrote:
tests/test-block-backend
+test-block-backend
test-blockjob
test-blockjob-txn
test-bufferiszero
What about using gitignore negated pattern in tests/?
Or, what we've threatened to do in the past: rename all unit tests to
On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote:
> Eduardo Habkost writes:
>
> [...]
> > About being more expressive than just a single list of key,value
> > pairs, I don't see any evidence of that being necessary for the
> > problems we're trying to address.
>
> Short history
On Mon, May 21, 2018 at 03:29:28PM -0300, Eduardo Habkost wrote:
> On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote:
> > Eduardo Habkost writes:
> >
> > [...]
> > > About being more expressive than just a single list of key,value
> > > pairs, I don't see any evidence of that bein
On Mon, May 21, 2018 at 07:44:40PM +0100, Daniel P. Berrangé wrote:
> On Mon, May 21, 2018 at 03:29:28PM -0300, Eduardo Habkost wrote:
> > On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote:
> > > Eduardo Habkost writes:
> > >
> > > [...]
> > > > About being more expressive than ju
ttp/people/sstabellini/qemu-dm.git
tags/xen-20180521-tag
for you to fetch changes up to f03df99f09ee0ca27ea2298a1b77438e7999044d:
xen_disk: be consistent with use of xendev and blkdev->xendev (2018-05-18
11:13:01 -0700)
X
From: Ross Lagerwall
The full size of the BAR is stored in the lower PCIIORegion.size. The
upper PCIIORegion.size is 0. Calculate the size of the upper half
correctly from the lower half otherwise the size read by the guest will
be incorrect.
Signed-off-by: Ross Lagerwall
Acked-by: Anthony PER
From: Paul Durrant
This patch adds grant table helper functions to the xen_backend code to
localize error reporting and use of xen_domid.
The patch also defers the call to xengnttab_open() until just before the
initialise method in XenDevOps is invoked. This method is responsible for
mapping the
From: Igor Druzhinin
This should help to avoid problems with accessing the device after
migration/resume without PV drivers by migrating its PCI configuration
space state. Without an explicitly defined state record it resets
every time a VM migrates which confuses the OS and makes every
access to
From: Paul Durrant
Not all Xen environments support the xengnttab_grant_copy() operation.
E.g. where the OS is FreeBSD or Xen is older than 4.8.0.
This patch introduces an emulation of that operation using
xengnttab_map_domain_grant_refs() and memcpy() for those environments.
Signed-off-by: Pau
From: Igor Druzhinin
Commit 99605175c (xen-pt: Fix PCI devices re-attach failed) introduced
a subtle bug. As soon as the guest switches off Bus Mastering on the
device it immediately causes all the BARs be unmapped due to the DMA
address space of the device being changed. This is undesired behavi
From: Paul Durrant
The code is sufficiently substantial that it improves code readability
to put it in a new function called by xen_hvm_init() rather than having
it inline.
Signed-off-by: Paul Durrant
Reviewed-by: Anthony Perard
Signed-off-by: Stefano Stabellini
---
hw/i386/xen/xen-hvm.c | 7
From: Paul Durrant
There is no longer any use of this flag outside of the xen_backend code.
Signed-off-by: Paul Durrant
Acked-by: Anthony Perard
Signed-off-by: Stefano Stabellini
---
hw/xen/xen_backend.c | 2 +-
include/hw/xen/xen_backend.h | 1 -
2 files changed, 1 insertion(+), 2 d
From: Paul Durrant
Currently the xen_disk source has to carry #ifdef exclusions to compile
against Xen older then 4.8. This is a bit messy so this patch lifts the
definition of struct xengnttab_grant_copy_segment and adds it into the
pre-4.8 compat area in xen_common.h, which allows xen_disk to b
From: Paul Durrant
Since xen_disk now always copies data to and from a guest there is no need
to maintain a vector entry corresponding to every page of a request.
This means there is less per-request state to maintain so the ioreq
structure can shrink significantly.
Signed-off-by: Paul Durrant
From: Paul Durrant
xen_handle
and some define additional handle types of the form:
xen__handle
Examples of these are xenforeignmemory_handle and
xenforeignmemory_resource_handle.
Both of these types will be misparsed by checkpatch if they appear as the
first token in a line since, as types de
From: Paul Durrant
Now that helpers are available in xen_backend, use them throughout all
Xen PV backends.
Signed-off-by: Paul Durrant
Acked-by: Anthony Perard
Signed-off-by: Stefano Stabellini
---
hw/9pfs/xen-9p-backend.c | 32 +++-
hw/char/xen_console.c| 9
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