On 04.02.2018 07:49, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tests/boot-serial-test.c | 1 +
> tests/Makefile.include | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
> index 418c5b92dc..ea87a80be7 10064
On Sun, Feb 4, 2018 at 5:11 AM, Richard Henderson
wrote:
> As discussed on list, the structure and inline function solution that
> Alex and I have been writing from scratch introduces a sizeable
> performance regression. Alex and I have done some work earlier
> in the week that improved things so
Richard Henderson writes:
> Reported-by: Thomas Huth
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
> ---
> hw/hppa/machine.c | 17 -
> 1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
> index afd3867313..19
On 4 February 2018 at 04:11, Richard Henderson
wrote:
> Or there's the code from glibc. I know Peter didn't like the idea;
> debugging this code is fairly painful -- the massive preprocessor
> macros mean that you can't step through anything. But at least we
> have a good relationship with glibc
On 1 February 2018 at 14:23, Paolo Bonzini wrote:
> On 01/02/2018 08:47, Gonglei wrote:
>> diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
>> index 35a05a6..d9d99c5 100644
>> --- a/hw/timer/mc146818rtc.c
>> +++ b/hw/timer/mc146818rtc.c
>> @@ -986,6 +986,7 @@ static void rtc_realizefn(
On Tue, Jan 9, 2018 at 3:31 AM, Christoph Hellwig wrote:
> On Wed, Jan 03, 2018 at 01:44:15PM +1300, Michael Clark wrote:
> > HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
> > allows identical copies of BBL (Berkeley Boot Loader) and linux to run
> > on both Spike and QEM
Consider that data is always immediately sent. As a result, keep
the SR_TXE and SR_TC bits always set. In addition, fix the reset value
of the USART status register.
Signed-off-by: Richard Braun
---
hw/char/stm32f2xx_usart.c | 4
include/hw/char/stm32f2xx_usart.h | 7 ++-
2 file
On Fri, Jan 12, 2018 at 7:43 AM, Michael Clark wrote:
>
>
> On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake wrote:
>
>> On 01/10/2018 08:22 PM, Michael Clark wrote:
>> > This adds RISC-V into the build system enabling the following targets:
>> >
>> > - riscv32-softmmu
>> > - riscv64-softmmu
>> > - r
On Mon, Feb 05, 2018 at 09:19:46AM +1300, Michael Clark wrote:
> BTW I've created branches in my own personal trees for Privileged ISA
> v1.9.1. These trees are what I use for v1.9.1 backward compatibility
> testing in QEMU:
>
> - https://github.com/michaeljclark/riscv-linux/tree/riscv-linux-4.6.2
On Thu, Jan 25, 2018 at 9:57 PM, Tiwei Bie wrote:
> On Fri, Jan 26, 2018 at 11:41:27AM +0800, Jason Wang wrote:
>> On 2018年01月26日 07:59, Michael S. Tsirkin wrote:
>> > > The virtual IOMMU isn't supported by the accelerators for now.
>> > > Because vhost-user currently lacks of an efficient way to
Reviewed-by: Thomas Huth
Signed-off-by: Richard Henderson
---
tests/boot-serial-test.c | 1 +
tests/Makefile.include | 2 ++
2 files changed, 3 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index 418c5b92dc..ea87a80be7 100644
--- a/tests/boot-serial-test.c
+++
Reviewed-by: Alex Bennée
Reported-by: Thomas Huth
Signed-off-by: Richard Henderson
---
hw/hppa/machine.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index afd3867313..19033e268d 100644
--- a/hw/hppa/machine.c
+++ b/
at:
git://github.com/rth7680/qemu.git tags/pull-hppa-20180204
for you to fetch changes up to edf90bd0af98bf03ec1e60e5c7632774f62837d8:
roms/seabios-hppa: Update submodule and image (2018-02-04 14:11:18 -0800)
hppa-soft
On Mon, Feb 5, 2018 at 10:29 AM, Christoph Hellwig wrote:
> On Mon, Feb 05, 2018 at 09:19:46AM +1300, Michael Clark wrote:
> > BTW I've created branches in my own personal trees for Privileged ISA
> > v1.9.1. These trees are what I use for v1.9.1 backward compatibility
> > testing in QEMU:
> >
>
QEMU RISC-V Emulation Support (RV64GC, RV32GC)
This patch series contains a number of bug fixes and code cleanups
incorporates changes from Richard Henderson's tree:
- https://github.com/rth7680/qemu/tree/tgt-riscv
The git tree for this v4 patch series (squashed and rebased):
- https://github.c
On 02/02/18 18:37, Markus Armbruster wrote:
> Alexey Kardashevskiy writes:
>
>> On 01/02/18 04:22, Markus Armbruster wrote:
>>> Alexey Kardashevskiy writes:
>>>
There is already 'device-list-properties' which does most of the job,
however it does not handle everything returned by qom-l
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1736655
Title:
2k3/xp gues
[Expired for qemu (Ubuntu) because there has been no activity for 60
days.]
** Changed in: qemu (Ubuntu)
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1736655
Ti
Quoting Fam Zheng (2018-02-02 00:34:11)
> git-publish [1] is a convenient tool to send patches and has been
> popular among QEMU developers. Recently it has been made available in
> Fedora official repo thanks to Stefan's work.
>
> One nice feature of the tool is a per-project configuration with
Quoting Fam Zheng (2018-02-02 00:34:12)
> Signed-off-by: Fam Zheng
> ---
> .gitpublish | 1 +
> README | 30 +-
> 2 files changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/.gitpublish b/.gitpublish
> index 170bd2ed48..7542e878fc 100644
> --- a/.gitpublis
git-publish [1] is a convenient tool to send patches and has been
popular among QEMU developers. Recently it has been made available in
Fedora official repo thanks to Stefan's work.
One nice feature of the tool is a per-project configuration with
profiles, especially in which the cccmd option is
v3: Fix trivial hunk placement. [Michael]
Fix PPC sub-list. [Michael]
v2: Add README paragraph [Marc-André, Stefan]
Fix 'trivial' profile [Marc-André]
Rename profiles [Stefan]
Fam Zheng (2):
Add a git-publish configuration file
README: Document 'git-publish' workflow
.gitpublish
Signed-off-by: Fam Zheng
---
README | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/README b/README
index b92a07a61a..d1a944ce20 100644
--- a/README
+++ b/README
@@ -56,7 +56,7 @@ The QEMU source code is maintained under the GIT version
control
Marc-André Lureau writes:
> Suggested-by: Markus Armbruster
> Signed-off-by: Marc-André Lureau
> ---
> include/qapi/qmp/qlit.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/qapi/qmp/qlit.h b/include/qapi/qmp/qlit.h
> index b18406bce9..0c6809ef3c 100644
> ---
Marc-André Lureau writes:
> Accept 'if' key in top-level elements, accepted as string or list of
> string type. The following patches will modify the test visitor to
> check the value is correctly saved, and generate #if/#endif code (as a
> single #if/endif line or a series for a list).
>
> Examp
Hello Radim,
+-- On Fri, 2 Feb 2018, Radim Krčmář wrote --+
| This should primarily go to the qemu devel list. I've Cc'd it, but
| reposting would be safer, thanks.
Ah, Okay. I did think qemu-devel would be better, but MAINTAINERS file lists
k...@vger.kernel.org address for accel/kvm/.
Tha
Marc-André Lureau writes:
> Built-in objects remain unconditional. Explicitly defined objects
> use the condition specified in the schema. Implicitly defined
> objects inherit their condition from their users. For most of them,
> there is exactly one user, so the condition to use is obvious.
From: Prasad J Pandit
When updating message signalled interrupt(MSI) route in routine
kvm_irqchip_update_msi_route, device parameter could be null.
Add check to avoid null dereference.
Reported-by: Guoxiang Niu
Signed-off-by: Prasad J Pandit
---
accel/kvm/kvm-all.c | 4 ++--
1 file changed, 2
Marc-André Lureau writes:
> We commonly initialize attributes to None in .init(), then set their
> real value in .check(). Accessing the attribute before .check()
> yields None. If we're lucky, the code that accesses the attribute
> prematurely chokes on None.
>
> It won't for .ifcond, because
GDB Register read and write routines.
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/gdbstub.c | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@ type
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.
Signed-off-by: Michael Clark
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0f952d4..d607039 100644
--- a/MAINTAINERS
+++ b/MAINTAIN
Helper routines for FPU instructions and NaN definitions.
Signed-off-by: Michael Clark
---
fpu/softfloat-specialize.h | 7 +-
target/riscv/fpu_helper.c | 375 +
2 files changed, 379 insertions(+), 3 deletions(-)
create mode 100644 target/riscv/fpu_
Add CPU state header, CPU definitions and initialization routines
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 385
target/riscv/cpu.h | 256 +
target/riscv/cpu_bits.h | 417 ++
Privileged control and status register helpers and page fault handling.
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 464 ++
target/riscv/helper.h| 78 ++
target/riscv/op_helper.c | 644 +++
3 fil
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
RISC-V code generator has complete coverage for the Base ISA v2.2,
Privileged ISA v1.9.1 and Privileged ISA v1.10:
- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privile
The RISC-V disassembler has no dependencies outside of the 'disas'
directory so it can be applied independently. The majority of the
disassembler is machine-generated from instruction set metadata:
- https://github.com/michaeljclark/riscv-meta
Expected checkpatch errors for consistency and brevit
Holds the state of a heterogenous array of RISC-V hardware threads.
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 95 +++
include/hw/riscv/riscv_hart.h | 45
2 files changed, 140 insertions(+)
create mode 100644 hw/
This provides a RISC-V Board compatible with the the SiFive E300 SDK.
The following machine is implemented:
- 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e300.c | 232 +
include/hw/riscv/
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 312
include/hw/riscv/sifive_clint.h | 56 ++
This provides a RISC-V Board compatible with the the SiFive U500 SDK.
The following machine is implemented:
- 'sifive_u500'; CLINT, PLIC, UART, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/sifive_u500.c | 338 +
include/hw/riscv/sifive_u5
Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.
PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
The SiFive verification team have PMP test cases that will be run.
Nothing currently depends on PMP support. It would be prefera
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 554 +
include/hw/riscv/sifive_plic.h | 91 ++
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 375
include/hw/riscv/virt
This adds RISC-V into the build system enabling the following targets:
- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user
This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
scri
Implementation of linux user emulation for RISC-V.
Signed-off-by: Michael Clark
---
linux-user/elfload.c | 22 +++
linux-user/main.c | 97 ++
linux-user/riscv/syscall_nr.h | 275 ++
linux-user/riscv/target_cpu.h
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.
The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/seri
On Mon, 29 Jan 2018 13:23:50 -0700
Alex Williamson wrote:
> These quirks are necessary for GeForce, but not for Quadro/GRID/Tesla
> assignment. Leaving them enabled is fully functional and provides the
> most compatibility, but due to the unique NVIDIA MSI ACK behavior[1],
> it also introduces l
Test finisher memory mapped device used to exit simulation.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_test.c | 99 ++
include/hw/riscv/sifive_test.h | 48
2 files changed, 147 insertions(+)
create mode 100644 hw/riscv/s
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
allows identical copies of BBL (Berkeley Boot Loader) and linux to run
on both Spike and QEMU. BBL provides HTIF console access via the
SBI (Supervisor Binary Interface) and the linux kernel SBI console.
The HTIF interface read
Thomas Huth writes:
> On 03.02.2018 09:43, Markus Armbruster wrote:
>> From: Alistair Francis
>>
>> Convert fprintf(stderr, ...) to use qemu_log(). Double prints in
>> target/ppc/translate.c were manually remove. A fprintf() in
>> target/sh4/translate.c was kept as it's inside a #if 0. The #if
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:
- 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10
Signed-off-by: Mi
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_prci.c | 95 ++
include/hw/riscv/sifive_prci.h | 43 +++
2 files changed, 138
Thomas Huth writes:
> On 02.02.2018 19:37, Markus Armbruster wrote:
>> From: Alistair Francis
>>
>> Replace a large number of the fprintf(stderr, "*\n" calls with
>> error_report(). The functions were renamed with these commands and then
>> compiler issues where manually fixed.
>>
>> find ./*
On 05.02.2018 07:33, Markus Armbruster wrote:
> Thomas Huth writes:
>
>> On 03.02.2018 09:43, Markus Armbruster wrote:
>>> From: Alistair Francis
>>>
>>> Convert fprintf(stderr, ...) to use qemu_log(). Double prints in
>>> target/ppc/translate.c were manually remove. A fprintf() in
>>> target/sh
Marc-André Lureau writes:
> Add helpers to wrap generated code with #if/#endif lines.
>
> Add a function decorator that will be used to wrap visitor methods.
> The decorator will check if code was generated before adding #if/#endif
> lines. Used in the following patches.
>
> Signed-off-by: Marc-A
This series contains three patches,
1) optimizes the code including walking DMA tables and rpcit handler
2) fixes the issue caused by IOTLB global refresh
3) uses the right pal and pba when registering ioat
The issue mentioned above was found when we tested SMC-r tools. This
behavior has been intr
The VFIO common code doesn't provide the possibility to modify a
previous mapping entry in another way than unmapping and mapping again
with new properties.
To avoid -EEXIST DMA mapping error, we introduce a GHashTable to store
S390IOTLBEntry instances in order to cache the mapped entries. When
in
Current s390x PCI IOMMU code is lack of flags' checking, including:
1) protection bit
2) table length
3) table offset
4) intermediate tables' invalid bit
5) format control bit
This patch introduces a new struct named S390IOTLBEntry, and makes up
these missed checkings. At the same time, inform the
When registering ioat, pba should be comprised of leftmost 52 bits and
rightmost 12 binary zeros, and pal should be comprised of leftmost 52
bits and right most 12 binary ones. The lower 12 bits of words 5 and 7
of the FIB are ignored by the facility. Let's fixup this.
Reviewed-by: Pierre Morel
S
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