From: Manos Pitsidianakis
BlockDriverState has a bdrv_co_drain() callback but no equivalent for
the end of the drain. The throttle driver (block/throttle.c) needs a way
to mark the end of the drain in order to toggle io_limits_disabled
correctly, thus bdrv_co_drain_end is needed.
Signed-off-by:
Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.
Multicore support is now being added so these registers need to have
configured values.
Signed-off-by: Stafford Horne
---
target/openrisc/sys_helper.c | 5 +++--
1 file change
The following changes since commit f90ea7ba7c5ae7010ee0ce062207ae42530f57d6:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171012'
into staging (2017-10-12 17:06:50 +0100)
are available in the git repository at:
git://github.com/stefanha/qemu.git tags/block-pull-requ
From: Manos Pitsidianakis
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Fam Zheng
Signed-off-by: Manos Pitsidianakis
Signed-off-by: Stefan Hajnoczi
---
block/throttle.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/block/throttle.c b/block/throttle.c
index 5bca76300f..8
Add OpenRISC Multicore PIC which handles inter processor interrupts
(IPI) between cores. In OpenRISC all device interrupts are routed to
each core enabling this device to be simple.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
default-configs/or1k-softmmu.mak | 1 +
hw/in
From: Manos Pitsidianakis
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Fam Zheng
Signed-off-by: Manos Pitsidianakis
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Stefan Hajnoczi
---
include/block/block_int.h | 4 ++--
block/io.c| 4 ++--
block/qed.c | 6 +++---
3 fi
In order to support multicore system we move some of the previously
static state variables into the state of each core.
On the other hand in order to allow timers to be synced between each
code the ttcr (tick timer count register) is moved out of the core.
This is not as per real hardware spec whi
On Mon 02 Oct 2017 04:33:32 PM CEST, Pradeep Jagadeesh wrote:
> This patch introduces hmp interfaces for the fsdev
> devices.
>
> Signed-off-by: Pradeep Jagadeesh
> Reviewed-by: Dr. David Alan Gilbert
> Reviewed-by: Alberto Garcia
It seems that you changed this patch since the last time I revie
Previously we were kicking the cpu on every update. This caused
problems noticeable in SMP configurations where one CPU got pinned
continuously servicing timer exceptions.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 2 +-
1 file changed, 1 insertio
Hello,
This series adds SMP support for OpenRISC. The platform is based on the
work that Stefan Kristiansson did around 2012 implemented in Verilog and
run on FPGAs. I have been working to upstream this work, these are my QEMU
patches I have been used to help with testing.
I have documented the
Wire in ompic and add basic support for SMP. The OpenRISC is special in
that interrupts for devices are routed to each core's PIC. This is
achieved using the qemu_irq_split utility, but this currently limits
OpenRISC to 2 cores.
This models the reference architecture described in the OpenRISC sp
On 10/13/2017 06:49 AM, Stafford Horne wrote:
> Previously coreid and numcores were hard coded as 0 and 1 respectively
> as OpenRISC QEMU did not have multicore support.
>
> Multicore support is now being added so these registers need to have
> configured values.
>
> Signed-off-by: Stafford Horne
On Mon 02 Oct 2017 04:33:28 PM CEST, Pradeep Jagadeesh wrote:
> This patch factors out code to use the ThrottleLimits
> structure.
> { 'struct': 'BlockIOThrottle',
> - 'data': { '*device': 'str', '*id': 'str', 'bps': 'int', 'bps_rd': 'int',
> -'bps_wr': 'int', 'iops': 'int', 'iops_rd
Hi,
I'm trying to convert some images from raw to vmdk to run in a ESXi6.5
server but I need to rectify the image before being able to run.
The scenario goes like that:
qemu-img convert -f raw image.raw -O vmdk -o compat6 image.vmdk
ESXi complains with "Failed - File system specific implement
[adding Markus, and block list]
On 10/13/2017 09:16 AM, Alberto Garcia wrote:
> On Mon 02 Oct 2017 04:33:28 PM CEST, Pradeep Jagadeesh wrote:
>> This patch factors out code to use the ThrottleLimits
>> structure.
>
>> { 'struct': 'BlockIOThrottle',
>> - 'data': { '*device': 'str', '*id': 'str',
On Mon 02 Oct 2017 04:33:29 PM CEST, Pradeep Jagadeesh wrote:
> -if (arg->has_iops_rd_max_length) {
> -cfg.buckets[THROTTLE_OPS_READ].burst_length =
> arg->iops_rd_max_length;
> -}
> -if (arg->has_iops_wr_max_length) {
> -cfg.buckets[THROTTLE_OPS_WRITE].burst_length =
The Witherspoon boards are OpenPOWER system hosting POWER9 Processors.
Let's add support for their BMC including a couple of I2C devices as
found on real HW.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
---
Changes since v2:
- removed 'ignore_memory_transaction_failures' flag
The pca9552 LED blinkers on the Witherspoon machine are used for leds
but also as GPIOs to control fans and GPUs.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
---
hw/arm/aspeed.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 2a6ca
On Fri, Oct 13, 2017 at 06:58:21AM -0700, Richard Henderson wrote:
> On 10/13/2017 06:49 AM, Stafford Horne wrote:
> > Previously coreid and numcores were hard coded as 0 and 1 respectively
> > as OpenRISC QEMU did not have multicore support.
> >
> > Multicore support is now being added so these r
The AST2500 EVB does not have an RTC but we can pretend that one is
plugged on the I2C bus header.
The romulus and witherspoon boards expects an Epson RX8900 I2C RTC but
a ds1338 is good enough for the basic features we need.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
---
hw/a
Hello,
This series adds a new Aspeed machine to emulate the BMC of a
Witherspoon system. It also extends the other Aspeed machines with I2C
devices and adds a simple model for the pca9552 LED blinker present on
the witherspoon board.
Thanks,
C.
Changes since v2:
- removed comments on the I2C
The Aspeed boards have at least one EEPROM to hold the Vital Product
Data (VPD).
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
---
hw/arm/aspeed.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 032fd61d452f..2a6ca58527f8
This is an helper routine to add a single EEPROM on an I2C bus. It can
be directly used by smbus_eeprom_init() which adds a certain number of
EEPROMs on mips and x86 machines.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i2c/smbus_eeprom.c | 16 +++-
i
Specs are available here :
https://www.nxp.com/docs/en/data-sheet/PCA9552.pdf
This is a simple model supporting the basic registers for led and GPIO
mode. The device also supports two blinking rates but not the model
yet.
Signed-off-by: Cédric Le Goater
---
Changes since v2:
- removed com
Hello,
Please consider for pull.
The following changes since commit 7851197b812b383ae1208c5d86391c5179c8209d:
Update version for 2.10.1 release (2017-10-02 12:42:58 -0500)
are available in the git repository at:
git://github.com/stffrdhrn/qemu.git tags/openrisc-20171113-smp-pr
for you to
Add OpenRISC Multicore PIC which handles inter processor interrupts
(IPI) between cores. In OpenRISC all device interrupts are routed to
each core enabling this device to be simple.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
default-configs/or1k-softmmu.mak | 1 +
hw/in
Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.
Multicore support is now being added so these registers need to have
configured values.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
target/openrisc/sys_h
In order to support multicore system we move some of the previously
static state variables into the state of each core.
On the other hand in order to allow timers to be synced between each
code the ttcr (tick timer count register) is moved out of the core.
This is not as per real hardware spec whi
Wire in ompic and add basic support for SMP. The OpenRISC is special in
that interrupts for devices are routed to each core's PIC. This is
achieved using the qemu_irq_split utility, but this currently limits
OpenRISC to 2 cores.
This models the reference architecture described in the OpenRISC sp
Previously we were kicking the cpu on every update. This caused
problems noticeable in SMP configurations where one CPU got pinned
continuously servicing timer exceptions.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 2 +-
1 file changed, 1 insertio
On Fri, Oct 13, 2017 at 2:44 AM, Stefan Hajnoczi wrote:
> On Thu, Oct 12, 2017 at 09:20:26PM +0530, Pankaj Gupta wrote:
[..]
>> +#ifndef REQ_FLUSH
>> +#define REQ_FLUSH REQ_PREFLUSH
>> +#endif
>
> Is this out-of-tree kernel module compatibility stuff that can be
> removed?
Yes, this was copied fr
On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
> Minimal implementation of structured read: one structured reply chunk,
> no segmentation.
> Minimal structured error implementation: no text message.
> Support DF flag, but just ignore it, as there is no segmentation any
> way.
>
> Sign
On 13 October 2017 at 08:00, Gerd Hoffmann wrote:
> On Thu, 2017-10-12 at 16:25 -0400, hanji unit wrote:
>> Hello, is it possible to run (or rebuild modifying build flags) QEMU
>> without support for X11 window system integration?
>
> ./configure --disable-gtk --disable-sdl --disable-opengl
You c
On 13 October 2017 at 12:14, Marc-André Lureau
wrote:
> Hi
>
> On Wed, Oct 11, 2017 at 9:47 PM, Stefan Berger
> wrote:
>> EBADMSG was only added to OpenBSD very recently. To make QEMU compilable
>> on older OpenBSD versions use EMSGSIZE instead when a mismatch between
>> number of received bytes
On 13 October 2017 at 12:46, Thomas Huth wrote:
> I disagree. If the next OpenBSD release uses Clang by default, we're not
> building QEMU there with the *working default* C compiler anymore.
> You're then rather forcing the OpenBSD users then to install an
> additional (likely unliked, since GPLv
On 10/13/2017 11:00 AM, Eric Blake wrote:
> On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
>> Minimal implementation of structured read: one structured reply chunk,
>> no segmentation.
>> Minimal structured error implementation: no text message.
>> Support DF flag, but just ignore it,
Hi,
I am new to the alias. I have some questions on this subject
and seek some clarifications from the experts in the team.
I ran into a couple of issues when I tried with large configuration
( >= 1TB memory, > 255 CPUs) for x86_64 guest machine.
1. QEMU uses the default value of 40 (TCG_PHYS_AD
On 13 October 2017 at 13:51, Laszlo Ersek wrote:
> Another idea is to move *the* system DRAM base to a different guest-phys
> address. (Likely using a different version of the "virt" machine type,
> or even a different machine type entirely.) This would not be compatible
> with current ArmVirtQemu
13.10.2017 19:00, Eric Blake wrote:
On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
Minimal implementation of structured read: one structured reply chunk,
no segmentation.
Minimal structured error implementation: no text message.
Support DF flag, but just ignore it, as there is no se
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3a0f27c782..521b82d46e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -488,6 +488,7 @@ typedef struct CPUARMState {
* Qn = regs[2n+1]:r
---
target/arm/cpu.h | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 89d49cdcb2..3a0f27c782 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1340,6 +1340,7 @@ enum arm_features {
ARM_FEATURE_VBAR, /* has cp15
Signed-off-by: Alex Bennée
---
linux-user/main.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index 829f974662..5072aa855b 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3854,6 +3854,11 @@ static void handle_arg_log(const char *arg)
Hi,
This is the current state of ARM v8.2 half precision operations. There
are two halves to this effort, expanding our copy of softfloat to
include the requisite operations and then plumbing in the appropriate
helpers and tcg generation code into the ARM front end.
I'm posting this today as I wa
This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.
Signed-off-by: Alex Bennée
---
include/exec/helper-head.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/includ
Mention the pseudo-code fragment from which this is based and correct
the spelling of signalling.
Signed-off-by: Alex Bennée
---
fpu/softfloat-specialize.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index
Expand the current helpers to include half-precision functions. The
includes having f16 version of the compare functions.
Signed-off-by: Alex Bennée
---
fpu/softfloat.c | 2 ++
include/fpu/softfloat.h | 11 +++
2 files changed, 13 insertions(+)
diff --git a/fpu/softfloat.c b/fp
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.
Signed-off-by: Alex Bennée
---
fpu/softfloat.c | 15 +++
include/fpu/softfloat.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 433c5
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.
Signed-off-by: Alex Bennée
---
include/fpu/softfloat.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index d5e99667b6..edf402d422 100644
--
While a comparison between a QNaN and a number will return the number
it is not the same with a signaling NaN. In this case the SNaN will
"win" and after potentially raising an exception it will be quietened.
Signed-off-by: Alex Bennée
---
fpu/softfloat.c | 8 ++--
1 file changed, 6 insertio
This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).
Signed-off-by: Alex Bennée
--
v1
- dropped the advsimd_2a stuff
---
target/ar
Signed-off-by: Alex Bennée
---
target/arm/helper-a64.c| 18 ++
target/arm/helper-a64.h| 1 +
target/arm/translate-a64.c | 45 +++--
3 files changed, 54 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/ar
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.
Signed-off-by: Alex Bennée
---
fpu/softfloat-specialize.h | 43 +++
1 file changed, 43 insertions(+)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-spec
Signed-off-by: Alex Bennée
---
target/arm/helper-a64.c| 14 +++---
target/arm/helper-a64.h| 1 -
target/arm/translate-a64.c | 3 +++
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index b62d77aec4..137866732d 100
Rather than following the SoftFloat3 implementation I've used the same
basic template as the rest of our softfloat code. One minor difference
is the 32bit intermediates end up with the binary point in the same
place as the 32 bit version so the change isn't totally mechanical.
Signed-off-by: Alex
On Fri, Oct 13, 2017 at 05:18:59PM +0100, Peter Maydell wrote:
> On 13 October 2017 at 13:51, Laszlo Ersek wrote:
> > Another idea is to move *the* system DRAM base to a different guest-phys
> > address. (Likely using a different version of the "virt" machine type,
> > or even a different machine
We do implement all the opcodes.
Signed-off-by: Alex Bennée
---
target/arm/translate-a64.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1282d14c58..50e53bf8b0 100644
--- a/target/arm/translate-a64.c
+++ b/targ
On Fri, Oct 13, 2017 at 1:54 AM, Igor Mammedov wrote:
> On Thu, 12 Oct 2017 17:07:23 -0700
> Alistair Francis wrote:
>
>> There are numorous QEMU machines that only have a single or a handful of
>> valid CPU options. To simplyfy the management of specificying which CPU
>> is/isn't valid let's cre
This is a simple pattern based framework for testing our softfloat
implementation. It is easier to use while debugging softfloat itself
than indirectly with a tool like risu.
As the softfloat library is built against given targets we need a
version per target architecture we build.
Signed-off-by:
13.10.2017 19:15, Eric Blake wrote:
On 10/13/2017 11:00 AM, Eric Blake wrote:
On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
Minimal implementation of structured read: one structured reply chunk,
no segmentation.
Minimal structured error implementation: no text message.
Support DF
I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.
Signed-off-by: Alex Bennée
---
target/arm/helper-a64.c| 39 +++
target/arm/helper-a64.h| 6 ++
target/arm/translate-a64.c | 25 +++
Signed-off-by: Alex Bennée
---
fpu/softfloat-specialize.h | 52 +++
fpu/softfloat.c| 327 +
include/fpu/softfloat.h| 2 +
3 files changed, 381 insertions(+)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
ind
Signed-off-by: Alex Bennée
---
tests/test-softfloat.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/tests/test-softfloat.c b/tests/test-softfloat.c
index d7b740e1cb..e1f356572d 100644
--- a/tests/test-softfloat.c
+++ b/tests/test-softfloat.c
@@ -16,6 +16,31 @@ ty
This is mostly a mechanical conversion of the float32 variants of the
same name with some judicious search/replace and some constants
changed.
Signed-off-by: Alex Bennée
---
fpu/softfloat.c | 216
include/fpu/softfloat.h | 8 ++
2 files
This is just the decode skeleton which will be filled out by later
patches.
Signed-off-by: Alex Bennée
---
target/arm/translate-a64.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d12106695f.
This is the initial decode skeleton for the Advanced SIMD scalar
three same instruction group. The fprintf is purely to aid debugging
as the additional instructions are added. It will be removed once the
group is complete.
Signed-off-by: Alex Bennée
---
target/arm/translate-a64.c | 76 ++
Signed-off-by: Alex Bennée
---
target/arm/helper-a64.c| 17 ++
target/arm/helper-a64.h| 1 +
target/arm/translate-a64.c | 56 ++
3 files changed, 74 insertions(+)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index
A mild re-factoring of the !is_double leg to gracefully handle both
single and half-precision operations.
Signed-off-by: Alex Bennée
---
target/arm/helper-a64.c| 6 ++
target/arm/helper-a64.h| 1 +
target/arm/translate-a64.c | 19 +--
3 files changed, 20 insertions(
Half-precision helpers for float16 maths. I didn't bother hand-coding
the count leading zeros as we could always fall-back to host-utils if
we needed to.
Signed-off-by: Alex Bennée
---
fpu/softfloat-macros.h | 39 +++
fpu/softfloat.c| 21 ++
I didn't have another reference for this so I wrote it from first
principles. The roundAndPackInt16 works with the same shifted input as
roundAndPacknt32 but with different constants for invalid testing for
overflow.
Signed-off-by: Alex Bennée
---
fpu/softfloat.c | 98 +++
Again a mechanical conversion.
Signed-off-by: Alex Bennée
---
fpu/softfloat.c | 82 +
include/fpu/softfloat.h | 1 +
2 files changed, 83 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index f7473f97e3..dc7f5f6d88 100644
---
The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.
Signed-off-by: Alex Bennée
---
target/arm/helper-a64.c| 4
target/arm/helper-a64.h| 4
target/arm/translate-a64.c | 12 +++-
3 files changed, 19 inse
Signed-off-by: Alex Bennée
---
target/arm/helper-a64.c| 20
target/arm/helper-a64.h| 1 +
target/arm/translate-a64.c | 7 +++
3 files changed, 28 insertions(+)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 63b2bbd4b2..1cc2758eac 100644
--
While the group encoding declares bit 28 a zero it is set for
FCMGT (zero)
Signed-off-by: Alex Bennée
---
target/arm/translate-a64.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 11990daff4..7792cea9f5
On 10/13/2017 12:12 PM, Peter Maydell wrote:
On 13 October 2017 at 12:14, Marc-André Lureau
wrote:
Hi
On Wed, Oct 11, 2017 at 9:47 PM, Stefan Berger
wrote:
EBADMSG was only added to OpenBSD very recently. To make QEMU compilable
on older OpenBSD versions use EMSGSIZE instead when a mismatch
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20171013162438.32458-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support
(work-in-progress)
=== TEST SCRIPT BEGIN ===
#!/bin/bash
B
* Prasad Singamsetty (prasad.singamse...@oracle.com) wrote:
> Hi,
>
> I am new to the alias. I have some questions on this subject
> and seek some clarifications from the experts in the team.
> I ran into a couple of issues when I tried with large configuration
> ( >= 1TB memory, > 255 CPUs) for x
On Fri, 13 Oct 2017 18:01:44 +0100
"Dr. David Alan Gilbert" wrote:
> * Prasad Singamsetty (prasad.singamse...@oracle.com) wrote:
> > Hi,
> >
> > I am new to the alias. I have some questions on this subject
> > and seek some clarifications from the experts in the team.
> > I ran into a couple of
Public bug reported:
Today I tried to use QEMU on Windows 8.1 x64 with Intel HAX.
Command line: qemu-system-x86_64.exe -accel hax -m 8000 -hda
/opt/disk/ubuntu.img -cdrom /opt/iso/ubuntu-17.04-server-amd64.iso
Host machine has 32Gb physical memory, I got error:
HAX is working and emulator runs
On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
> Split out nbd_receive_simple_option to be reused for structured reply
s/receive/request/, but see [1]
> option.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> nbd/client.c | 64
> +++
On 10/12/2017 02:43 PM, Paolo Bonzini wrote:
>> Any particular reason to use sigsetjmp(x, 0) instead of setjmp(x)?
>> Certainly there are no signal frames that the longjmp will pass...
>
> sigsetjmp is used to _not_ save the signal mask. On OS X setjmp saves
> the signal mask by default, which is
Aligned 8-byte memory writes by a 64-bit target on a 64-bit host should
always turn into atomic 8-byte writes on the host, however if we missed
in the softmmu, and the TLB line was marked as not dirty, then we
would end up tearing the 8-byte write into two 4-byte writes in
access_with_adjusted_size
It seems that HAX not working at all:
qemu-system-x86_64.exe -accel hax -fda /opt/iso/freedos.img
(with image of boot floppy from official FreeDOS site)
Crash on loading with:
VCPU shutdown request
VCPU shutdown request
VCPU shutdown request
VCPU shutdown request
VCPU shutdown request
VCPU shutd
> From: Andrew Baumann
> Sent: Friday, 13 October 2017 11:19
>
> Aligned 8-byte memory writes by a 64-bit target on a 64-bit host should
> always turn into atomic 8-byte writes on the host, however if we missed
> in the softmmu, and the TLB line was marked as not dirty, then we
> would end up tear
On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> include/block/nbd.h | 48
> nbd/nbd-internal.h | 25 -
> nbd/client.c| 32 ---
13.10.2017 21:47, Eric Blake wrote:
On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/nbd.h | 48
nbd/nbd-internal.h | 25 -
nbd/client.c
On Wed, Oct 11, 2017 at 04:19:38PM -0400, Waiman Long wrote:
> On 10/10/2017 03:41 PM, Eduardo Habkost wrote:
> > On Tue, Oct 10, 2017 at 02:07:25PM -0400, Waiman Long wrote:
> >> On 10/10/2017 11:50 AM, Eduardo Habkost wrote:
> Yes. Another possibility is to enable it when there is >1 NUMA n
On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> include/block/nbd.h | 48
> nbd/nbd-internal.h | 25 -
> nbd/client.c| 32 ---
See https://software.intel.com/en-us/android/articles/installation-
instructions-for-intel-hardware-accelerated-execution-manager-windows:
"QEMU or Android Emulator will fail to launch if the guest RAM size
(specified with the -m option for QEMU or -memory for Android Emulator)
exceeds 4095MB."
H
On Thu, Oct 12, 2017 at 06:27:46PM +0200, Igor Mammedov wrote:
> On Thu, 5 Oct 2017 15:50:34 +0200
> Igor Mammedov wrote:
>
> Eduardo,
>
> Could you merge series via machine tree, pls?
I just queued it on machine-next. Pull request will be sent only
next week, though.
--
Eduardo
On 10/12/2017 04:53 AM, Vladimir Sementsov-Ogievskiy wrote:
> In following patch nbd_receive_reply will be used both for simple
> and structured reply header receiving.
> NBDReply is altered into union of simple reply header and structured
> reply chunk header, simple error translation moved to blo
On Thu, Oct 12, 2017 at 04:54:37PM -0700, Anatol Pomozov wrote:
> x86 is not the only architecture supported by multiboot.
> For example GRUB supports MIPS architecture as well.
>
> Signed-off-by: Anatol Pomozov
> ---
> hw/i386/multiboot.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On 10/13/17 15:21, Ard Biesheuvel wrote:
> On 13 October 2017 at 13:51, Laszlo Ersek wrote:
>> Hi Ard, Leif,
>>
>> the current physical memory map of the "virt" machine type doesn't leave
>> much room for ECAM / MMCONFIG, which limits the number of PCI Express
>> root ports and downstream ports (e
On 10/13/17 18:18, Peter Maydell wrote:
> On 13 October 2017 at 13:51, Laszlo Ersek wrote:
>> Another idea is to move *the* system DRAM base to a different guest-phys
>> address. (Likely using a different version of the "virt" machine type,
>> or even a different machine type entirely.) This would
On 10/13/2017 11:19 AM, Andrew Baumann wrote:
> Aligned 8-byte memory writes by a 64-bit target on a 64-bit host should
> always turn into atomic 8-byte writes on the host, however if we missed
> in the softmmu, and the TLB line was marked as not dirty, then we
> would end up tearing the 8-byte wri
On 10/13/2017 11:27 AM, Andrew Baumann wrote:
>> From: Andrew Baumann
>> Sent: Friday, 13 October 2017 11:19
>>
>> Aligned 8-byte memory writes by a 64-bit target on a 64-bit host should
>> always turn into atomic 8-byte writes on the host, however if we missed
>> in the softmmu, and the TLB line w
Hi Fam,
We used the same host for both src and dest for testing purposes;
ideally it should work regardless of whether src and dst are the same
host.
When we tested it, src and dest were NOT using the same vars file and
rom file; they each had their own copy.
Please, can you keep us updated when
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> linux-user/main.c | 7 +++
> 1 file changed, 7 insertions(+)
Reviewed-by: Richard Henderson
r~
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> ---
> target/arm/cpu.h | 1 +
> target/arm/cpu64.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 89d49cdcb2..3a0f27c782 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1340,6 +13
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> This allows us to explicitly pass float16 to helpers rather than
> assuming uint32_t and dealing with the result. Of course they will be
> passed in i32 sized registers by default.
>
> Signed-off-by: Alex Bennée
> ---
> include/exec/helper-head.h | 3
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> target/arm/cpu.h | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
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