"Dr. David Alan Gilbert (git)" writes:
> From: "Dr. David Alan Gilbert"
>
> opt was declared as a separate local inside the last loop,
> shadowing the local at the top of the function.
>
> Signed-off-by: Dr. David Alan Gilbert
I can take this through my tree.
On 28.09.2017 22:36, David Hildenbrand wrote:
> External interrupts are currently all handled like floating external
> interrupts, they are queued. Let's prepare for a split of floating
> and local interrupts by turning INTERRUPT_EXT into a mask.
>
> While we can have various floating external int
06.10.2017 01:12, Eric Blake wrote:
On 10/05/2017 05:36 AM, Paolo Bonzini wrote:
On 05/10/2017 12:02, Vladimir Sementsov-Ogievskiy wrote:
03.10.2017 17:06, Paolo Bonzini wrote:
On 03/10/2017 15:35, Vladimir Sementsov-Ogievskiy wrote:
In the end this probably means that you have a read_chunk_h
06.10.2017 10:09, Vladimir Sementsov-Ogievskiy wrote:
06.10.2017 01:12, Eric Blake wrote:
On 10/05/2017 05:36 AM, Paolo Bonzini wrote:
On 05/10/2017 12:02, Vladimir Sementsov-Ogievskiy wrote:
03.10.2017 17:06, Paolo Bonzini wrote:
On 03/10/2017 15:35, Vladimir Sementsov-Ogievskiy wrote:
In t
Hi Bharat,
On 06/10/2017 05:46, Bharat Bhushan wrote:
>
>
Thanks
Eric
>
> However you should be allowed to map 1 sg element of 5 pages and
> then notify the host about this event I think. Still looking at the
> code...
>
> I still can't reproduce the issue
On Thu, Oct 05, 2017 at 06:24:42PM +0200, Igor Mammedov wrote:
> consolidate 'host' core type registration by moving it from
> KVM specific code into spapr_cpu_core.c, similar like it's
> done in x86 target.
>
> Signed-off-by: Igor Mammedov
IIUC this will change behaviour slightly: with this pat
On Thu, Oct 05, 2017 at 06:24:39PM +0200, Igor Mammedov wrote:
> there is a dedicated callback CPUClass::parse_features
> which purpose is to convert -cpu features into a set of
> global properties AND deal with compat/legacy features
> that couldn't be directly translated into CPU's properties.
>
On Thu, Oct 05, 2017 at 06:24:44PM +0200, Igor Mammedov wrote:
> use generic cpu_model parsing introduced by
> (6063d4c0f vl.c: convert cpu_model to cpu type and set of global properties
> before machine_init())
>
> it allows to:
> * replace sPAPRMachineClass::tcg_default_cpu with
> Machin
On Thu, Oct 05, 2017 at 06:24:40PM +0200, Igor Mammedov wrote:
> spapr core type definition doesn't have any fields that
> require it to be defined at runtime. So replace code
> that fills in TypeInfo at runtime with static TypeInfo
> array that does the same at complie time.
>
> Signed-off-by: Ig
On Thu, Sep 28, 2017 at 06:38:55PM +0530, seeteena wrote:
>
> Thanks Thomas. Since you already put them on cc. I will wait for the
> response.
At this point, I think your patch has been lost in the noise, I'm
afraid. I suggest reposting, CCing those suggested people from the
start. I'd also sug
On Thu, Oct 05, 2017 at 06:24:43PM +0200, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> hw/ppc/spapr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index ad7afd6..0661dba 100644
> --- a/hw/p
06.10.2017 01:12, Eric Blake wrote:
On 10/05/2017 05:36 AM, Paolo Bonzini wrote:
On 05/10/2017 12:02, Vladimir Sementsov-Ogievskiy wrote:
03.10.2017 17:06, Paolo Bonzini wrote:
On 03/10/2017 15:35, Vladimir Sementsov-Ogievskiy wrote:
In the end this probably means that you have a read_chunk_h
On Thu, Oct 05, 2017 at 06:24:41PM +0200, Igor Mammedov wrote:
> replace sPAPRCPUCoreClass::cpu_class with cpu type name
> since it were needed just to get that at points it were
> accessed.
>
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> include/hw/ppc/spapr_cpu_core.h | 2 +
On Thu, 5 Oct 2017 18:25:04 +0100
Mark Cave-Ayland wrote:
> On 05/10/17 14:51, Igor Mammedov wrote:
>
> > Signed-off-by: Igor Mammedov
> > Reviewed-by: Philippe Mathieu-Daudé
> > Tested-by: Philippe Mathieu-Daudé
> > ---
> > CC: mark.cave-ayl...@ilande.co.uk
> > CC: atar4q...@gmail.com
> > --
On Thu, 5 Oct 2017 18:24:43 +0200
Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
> ---
So... this is preparatory work for the next patch because the generic cpu_model
parsing code doesn't handle aliases, is it ?
> hw/ppc/spapr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-
On Fri, 2017-10-06 at 11:40 +0530, Nikunj A Dadhania wrote:
> Cédric Le Goater writes:
>
> > Hello,
> >
> > When a CPU is stopped with the 'stop-self' RTAS call, its state
> > 'halted' is switched to 1 and, in this case, the MSR is not taken into
> > account anymore in the cpu_has_work() routine
On 10/06/2017 09:46 AM, Benjamin Herrenschmidt wrote:
> On Fri, 2017-10-06 at 11:40 +0530, Nikunj A Dadhania wrote:
>> Cédric Le Goater writes:
>>
>>> Hello,
>>>
>>> When a CPU is stopped with the 'stop-self' RTAS call, its state
>>> 'halted' is switched to 1 and, in this case, the MSR is not take
Benjamin Herrenschmidt writes:
> On Fri, 2017-10-06 at 11:40 +0530, Nikunj A Dadhania wrote:
>> Cédric Le Goater writes:
>>
>> > Hello,
>> >
>> > When a CPU is stopped with the 'stop-self' RTAS call, its state
>> > 'halted' is switched to 1 and, in this case, the MSR is not taken into
>> > acc
On Thu, 5 Oct 2017 14:09:06 -0300
Eduardo Habkost wrote:
> On Thu, Oct 05, 2017 at 11:04:27AM +0200, Igor Mammedov wrote:
> > On Wed, 4 Oct 2017 14:39:20 -0700
> > Alistair Francis wrote:
> >
> > > On Wed, Oct 4, 2017 at 9:34 AM, Eduardo Habkost
> > > wrote:
> > > > On Wed, Oct 04, 2017 a
On Fri, 6 Oct 2017 14:02:56 +1100
David Gibson wrote:
> On Thu, Oct 05, 2017 at 06:24:31PM +0200, Igor Mammedov wrote:
> > Signed-off-by: Igor Mammedov
>
> Acked-by: David Gibson
>
> Do you want me to queue the ppc patches here, or do you already have a
> plan for that?
Id didn't want to di
* Markus Armbruster (arm...@redhat.com) wrote:
> Jan Dakinevich writes:
>
> > On 10/03/2017 05:02 PM, Eric Blake wrote:
> >> On 10/03/2017 07:47 AM, Jan Dakinevich wrote:
> >>> The command is intended for gathering virtio information such as status,
> >>> feature bits, negotiation status. It is c
On Thu, 5 Oct 2017 21:05:37 +0200
Greg Kurz wrote:
> On Thu, 5 Oct 2017 18:24:39 +0200
> Igor Mammedov wrote:
>
> > there is a dedicated callback CPUClass::parse_features
> > which purpose is to convert -cpu features into a set of
> > global properties AND deal with compat/legacy features
> >
On Fri Oct 06, 2017 at 09:24:20AM +0200, Auger Eric wrote:
> Hi Bharat,
>
> On 06/10/2017 05:46, Bharat Bhushan wrote:
> >
> >
> Thanks
>
> Eric
> >
> > However you should be allowed to map 1 sg element of 5 pages and
> > then notify the host about this event I think.
On Thu, Oct 05, 2017 at 06:24:48PM +0200, Igor Mammedov wrote:
> pnv core type definition doesn't have any fields that
> require it to be defined at runtime. So replace code
> that fills in TypeInfo at runtime with static TypeInfo
> array that does the same at complie time.
>
> Signed-off-by: Igor
On Thu, Oct 05, 2017 at 06:24:50PM +0200, Igor Mammedov wrote:
> Use a new DEFINE_TYPES() helper to simplify type registration
>
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> hw/ppc/pnv.c | 92
> ++--
> 1 file changed, 3
On Thu, Oct 05, 2017 at 06:24:47PM +0200, Igor Mammedov wrote:
> deduce cpu type directly from core type instead of
> maintaining type mapping in PnvCoreClass::cpu_oc and doing
> extra cpu_model parsing in pnv_core_class_init()
>
> Signed-off-by: Igor Mammedov
> ---
> include/hw/ppc/pnv_core.h |
On Thu, Oct 05, 2017 at 04:24:58PM -0300, Daniel Henrique Barboza wrote:
> In cases where a device is hotplugged and hot-unplugged shortly after,
> there is a chance of QEMU breaking with the following message:
>
> hw/ppc/spapr_drc.c:417:spapr_drc_detach: assertion failed: (drc->dev)
> Aborted
>
On Thu, Oct 05, 2017 at 06:24:45PM +0200, Igor Mammedov wrote:
> use common cpu_model prasing in vl.c and set default cpu_model
> using generic MachineClass::default_cpu_type.
>
> Beside of switching to generic infrastructure it solves several
> issues.
>
> * ppc_cpu_class_by_name() is used to d
On Thu, Oct 05, 2017 at 06:24:46PM +0200, Igor Mammedov wrote:
> typically for cpus/core type names following convention is used
>
>new_type_prefix-superclass_typename
>
> make PNV core/chip to follow common convention.
>
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> inc
On Thu, Oct 05, 2017 at 06:24:49PM +0200, Igor Mammedov wrote:
> deduce core type directly from chip type instead of
> maintaining type mapping in PnvChipClass::cpu_model.
>
> Signed-off-by: Igor Mammedov
> ---
> include/hw/ppc/pnv.h | 1 -
> include/hw/ppc/pnv_core.h | 1 -
> hw/ppc/pnv.
On Fri, 6 Oct 2017 14:54:47 +1100
David Gibson wrote:
> On Thu, Oct 05, 2017 at 06:24:39PM +0200, Igor Mammedov wrote:
> > there is a dedicated callback CPUClass::parse_features
> > which purpose is to convert -cpu features into a set of
> > global properties AND deal with compat/legacy features
Am 06.10.2017 um 05:56 hat John Snow geschrieben:
> On 10/05/2017 07:38 AM, Kevin Wolf wrote:
> > Let me try to just consolidate all of the above into a single state
> > machine:
> >
> > 1. CREATED --> RUNNING
> > driver callback: .start
> > 2a. RUNNING --> READY | CANCELLED
> > v
On Fri, 6 Oct 2017 15:41:04 +1100
David Gibson wrote:
> On Thu, Oct 05, 2017 at 06:24:42PM +0200, Igor Mammedov wrote:
> > consolidate 'host' core type registration by moving it from
> > KVM specific code into spapr_cpu_core.c, similar like it's
> > done in x86 target.
> >
> > Signed-off-by: Igo
On Thu, Oct 05, 2017 at 06:49:58PM +0200, Cédric Le Goater wrote:
> When a CPU is stopped with the 'stop-self' RTAS call, its state
> 'halted' is switched to 1 and, in this case, the MSR is not taken into
> account anymore in the cpu_has_work() routine. Only the pending
> hardware interrupts are ch
On Fri, Oct 06, 2017 at 11:40:02AM +0530, Nikunj A Dadhania wrote:
> Cédric Le Goater writes:
>
> > Hello,
> >
> > When a CPU is stopped with the 'stop-self' RTAS call, its state
> > 'halted' is switched to 1 and, in this case, the MSR is not taken into
> > account anymore in the cpu_has_work() r
On Thu, Oct 05, 2017 at 06:49:59PM +0200, Cédric Le Goater wrote:
> When a CPU is stopped with the 'stop-self' RTAS call, its state
> 'halted' is switched to 1 and, in this case, the MSR is not taken into
> account anymore in the cpu_has_work() routine. Only the pending
> hardware interrupts are ch
On Fri, Oct 06, 2017 at 11:07:14AM +0200, Igor Mammedov wrote:
> On Fri, 6 Oct 2017 15:41:04 +1100
> David Gibson wrote:
>
> > On Thu, Oct 05, 2017 at 06:24:42PM +0200, Igor Mammedov wrote:
> > > consolidate 'host' core type registration by moving it from
> > > KVM specific code into spapr_cpu_co
On Fri, Oct 06, 2017 at 10:27:38AM +0200, Igor Mammedov wrote:
> On Fri, 6 Oct 2017 14:02:56 +1100
> David Gibson wrote:
>
> > On Thu, Oct 05, 2017 at 06:24:31PM +0200, Igor Mammedov wrote:
> > > Signed-off-by: Igor Mammedov
> >
> > Acked-by: David Gibson
> >
> > Do you want me to queue the
On Fri, Oct 06, 2017 at 11:03:52AM +0200, Igor Mammedov wrote:
> On Fri, 6 Oct 2017 14:54:47 +1100
> David Gibson wrote:
>
> > On Thu, Oct 05, 2017 at 06:24:39PM +0200, Igor Mammedov wrote:
> > > there is a dedicated callback CPUClass::parse_features
> > > which purpose is to convert -cpu feature
On Fri, 6 Oct 2017 16:04:39 +1100
David Gibson wrote:
> On Thu, Oct 05, 2017 at 06:24:44PM +0200, Igor Mammedov wrote:
> > use generic cpu_model parsing introduced by
> > (6063d4c0f vl.c: convert cpu_model to cpu type and set of global
> > properties before machine_init())
> >
> > it allows to
On Fri, 6 Oct 2017 09:39:25 +0200
Greg Kurz wrote:
> On Thu, 5 Oct 2017 18:24:43 +0200
> Igor Mammedov wrote:
>
> > Signed-off-by: Igor Mammedov
> > ---
>
> So... this is preparatory work for the next patch because the generic
> cpu_model
> parsing code doesn't handle aliases, is it ?
gen
On Fri, 6 Oct 2017 19:34:19 +1100
David Gibson wrote:
> On Thu, Oct 05, 2017 at 06:24:45PM +0200, Igor Mammedov wrote:
> > use common cpu_model prasing in vl.c and set default cpu_model
> > using generic MachineClass::default_cpu_type.
> >
> > Beside of switching to generic infrastructure it sol
On Fri, 6 Oct 2017 19:41:12 +1100
David Gibson wrote:
> On Thu, Oct 05, 2017 at 06:24:47PM +0200, Igor Mammedov wrote:
> > deduce cpu type directly from core type instead of
> > maintaining type mapping in PnvCoreClass::cpu_oc and doing
> > extra cpu_model parsing in pnv_core_class_init()
> >
>
On Fri, 6 Oct 2017 19:46:34 +1100
David Gibson wrote:
> On Thu, Oct 05, 2017 at 06:24:49PM +0200, Igor Mammedov wrote:
> > deduce core type directly from chip type instead of
> > maintaining type mapping in PnvChipClass::cpu_model.
> >
> > Signed-off-by: Igor Mammedov
> > ---
> > include/hw/pp
On Fri, Oct 06, 2017 at 11:20:05AM +0200, Igor Mammedov wrote:
> On Fri, 6 Oct 2017 16:04:39 +1100
> David Gibson wrote:
>
> > On Thu, Oct 05, 2017 at 06:24:44PM +0200, Igor Mammedov wrote:
> > > use generic cpu_model parsing introduced by
> > > (6063d4c0f vl.c: convert cpu_model to cpu type and
On Fri, 6 Oct 2017 20:12:02 +1100
David Gibson wrote:
> On Fri, Oct 06, 2017 at 10:27:38AM +0200, Igor Mammedov wrote:
> > On Fri, 6 Oct 2017 14:02:56 +1100
> > David Gibson wrote:
> >
> > > On Thu, Oct 05, 2017 at 06:24:31PM +0200, Igor Mammedov wrote:
> > > > Signed-off-by: Igor Mammedov
Am 06.10.2017 um 01:18 hat Doug Gale geschrieben:
> I added the tracing output in this patch to assist me in implementing
> an NVMe driver. It helped tremendously.
>
> From 1d19086cdef8d492929852d582cb41dcc5026f71 Mon Sep 17 00:00:00 2001
> From: Doug Gale
> Date: Thu, 5 Oct 2017 19:02:03 -0400
>
On Fri, 6 Oct 2017 20:17:41 +1100
David Gibson wrote:
> On Fri, Oct 06, 2017 at 11:03:52AM +0200, Igor Mammedov wrote:
> > On Fri, 6 Oct 2017 14:54:47 +1100
> > David Gibson wrote:
> >
> > > On Thu, Oct 05, 2017 at 06:24:39PM +0200, Igor Mammedov wrote:
> > > > there is a dedicated callback
On Fri, 2017-10-06 at 20:07 +1100, David Gibson wrote:
> Hm. Checking mmu_model doesn't seem right to me. I mean, it'll get
> the right answer in practice, but the LPCR programming has nothing
> whatsoever to do with the MMU.
>
> I think explicitly checking if cpu_ is a POWER9 instance with
> ob
On Fri, 6 Oct 2017 20:35:41 +1100
David Gibson wrote:
> On Fri, Oct 06, 2017 at 11:20:05AM +0200, Igor Mammedov wrote:
> > On Fri, 6 Oct 2017 16:04:39 +1100
> > David Gibson wrote:
> >
> > > On Thu, Oct 05, 2017 at 06:24:44PM +0200, Igor Mammedov wrote:
> > > > use generic cpu_model parsing
From: David Hildenbrand
We want to use it in another file.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
Message-Id: <20170920153016.3858-3-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
target/s390x/internal.h | 14 ++
The following changes since commit d8f932cc696250cb740240d668b39df5fbb2d5a0:
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
into staging (2017-10-05 16:54:29 +0100)
are available in the git repository at:
git://github.com/cohuck/qemu tags/s390x-2017100
From: David Hildenbrand
Missing and is used inside Linux in the context of CPACF.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
Message-Id: <20170920153016.3858-2-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
target/s390x/cpu.h | 2 ++
target/s390x/insn-data.d
From: Igor Mammedov
Define default CPU type in generic way in machine class_init
and let common machine code handle cpu_model parsing.
Signed-off-by: Igor Mammedov
Reviewed-by: David Hildenbrand
Message-Id: <1505998749-269631-1-git-send-email-imamm...@redhat.com>
Signed-off-by: Cornelia Huck
From: Halil Pasic
Replace direct access which implicitly assumes no IDA
or MIDA with the new ccw data stream interface which should
cope with these transparently in the future.
Note that checking the return code for ccw_dstream_* will be
done in a follow-on patch.
Signed-off-by: Halil Pasic
Re
From: Halil Pasic
This is a preparation for introducing handling for indirect data
addressing and modified indirect data addressing (CCW). Here we introduce
an interface which should make the addressing scheme transparent for the
client code. Here we implement only the basic scheme (no IDA or MID
From: David Hildenbrand
The STFLE bits for the MSA (extension) facilities simply indicate that
the respective instructions can be executed. The QUERY subfunction can then
be used to identify which features exactly are available.
Availability of subfunctions can also vary on real hardware. For no
From: David Hildenbrand
env->psa is a 64bit value, while we copy 4 bytes into the save area,
resulting always in 0 getting stored.
Let's try to reduce such errors by using a proper structure. While at
it, use correct cpu->be conversion (and get_psw_mask()), as we will be
reusing this code for TC
From: Halil Pasic
The architecture mandates the addresses to be accessed on the first
indirection level (that is, the data addresses without IDA, and the
(M)IDAW addresses with (M)IDA) to be checked against an CCW format
dependent limit maximum address. If a violation is detected, the storage
ac
From: David Hildenbrand
Let's move it into the machine, so we trigger the IRQ after setting
ms->possible_cpus (which SCLP uses to construct the list of
online CPUs).
This also fixes a problem reported by Thomas Huth, whereby qemu can be
crashed using the none machine
qemu-s390x-softmmu -M none
From: Halil Pasic
Replace direct access which implicitly assumes no IDA
or MIDA with the new ccw data stream interface which should
cope with these transparently in the future.
Note that checking the return code for ccw_dstream_* will be
done in a follow-on patch.
Signed-off-by: Halil Pasic
Re
From: David Hildenbrand
Looks like, lurag was not loading 64bit but only 32bit.
As we properly handle the return address now, we can drop
potential_page_fault().
Signed-off-by: David Hildenbrand
Message-Id: <20170926183318.12995-4-da...@redhat.com>
Reviewed-by: Richard Henderson
Reviewed-by:
From: David Hildenbrand
This makes it easy to access real addresses (prefix) and in addition
checks for valid memory addresses, which is missing when using e.g.
stl_phys().
We can later reuse it to implement low address protection checks (then
we might even decide to introduce yet another MMU fo
From: David Hildenbrand
core_id is not needed by linux-user, as the core_id a.k.a. CPU address
is only accessible from kernel space.
Therefore, drop next_core_id and make cpu_index get autoassigned again
for linux-user.
While at it, shield core_id and cpuid completely from linux-user. cpuid
can
From: David Hildenbrand
It should have been a >=, but let's directly perform a proper access
check to also be able to deal with hotplugged memory later.
Signed-off-by: David Hildenbrand
Message-Id: <20170926183318.12995-2-da...@redhat.com>
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Hut
From: David Hildenbrand
Low address protection checks will be moved into the mmu later.
Signed-off-by: David Hildenbrand
Message-Id: <20170926183318.12995-6-da...@redhat.com>
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Signed-off-by: Cornelia Huck
---
target/s390x/mem_helper.c |
From: David Hildenbrand
We don't wrap addresses in the mmu for the _real case, therefore the
behavior should be unchanged.
Signed-off-by: David Hildenbrand
Message-Id: <20170926183318.12995-7-da...@redhat.com>
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Signed-off-by: Cornelia Huc
From: David Hildenbrand
Will be handy in the future.
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
Message-Id: <20170928134609.16985-6-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
hw/s390x/s390-virtio-ccw.c | 2 +-
target/s390x/cpu.h
From: Halil Pasic
Let's add indirect data addressing support for our virtual channel
subsystem. This implementation does not bother with any kind of
prefetching. We simply step through the IDAL on demand.
Signed-off-by: Halil Pasic
Message-Id: <20170921180841.24490-6-pa...@linux.vnet.ibm.com>
R
From: David Hildenbrand
Forgot it when factoring code out into these files. This is 100% s390x
KVM material.
Signed-off-by: David Hildenbrand
Message-Id: <20170928134609.16985-2-da...@redhat.com>
Acked-by: Christian Borntraeger
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 2 ++
1 file chan
From: Christian Borntraeger
This reverts commit d32bd032d8fde41281aae34c16a4aa97e9acfeac.
Turns out that old QEMUs always created a pci host bridge
and for many CPU models the migration from old QEMUs to new
QEMUs will fail with
qemu-system-s390x: Unknown savevm section or instance 'PCIBUS' 0
qe
From: Halil Pasic
Commit e996583eb3 ("s390x/css: activate ChannelSubSys migration",
2017-07-11) was supposed to enable css migration for virtio-ccw
machines starting 2.10, but it ended up effectively enabling it
only for 2.10 as the registration of the appropriate VMStateDescription
happens in cc
From: David Hildenbrand
As we properly handle the return address now, we can drop
potential_page_fault().
Signed-off-by: David Hildenbrand
Message-Id: <20170926183318.12995-5-da...@redhat.com>
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Signed-off-by: Cornelia Huck
---
target/s3
From: Halil Pasic
The problem is, that the current implementation places unrealistic and
arbitrary constraints on the length of writes to the device (that is the
outbound requests), by asserting ccw.count being such that that even the
worst case escaped payload will fit an more or less arbitrary
From: David Hildenbrand
Using virtual memory access is wrong and will soon include low-address
protection checks, which is to be bypassed for STFL.
STFL is a privileged instruction and using LowCore requires
!CONFIG_USER_ONLY, so add the ifdef and move the declaration to the
right place.
This w
A TYPE_SCLP_CPU_HOTPLUG device for handling cpu hotplug events
is already created by the sclp event facility. Adding a second
TYPE_SCLP_CPU_HOTPLUG device via -device sclp-cpu-hotplug creates
an ambiguity in raise_irq_cpu_hotplug(), leading to a crash once
a cpu is hotplugged.
To fix this, disallo
From: Halil Pasic
Let us convert the 3270 code so it uses the recently introduced
CcwDataStream abstraction instead of blindly assuming direct data access.
This patch does not change behavior beyond introducing IDA support: for
direct data access CCWs everything stays as-is. (If there are bugs,
From: David Hildenbrand
Not that it would matter in the near future, but it is actually 2048
bytes, therefore 16384 possible bits.
Reviewed-by: Christian Borntraeger
Reviewed-by: Thomas Huth
Signed-off-by: David Hildenbrand
Message-Id: <20170928134609.16985-4-da...@redhat.com>
Signed-off-by:
From: "Collin L. Walling"
Provides an interface for getting and setting the guest's extended
TOD-Clock via a single ioctl to kvm. If the ioctl fails because it
is not support by kvm, then we fall back to the old style of
retrieving the clock via two ioctls.
Signed-off-by: Collin L. Walling
Revi
From: "Collin L. Walling"
If we fail to set a proper TOD clock on the target system, this can
already result in some problematic cases. We print several warn messages
on source and target in that case.
If kvm fails to set a nonzero epoch index, then we must ultimately fail
the migration as this
Add missing categorizations for some s390x devices:
- zpci device -> misc
- 3270 -> display
- vfio-ccw -> misc
Acked-by: Christian Borntraeger
Reviewed-by: Thomas Huth
Signed-off-by: Cornelia Huck
---
hw/s390x/3270-ccw.c | 1 +
hw/s390x/s390-pci-bus.c | 1 +
hw/vfio/ccw.c | 1 +
Just as for external interrupts and I/O interrupts, we need to
initialize mchk_index during cpu reset.
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Signed-off-by: Cornelia Huck
---
target/s390x/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/cpu.c b/target/s
From: Thomas Huth
The "sclp" device is just an internal device that can not be instantiated
by the users. If they try to use it, they only get a simple error message:
$ qemu-system-s390x -nographic -device sclp
qemu-system-s390x: Option '-device s390-sclp-event-facility' cannot be
handled by thi
From: Thomas Huth
The "sclpquiesce" device is just an internal device that should not be
created by the user directly. Though it currently does not seem to cause
any obvious trouble when the user instantiates an additional device, let's
better mark it with user_creatable = false to avoid unexpect
On Fri, Oct 06, 2017 at 11:52:44AM +0200, Igor Mammedov wrote:
> On Fri, 6 Oct 2017 20:17:41 +1100
> David Gibson wrote:
>
> > On Fri, Oct 06, 2017 at 11:03:52AM +0200, Igor Mammedov wrote:
> > > On Fri, 6 Oct 2017 14:54:47 +1100
> > > David Gibson wrote:
> > >
> > > > On Thu, Oct 05, 2017 at
On Fri, 6 Oct 2017 11:27:10 +0200
Igor Mammedov wrote:
> On Fri, 6 Oct 2017 09:39:25 +0200
> Greg Kurz wrote:
>
> > On Thu, 5 Oct 2017 18:24:43 +0200
> > Igor Mammedov wrote:
> >
> > > Signed-off-by: Igor Mammedov
> > > ---
> >
> > So... this is preparatory work for the next patch be
On Fri, Oct 06, 2017 at 11:53:30AM +0200, Benjamin Herrenschmidt wrote:
> On Fri, 2017-10-06 at 20:07 +1100, David Gibson wrote:
> > Hm. Checking mmu_model doesn't seem right to me. I mean, it'll get
> > the right answer in practice, but the LPCR programming has nothing
> > whatsoever to do with
On 10/05/2017 07:13 PM, Maxime Coquelin wrote:
static MemoryRegionSection flatview_do_translate(FlatView *fv,
hwaddr addr,
hwaddr *xlat,
- hwad
On Tue, Oct 03, 2017 at 05:21:57PM -0500, Michael Roth wrote:
> Quoting Michael Roth (2017-07-26 20:30:52)
> > This series was motivated by the discussion in this thread:
> >
> > https://www.redhat.com/archives/libvir-list/2017-June/msg01370.html
> >
> > The issue this series addresses is that
Emilio G. Cota writes:
> On Mon, Aug 07, 2017 at 19:52:16 -0400, Emilio G. Cota wrote:
>> This series applies on top of the "multiple TCG contexts" series, v4:
>> https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg06769.html
> (snip)
>> Please review!
>
> Turns out this patchset breaks i
(1) make .git-submodule-status depend on config-host.mak,
for GIT_SUBMODULES changes.
(2) make $(KEYCODEMAP_{GEN,CSV}) depend on .git-submodule-status
so make knows what to do if they are not there.
I still get errors because make tries to generate the files before they are
checked out,
On 06/10/17 08:37, Igor Mammedov wrote:
>> No objections to this patch but just to confirm from the previous
>> discussion that the cpu type gets parsed in a way such that an existing
>> -cpu "TI SuperSparc II" option gets mapped to the correct
>> "TI-SuperSparc-II" type? Presumably this is now ha
Status changed to 'Confirmed' because the bug affects multiple users.
** Changed in: qemu (Ubuntu)
Status: New => Confirmed
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1718719
Title:
qemu
Hmm... -h is common to all targets, ie, you should only find properties
that can be passed to -machine for all qemu-system-* binaries (I don't
know how s390-squash-mcss landed there but it looks wrong).
The right way to query properties supported by a pseries machine type
is:
$ ./ppc64-softmmu/qe
This series is a rebase of the first two patches of Peter's series
improving address_space_get_iotlb_entry():
Message-Id: <1496404254-17429-1-git-send-email-pet...@redhat.com>
This second revision of the rebase fixes the page_mask initial value,
that was mistakenly set to its complement. This bug
On Fri, Oct 06, 2017 at 10:23:12AM +0200, Igor Mammedov wrote:
> On Thu, 5 Oct 2017 14:09:06 -0300
> Eduardo Habkost wrote:
>
> > On Thu, Oct 05, 2017 at 11:04:27AM +0200, Igor Mammedov wrote:
> > > On Wed, 4 Oct 2017 14:39:20 -0700
> > > Alistair Francis wrote:
> > >
> > > > On Wed, Oct 4, 2
From: Peter Xu
This patch let address_space_get_iotlb_entry() to use the newly
introduced page_mask parameter in flatview_do_translate(). Then we
will be sure the IOTLB can be aligned to page mask, also we should
nicely support huge pages now when introducing a764040.
Fixes: a764040 ("exec: abst
On Fri, 06 Oct 2017 11:21:08 -
Greg Kurz wrote:
> Hmm... -h is common to all targets, ie, you should only find properties
> that can be passed to -machine for all qemu-system-* binaries (I don't
> know how s390-squash-mcss landed there but it looks wrong).
That output comes from qemu-options
From: Peter Xu
The function is originally used for flatview_space_translate() and what
we care about most is (xlat, plen) range. However for iotlb requests, we
don't really care about "plen", but the size of the page that "xlat" is
located on. While, plen cannot really contain this information.
On Fri, Oct 06, 2017 at 03:15:44PM +1100, David Gibson wrote:
> On Thu, Sep 28, 2017 at 06:38:55PM +0530, seeteena wrote:
> >
> > Thanks Thomas. Since you already put them on cc. I will wait for the
> > response.
>
> At this point, I think your patch has been lost in the noise, I'm
> afraid. I s
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