Hi,
This series failed build test on s390x host. Please find the details below.
Message-id: 20170817125904.7421-1-pbutsy...@virtuozzo.com
Type: series
Subject: [Qemu-devel] [PATCH] follow-up path - " qcow2: add shrink image
support"
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be
On 17.08.2017 14:55, David Hildenbrand wrote:
> On 17.08.2017 14:35, Thomas Huth wrote:
>> On 17.08.2017 13:40, Philippe Mathieu-Daudé wrote:
>>> On 08/17/2017 06:22 AM, David Hildenbrand wrote:
[...]
feat-src = $(SRC_PATH)/target/$(TARGET_BASE_ARCH)/
diff --git a/target/s390x/cpu.h b/t
On Thu, 17 Aug 2017 15:06:10 +0200
Thomas Huth wrote:
> On 17.08.2017 14:55, David Hildenbrand wrote:
> > On 17.08.2017 14:35, Thomas Huth wrote:
> >> On 17.08.2017 13:40, Philippe Mathieu-Daudé wrote:
> >>> On 08/17/2017 06:22 AM, David Hildenbrand wrote:
> [...]
> feat-src = $(SRC_
On Thu, 17 Aug 2017 14:41:34 +0200
Thomas Huth wrote:
> On 17.08.2017 11:22, David Hildenbrand wrote:
> > Let's reshuffle the function prototypes so we get a cleaner outline
> > of the files.
> >
> > Reviewed-by: Richard Henderson
> > Signed-off-by: David Hildenbrand
> > ---
> > target/s390x/
On 17.08.2017 15:07, Cornelia Huck wrote:
> On Thu, 17 Aug 2017 15:06:10 +0200
> Thomas Huth wrote:
>
>> On 17.08.2017 14:55, David Hildenbrand wrote:
>>> On 17.08.2017 14:35, Thomas Huth wrote:
On 17.08.2017 13:40, Philippe Mathieu-Daudé wrote:
> On 08/17/2017 06:22 AM, David Hilden
On Thu, 17 Aug 2017 11:22:15 +0200
David Hildenbrand wrote:
> cpu.h is accessed outside of target/s390x. It should only contain
> what is expected to be accessed outside of this folder. Therefore, create
> internal.h and move a lot to that file. In addition, introduce
> kvm-stub.c and kvm_390x.h
On 17.08.2017 15:11, Cornelia Huck wrote:
> On Thu, 17 Aug 2017 11:22:15 +0200
> David Hildenbrand wrote:
>
>> cpu.h is accessed outside of target/s390x. It should only contain
>> what is expected to be accessed outside of this folder. Therefore, create
>> internal.h and move a lot to that file.
On 17.08.2017 15:10, David Hildenbrand wrote:
> On 17.08.2017 15:07, Cornelia Huck wrote:
>> On Thu, 17 Aug 2017 15:06:10 +0200
>> Thomas Huth wrote:
>>
>>> On 17.08.2017 14:55, David Hildenbrand wrote:
On 17.08.2017 14:35, Thomas Huth wrote:
> On 17.08.2017 13:40, Philippe Mathieu-Daud
On 08/17/2017 10:06 AM, Thomas Huth wrote:
On 17.08.2017 14:55, David Hildenbrand wrote:
On 17.08.2017 14:35, Thomas Huth wrote:
On 17.08.2017 13:40, Philippe Mathieu-Daudé wrote:
On 08/17/2017 06:22 AM, David Hildenbrand wrote:
[...]
feat-src = $(SRC_PATH)/target/$(TARGET_BASE_ARCH)/
dif
On 08/02/2017 06:24 PM, Cleber Rosa wrote:
>
>
> On 08/02/2017 05:36 PM, Philippe Mathieu-Daudé wrote:
>> Hi Cleber,
>>
>> On 08/02/2017 05:15 PM, Cleber Rosa wrote:
>>> Which contains one specific function used by iov.c.
>>>
>>> Without this, "make -C tests/tcg test_path" (and consequently
>>>
Hi Linu,
On 17/08/17 12:26, Linu Cherian wrote:
> Hi Eric,
>
> On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote:
>> This series implements the virtio-iommu device.
>>
>> This v3 mostly is a rebase on top of v2.10-rc0 that uses
>> IOMMUMmeoryRegion plus some small fixes.
>>
>> This is a p
Hi Eric,
On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote:
> This series implements the virtio-iommu device.
>
> This v3 mostly is a rebase on top of v2.10-rc0 that uses
> IOMMUMmeoryRegion plus some small fixes.
>
> This is a proof of concept based on the virtio-iommu specification
> w
On 17.08.2017 11:46, David Hildenbrand wrote:
> On 17.08.2017 10:53, Cornelia Huck wrote:
>> On Thu, 17 Aug 2017 08:25:10 +0200
>> Thomas Huth wrote:
>>
>>> By using the "virtio-xxx" device name aliases instead of the
>>> "virtio-xxx-pci" names, we can use this test on s390x, too,
>>> to check tha
Marc-André Lureau writes:
> Hi,
>
> In order to clean-up some hacks in qapi (having to unregister commands
> at runtime), I proposed a "[PATCH v5 02/20] qapi.py: add a simple #ifdef
> condition"
>
> (see http://lists.gnu.org/archive/html/qemu-devel/2016-08/msg03106.html).
>
> However, we decided
On Thu, 17 Aug 2017 15:54:38 +0200
Thomas Huth wrote:
> On 17.08.2017 11:46, David Hildenbrand wrote:
> > On 17.08.2017 10:53, Cornelia Huck wrote:
> >> On Thu, 17 Aug 2017 08:25:10 +0200
> >> Thomas Huth wrote:
> >>
> >>> By using the "virtio-xxx" device name aliases instead of the
> >>> "v
On 17.08.2017 10:41, Cornelia Huck wrote:
> On Thu, 17 Aug 2017 08:25:09 +0200
> Thomas Huth wrote:
>
>> With some small modifications, we can also use the the netfilter,
>> the fiter-mirror and the filter-redirector tests on s390x.
>
> s/fiter/filter/
OK ... could you please fix that when pick
On Wed, Aug 16, 2017 at 11:11:44PM +0300, Manos Pitsidianakis wrote:
> On Wed, Aug 16, 2017 at 02:25:44PM +0100, Stefan Hajnoczi wrote:
> > On Tue, Aug 15, 2017 at 11:18:53AM +0300, Manos Pitsidianakis wrote:
> > > @@ -3142,7 +3174,7 @@ static bool should_update_child(BdrvChild *c,
> > > BlockDriv
Since
(commit d4a606b3 i386: Don't override -cpu options on -cpu host/max)
it became possible to delete hack where it was necessary to
postpone applying plus/minus features to realize time
after max_features were applied to keep legacy +-feat
override semantics.
With above commit it's possible to
Move cpu_model +-feat parsing into a separate file so that it
could be reused later for parsing similar format of sparc target
Signed-off-by: Igor Mammedov
---
CC: Riku Voipio
CC: Laurent Vivier
CC: Paolo Bonzini
CC: Richard Henderson
CC: Eduardo Habkost
---
include/qom/cpu.h
This makes the werror/rerror options available on the scsi-block device,
to allow user specify error handling policy in the same way as scsi-hd
etc.
Signed-off-by: Fam Zheng
---
Take care of status, error, sense and QMP as well. [Paolo]
---
hw/scsi/scsi-disk.c | 81
QEMU currently aborts unexpectedly when the user tries to add and
remove a "spapr-tce-table" device:
$ qemu-system-ppc64 -nographic -S -nodefaults -monitor stdio
QEMU 2.9.92 monitor - type 'help' for more information
(qemu) device_add spapr-tce-table,id=x
(qemu) device_del x
**
ERROR:qemu/qdev-mon
On Thu, 17 Aug 2017 00:50:50 -0300
Philippe Mathieu-Daudé wrote:
> On 07/14/2017 10:51 AM, Igor Mammedov wrote:
> > QOMfy cpu models handling introducing propper cpu types
> > for each cpu model.
> >
> > Signed-off-by: Igor Mammedov
> > ---
> > with this and conversion of features to properties
On Wed, Aug 16, 2017 at 11:10:46AM +0200, Igor Mammedov wrote:
> On Tue, 15 Aug 2017 22:24:08 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Tue, Aug 15, 2017 at 02:07:51PM +0200, Igor Mammedov wrote:
> > > On Tue, 15 Aug 2017 12:15:48 +0100
> > > Anthony PERARD wrote:
> > >
> > > > To do PCI p
On 17/08/2017 16:11, Fam Zheng wrote:
> This makes the werror/rerror options available on the scsi-block device,
> to allow user specify error handling policy in the same way as scsi-hd
> etc.
>
> Signed-off-by: Fam Zheng
>
> ---
>
> Take care of status, error, sense and QMP as well. [Paolo]
>
The throttling code can change internally the value of bkt->max if it
hasn't been set by the user. The problem with this is that if we want
to retrieve the original value we have to undo this change first. This
is ugly and unnecessary: this patch removes the throttle_fix_bucket()
and throttle_unfix
Hi all,
this series contains a few small changes to the throttling code and
its documentation.
Stefan, once this is reviewed, can you please remove the "Make
LeakyBucket.avg and LeakyBucket.max integer types" commit (id
1744e9a12cbcebff2e) from your block-next branch? This series contains
a new v
The level of the burst bucket is stored in bkt.burst_level, not
bkt.burst_lenght.
Signed-off-by: Alberto Garcia
---
include/qemu/throttle.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/qemu/throttle.h b/include/qemu/throttle.h
index d056008c18..66a8ac10a4 100644
--
Both the throttling limits set with the throttling.iops-* and
throttling.bps-* options and their QMP equivalents defined in the
BlockIOThrottle struct are integer values.
Those limits are also reported in the BlockDeviceInfo struct and they
are integers there as well.
Therefore there's no reason
The way the throttling algorithm works is that requests start being
throttled once the bucket level exceeds the burst limit. When we get
there the bucket leaks at the level set by the user (bkt->avg), and
that leak rate is what prevents guest I/O from exceeding the desired
limit.
If we don't allow
On Wed, 16 Aug 2017 16:56:40 -0300
Eduardo Habkost wrote:
> On Fri, Jul 14, 2017 at 03:52:09PM +0200, Igor Mammedov wrote:
> > call xtensa_irq_init() at realize time which makes
> > cpu_xtensa_init() like generic cpu creation function.
> > As result we can replace it with cpu_generic_init()
> > w
On 15/08/2017 09:30, Markus Armbruster wrote:
> The stupid fix is to repeat libraries until the link succeeds:
>
> test-util-obj-y = libqemuutil.a libqemustub.a libqemuutil.a
>
> You may have seen this with -lX11 if you're old enough.
>
> ld(1) suggests the linker can do it for us:
>
>
On Thu, 17 Aug 2017 01:30:56 -0300
Philippe Mathieu-Daudé wrote:
> no logical change, only code movement (and fix a comment typo).
while at that fix checkpatch errors or
first fix checkpatch noted issues in cpu.h and then move it in next patch to
internal.h
>
> Signed-off-by: Philippe Mathieu
no logical change, only code movement (and fix a comment typo).
while at that fix checkpatch errors or
first fix checkpatch noted issues in cpu.h and then move it in next patch to
internal.h
ok will do!
On Thu, 17 Aug 2017 15:23:27 +0100
Anthony PERARD wrote:
> On Wed, Aug 16, 2017 at 11:10:46AM +0200, Igor Mammedov wrote:
> > On Tue, 15 Aug 2017 22:24:08 +0300
> > "Michael S. Tsirkin" wrote:
> >
> > > On Tue, Aug 15, 2017 at 02:07:51PM +0200, Igor Mammedov wrote:
> > > > On Tue, 15 Aug 20
On Thu, 17 Aug 2017 01:31:00 -0300
Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
looks good, just squash it into previous patch
>
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> i
On Thu, 17 Aug 2017 01:30:54 -0300
Philippe Mathieu-Daudé wrote:
> Hi,
>
> While working with the mips codebase I had to QOMify it.
>
> I then read Igor's series "complete cpu QOMification" [1] and after some IRC
> chat I suggested Igor to rebase his series on mine to avoid code moving
> forwar
Hi Bharat,
On 14/07/2017 09:25, Bharat Bhushan wrote:
> Translate msi address if device is behind virtio-iommu.
> This logic is similar to vSMMUv3/Intel iommu emulation.
Why Intel?
>
> This RFC patch does not handle the case where both vsmmuv3 and
> virtio-iommu are available.
I think this should
Hi Bharat,
On 14/07/2017 09:25, Bharat Bhushan wrote:
> This patch allows virtio-iommu protection for PCI
> device-passthrough.
>
> MSI region is mapped by current version of virtio-iommu driver.
> This MSI region mapping in not getting pushed on hw iommu
> vfio_get_vaddr() allows only ram-region
On 17/08/17 16:26, Auger Eric wrote:
> Hi Linu, Jean,
>
> On 17/08/2017 15:39, Jean-Philippe Brucker wrote:
>> Hi Linu,
>>
>> On 17/08/17 12:26, Linu Cherian wrote:
>>> Hi Eric,
>>>
>>> On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote:
This series implements the virtio-iommu device.
On Thu, Aug 17, 2017 at 04:19:16PM +0200, Thomas Huth wrote:
> QEMU currently aborts unexpectedly when the user tries to add and
> remove a "spapr-tce-table" device:
>
> $ qemu-system-ppc64 -nographic -S -nodefaults -monitor stdio
> QEMU 2.9.92 monitor - type 'help' for more information
> (qemu) d
Hi Linu, Jean,
On 17/08/2017 15:39, Jean-Philippe Brucker wrote:
> Hi Linu,
>
> On 17/08/17 12:26, Linu Cherian wrote:
>> Hi Eric,
>>
>> On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote:
>>> This series implements the virtio-iommu device.
>>>
>>> This v3 mostly is a rebase on top of v2.1
On 20 July 2017 at 15:36, Programmingkid wrote:
> The GTK interface uses Control-Alt-G to ungrab the mouse. This patch changes
> the ungrab keys in the Cocoa interface to be consistent with the GTK
> interface. This patch has the added benefit of being able to send Control-Alt
> key combination
travis builds fail at HEAD at rc3 master with
block/nbd-client.c: In function ‘nbd_read_reply_entry’:
block/nbd-client.c:110:8: error: ‘ret’ may be used uninitialized in this
function [-Werror=uninitialized]
fix it by initializing 'ret' to 0
Signed-off-by: Igor Mammedov
---
block/nbd-clie
On 17/08/2017 18:14, Igor Mammedov wrote:
> travis builds fail at HEAD at rc3 master with
>
> block/nbd-client.c: In function ‘nbd_read_reply_entry’:
> block/nbd-client.c:110:8: error: ‘ret’ may be used uninitialized in this
> function [-Werror=uninitialized]
>
> fix it by initializing 'ret'
On 17 August 2017 at 17:16, Paolo Bonzini wrote:
> On 17/08/2017 18:14, Igor Mammedov wrote:
>> travis builds fail at HEAD at rc3 master with
>>
>> block/nbd-client.c: In function ‘nbd_read_reply_entry’:
>> block/nbd-client.c:110:8: error: ‘ret’ may be used uninitialized in this
>> function [
Hi Wanpeng,
On 08/16/2017 10:55 PM, Wanpeng Li wrote:
Cc Chandu,
On 8/16/17 1:00 AM, Brijesh Singh wrote:
Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
The following features bits have been added/removed co
Adding PCI passthrough before the guest start works fine (broken in 2.9 but now
fixed), but hotplug does not work anymore.
Anthony PERARD (3):
hw/acpi: Limit hotplug to root bus on legacy mode
hw/acpi: Move acpi_set_pci_info to pcihp
Revert "ACPI: don't call acpi_pcihp_device_plug_cb on xen"
Signed-off-by: Anthony PERARD
---
New patch in V3
---
hw/acpi/pcihp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index c420a388ea..9db3c2eaf2 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -273,7 +273,7 @@ static void pci_write(voi
This reverts commit 153eba4726dfa1bdfc31d1fe973b2a61b9035492.
This patch prevents PCI passthrough hotplug on Xen. Even if the Xen tool
stack prepares its own ACPI tables, we still rely on QEMU for hotplug
ACPI notifications.
The original issue is fixed by the two previous patch:
hw/acpi: Disall
This means that the function will be call and the property
acpi-pcihp-bsel will be set even if ACPI build is disable.
To do PCI passthrough with Xen, the property acpi-pcihp-bsel needs to be
set, but this was done only when ACPI tables are built which is not
needed for a Xen guest. The need for th
On 08/17/2017 11:14 AM, Igor Mammedov wrote:
> travis builds fail at HEAD at rc3 master with
>
> block/nbd-client.c: In function ‘nbd_read_reply_entry’:
> block/nbd-client.c:110:8: error: ‘ret’ may be used uninitialized in this
> function [-Werror=uninitialized]
>
> fix it by initializing 'r
On 17/08/2017 18:17, Peter Maydell wrote:
> On 17 August 2017 at 17:16, Paolo Bonzini wrote:
>> On 17/08/2017 18:14, Igor Mammedov wrote:
>>> travis builds fail at HEAD at rc3 master with
>>>
>>> block/nbd-client.c: In function ‘nbd_read_reply_entry’:
>>> block/nbd-client.c:110:8: error: ‘ret’
On 08/17/2017 01:54 AM, no-re...@patchew.org wrote:
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20170817043102.6322-1-f4...@amsat.org
Subject: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
[...]
Updating 3c8cf5a9c21ff8
On 17 August 2017 at 17:31, Paolo Bonzini wrote:
> On 17/08/2017 18:17, Peter Maydell wrote:
>> On 17 August 2017 at 17:16, Paolo Bonzini wrote:
>>> On 17/08/2017 18:14, Igor Mammedov wrote:
travis builds fail at HEAD at rc3 master with
block/nbd-client.c: In function ‘nbd_read_r
On 17/08/2017 18:37, Peter Maydell wrote:
> On 17 August 2017 at 17:31, Paolo Bonzini wrote:
>> On 17/08/2017 18:17, Peter Maydell wrote:
>>> On 17 August 2017 at 17:16, Paolo Bonzini wrote:
On 17/08/2017 18:14, Igor Mammedov wrote:
> travis builds fail at HEAD at rc3 master with
>
>
On 15/08/2017 19:00, Brijesh Singh wrote:
>
> The following features bits have been added/removed compare to Opteron_G5
>
> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
>fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
>xsaveopt, xsavec,
Paolo Bonzini writes:
> On 15/08/2017 09:30, Markus Armbruster wrote:
>> The stupid fix is to repeat libraries until the link succeeds:
>>
>> test-util-obj-y = libqemuutil.a libqemustub.a libqemuutil.a
>>
>> You may have seen this with -lX11 if you're old enough.
>>
>> ld(1) suggests the l
* Peter Xu (pet...@redhat.com) wrote:
> On Fri, Jul 14, 2017 at 06:15:54PM +0100, Dr. David Alan Gilbert wrote:
> > * Peter Xu (pet...@redhat.com) wrote:
> > > On Wed, Jun 28, 2017 at 08:00:34PM +0100, Dr. David Alan Gilbert (git)
> > > wrote:
> > > > From: "Dr. David Alan Gilbert"
> > > >
> > >
On Thu, Aug 17, 2017 at 10:02 AM, Markus Armbruster wrote:
> Paolo Bonzini writes:
>
>> On 15/08/2017 09:30, Markus Armbruster wrote:
>>> The stupid fix is to repeat libraries until the link succeeds:
>>>
>>> test-util-obj-y = libqemuutil.a libqemustub.a libqemuutil.a
>>>
>>> You may have see
---
include/exec/helper-head.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index 1cfc43b9ff..3fb4c3fc39 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -23,6 +23,7 @@
#define GET_TCGV_i32 GET_TCGV_I32
Currently it only makes sense for globals - i.e. registers directly
mapped to CPUEnv.
---
tcg/README | 1 +
tcg/tcg.h | 20
2 files changed, 21 insertions(+)
diff --git a/tcg/README b/tcg/README
index f116b7b694..e0868d95b4 100644
--- a/tcg/README
+++ b/tcg/README
@@ -57,6
Although the other types are aliases lets make it clear what TCG types
are available.
Signed-off-by: Alex Bennée
---
tcg/README | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/tcg/README b/tcg/README
index 03bfb6acd4..f116b7b694 100644
--- a/tcg/README
+++ b/tcg/READ
Register the vector registers with TCG.
Signed-off-by: Alex Bennée
---
target/arm/translate-a64.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 805af51900..b5f48605a7 100644
--- a/target/ar
Hi,
With upcoming work on SVE I've been looking at the way we implement
vector registers in QEMU's TCG. The current orthodoxy is to decompose
the vector into a series of TCG registers, often calling a helper
function the calculation of each element. The result of the helper is
then is then stored
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b39d64aa0b..cdd47cb868 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -457,8 +457,8 @@ typedef struct CPUARMState {
As we operate directly on the vectors in memory we pass around the
address for TCG_TYPE_VECTOR. Currently only helpers ever see these
values but if we were to generate simd backend instructions they would
load directly from the backing store.
We also need to ensure when copying from one temp regis
This is used to pass constant information to the helper. This includes
immediate data and element counts/offsets.
Signed-off-by: Alex Bennée
---
target/arm/advsimd_helper_flags.h | 50 +++
target/arm/helper-a64.c | 1 +
target/arm/translate-a64.c
These instructions show up in the ffmpeg profile from the
ff_simple_idct_put_neon function.
WARNING: this is experimental and essentially shortcuts to the
vectorised helper for the one instruction that shows up a lot in the
ffmpeg trace. Otherwise it falls through to the normal code
generation. We
These are the integer registers as will become clear when we start
declaring the vector ones.
Signed-off-by: Alex Bennée
---
target/arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..80
Dne 17.8.2017 v 07:24 Markus Armbruster napsal(a):
> Lukáš Doktor writes:
>
>> Dne 16.8.2017 v 18:58 Markus Armbruster napsal(a):
>>> Lukáš Doktor writes:
>>>
Dne 15.8.2017 v 14:31 Markus Armbruster napsal(a):
> Lukáš Doktor writes:
>
>> No actual code changes, just several pyl
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20170817180404.29334-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n
QEMU currently crashes when trying to use a 'pc-dimm' on the pseries
machine without specifying its 'memdev' property. Let's add a sanity
check to the pre_plug handler to fix this issue.
Signed-off-by: Thomas Huth
---
hw/ppc/spapr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(
Hi Paolo,
On 08/17/2017 11:45 AM, Paolo Bonzini wrote:
On 15/08/2017 19:00, Brijesh Singh wrote:
The following features bits have been added/removed compare to Opteron_G5
Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
fsgsbase, bmi1, avx2, smep, bmi2, rdseed, a
On 08/17/2017 12:54 AM, Markus Armbruster wrote:
> John Snow writes:
>
>> On 08/14/2017 05:57 PM, Eduardo Habkost wrote:
>>> Example output when using "-machine q35":
>>>
>>> {
>>> "available": true,
>>> "count": 1,
>>> "device-types": [
>>> "ide-device"
>>> ],
>>> "
In preperation for future work let's manually create the Xilnx machines.
This will allow us to set properties for the machines in the future.
Signed-off-by: Alistair Francis
---
hw/arm/xlnx-zcu102.c | 75 +++-
1 file changed, 68 insertions(+), 7 d
The EL2 and EL3 work is working well now and interanlly we now have
tests that expect to start in EL3 and transition through EL2 to EL1. To
make this easy to run let's expose the secure property to the machine
and then use that to enable EL2.
This series also does some machine/name tidying up and
If the user sets the secure property to true we want to enalbe both EL2
and EL3.
Signed-off-by: Alistair Francis
---
hw/arm/xlnx-zynqmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 9eceadbdc8..d6ca5dcd4e 100644
--- a/hw/
The EP108 is the same as the ZCU102, mark it as deprecated as we don't
need two machines.
Signed-off-by: Alistair Francis
---
hw/arm/xlnx-zcu102.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 8a53221d0a..54207ba095 100644
If you forget to add -cpu 486 or -cpu pentium your disk image will be
corrupted and the display will display random characters.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1706296
Title:
Booting
On 08/17/2017 02:02 PM, Markus Armbruster wrote:
Paolo Bonzini writes:
On 15/08/2017 09:30, Markus Armbruster wrote:
The stupid fix is to repeat libraries until the link succeeds:
test-util-obj-y = libqemuutil.a libqemustub.a libqemuutil.a
You may have seen this with -lX11 if you're old
This workaround should help you avoid problems with Windows NT 4.0.
Create the disk image for the hard drive that is 4GB or less in size:
qemu-img create -f qcow2 .qcow2 4G
Run QEMU booting from the CD-ROM. I assume you used the Windows NT 4.0
workstation CD.
qemu-system-i386 -cpu pentium -vga
On 08/17/2017 02:55 PM, Alistair Francis wrote:
On 15/08/2017 09:30, Markus Armbruster wrote:
The stupid fix is to repeat libraries until the link succeeds:
test-util-obj-y = libqemuutil.a libqemustub.a libqemuutil.a
[...]
Sticking '-Wp,-(' and '-Wp,-)' into the command line I get from
On 08/17/2017 11:03 AM, Alex Bennée wrote:
> Although the other types are aliases lets make it clear what TCG types
> are available.
>
> Signed-off-by: Alex Bennée
> ---
> tcg/README | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 08/17/2017 11:03 AM, Alex Bennée wrote:
> Currently it only makes sense for globals - i.e. registers directly
> mapped to CPUEnv.
> ---
> tcg/README | 1 +
> tcg/tcg.h | 20
> 2 files changed, 21 insertions(+)
I'm not keen on this. I know it makes for nicer intermediate
On 08/17/2017 11:03 AM, Alex Bennée wrote:
> As we operate directly on the vectors in memory we pass around the
> address for TCG_TYPE_VECTOR. Currently only helpers ever see these
> values but if we were to generate simd backend instructions they would
> load directly from the backing store.
>
>
On 08/17/2017 11:04 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> target/arm/cpu.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 08/17/2017 11:04 AM, Alex Bennée wrote:
> -static const char *regnames[] = {
> +static const char *x_regnames[] = {
> "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
> "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
> "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
On 08/17/2017 11:04 AM, Alex Bennée wrote:
> +int32_t *rd = (int32_t *) d;
> +int16_t *rn = (int16_t *) n;
> +int16_t rm = (int16_t) m;
> +int i;
> +
> +#pragma GCC ivdep
> +for (i = 0; i < opr_elt; ++i) {
> +rd[i] = rn[i + doff_elt] * rm;
> +}
You need to run t
Hi
On Tue, Aug 8, 2017 at 8:04 AM, Kevin Wolf wrote:
> Am 04.08.2017 um 06:53 hat Anatol Pomozov geschrieben:
>> Hi Kevin
>>
>> Thanks for the information.
>>
>> So I sounds like we do want multiboot to load all sections regardless
>> of its segments info. To achieve it we need to read sections h
On Thu Aug 17, 2017 at 05:26:53PM +0200, Auger Eric wrote:
> Hi Linu, Jean,
>
> On 17/08/2017 15:39, Jean-Philippe Brucker wrote:
> > Hi Linu,
> >
> > On 17/08/17 12:26, Linu Cherian wrote:
> >> Hi Eric,
> >>
> >> On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrote:
> >>> This series implem
On 08/04/17 12:49, Paolo Bonzini wrote:
> On 04/08/2017 10:36, Hannes Reinecke wrote:
>> The LUN0 emulation is just that, an emulation for a non-existing
>> LUN0. So we should be returning LUN_NOT_SUPPORTED for any request
>> coming from any other LUN.
>> And we should be aborting unhandled command
On 07.08.2017 19:50, Paolo Bonzini wrote:
>Not much to say, unfortunately. It's pretty much the same capabilities
>as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It
>also lacks FlexPriority compared to the Conroe I had checked.
>
>It's not great that even the revert patch do
On 17.08.2017 22:58, Gerhard Wiesinger wrote:
>
> On 07.08.2017 19:50, Paolo Bonzini wrote:
>
> >Not much to say, unfortunately. It's pretty much the same capabilities
> >as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It
> >also lacks FlexPriority compared to the Conroe I had
On 08/17/2017 04:52 AM, David Gibson wrote:
On Tue, Aug 15, 2017 at 05:28:46PM -0300, Daniel Henrique Barboza wrote:
This patch is a follow up on the discussions that started with
Laurent's patch series "spapr: disable hotplugging without OS" [1]
and discussions made at patch "spapr: reset DRC
Using C structs makes the code more readable and prevents type conversion
errors.
Borrow multiboot1 header from GRUB project.
Signed-off-by: Anatol Pomozov
---
hw/i386/multiboot.c| 124 +-
hw/i386/multiboot_header.h | 254 +
Multiboot may load section headers and all sections (even those that are
not part of any segment) to target memory.
Tested with an ELF application that uses data from strings table
section.
Signed-off-by: Anatol Pomozov
---
hw/core/loader.c | 8 ++--
hw/i386/multiboot.c | 83 +++
x86 is not the only architecture supported by multiboot.
For example GRUB supports MIPS architecture as well.
Signed-off-by: Anatol Pomozov
---
hw/i386/multiboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c
index 19113c0fce..a492
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 137 -
1 file changed, 87 insertions(+), 50 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..025354f983 100644
--- a/target/arm/transla
Nothing uses or enables them yet.
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 5 +
tcg/tcg.c | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index dd97095af5..1277caed3d 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -256,6 +256,11 @@ typedef struc
Nothing uses or implements them yet.
Signed-off-by: Richard Henderson
---
tcg/tcg-opc.h | 89 +++
tcg/tcg.h | 24
2 files changed, 113 insertions(+)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 956fb1e9f3..9162125f
101 - 200 of 261 matches
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