On 07/15/2017 03:43 PM, Emilio G. Cota wrote:
On Wed, Jul 12, 2017 at 13:06:23 -1000, Richard Henderson wrote:
You've got a problem here in that you're not including CF_COUNT_MASK in the
hash and you dropped the flush when changing to parallel_cpus = true. That
means you could find an old TB wi
On 14/07/2017 13:37, Mark Cave-Ayland wrote:
On 14/07/17 11:25, Marcel Apfelbaum wrote:
On 14/07/2017 12:59, Mark Cave-Ayland wrote:
On 11/07/17 22:44, Mark Cave-Ayland wrote:
For some machines it is impossible to plug devices into a particular
PCI bus
slot, e.g. for a real Ultra 5 there are
According to PCI spec. bit 1 of command
register (PCI_COMMAND_MEMORY) controls
a device's response to memory space accesses.
A value of 0 disables the device response.
A value of 1 allows the device to respond
to memory space accesses.
Current behavior introduced by commit
commit 1c380f9460522f
** Attachment added: "Statically compiled test program for mips"
https://bugs.launchpad.net/qemu/+bug/1704638/+attachment/4915584/+files/testpthsigmask-mips
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** Attachment added: "Statically compiled test program for mips64"
https://bugs.launchpad.net/qemu/+bug/1704638/+attachment/4915585/+files/testpthsigmask-mips64
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Public bug reported:
A program that is statically linked and invokes a weak pointer should
crash (because the weak pointer evaluates to NULL).
With qemu in user mode, for mips and mips64, it hangs. The process needs
to be killed with "kill -9".
How to reproduce for mips:
- Compile the program: m
On 07/13/2017 06:15 PM, Eduardo Habkost wrote:
> On Thu, Jul 13, 2017 at 01:54:01PM +0200, Halil Pasic wrote:
>>
>>
>> On 07/12/2017 08:29 PM, Eduardo Habkost wrote:
>>> On Wed, Jul 12, 2017 at 07:33:15PM +0200, Halil Pasic wrote:
On 07/11/2017 02:43 AM, Eduardo Habkost wrote:
On 07/12/2017 08:48 PM, Eduardo Habkost wrote:
> On Wed, Jul 12, 2017 at 08:06:14PM +0200, Halil Pasic wrote:
>>
>>
>> On 07/11/2017 02:43 AM, Eduardo Habkost wrote:
>>> Test case to detect the bug fixed by commit
>>> "qdev: fix the order compat and global properties are applied".
>>>
>>> Signed-
On 2017-07-15 16:30, Richard Henderson wrote:
> On 07/15/2017 12:14 PM, Aurelien Jarno wrote:
> > On 2017-07-06 16:20, Richard Henderson wrote:
> > > For uniprocessors, SH4 uses optimistic restartable atomic sequences.
> > > Upon an interrupt, a real kernel would simply notice magic values in
> > >
On 2017-07-15 16:33, Richard Henderson wrote:
> On 07/15/2017 12:59 PM, Aurelien Jarno wrote:
> > On 2017-07-06 16:20, Richard Henderson wrote:
> > > If a signal is delivered during the execution of a delay slot,
> > > or a gUSA region, clear those bits from the environment so that
> > > the signal
** Attachment added: "Statically compiled test program for sparc64"
https://bugs.launchpad.net/qemu/+bug/1704658/+attachment/4915667/+files/testdup3-sparc64
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Public bug reported:
In qemu user mode, for hppa and sparc64 targets, the parameter of the
dup3 is not passed correctly when it contains the O_CLOEXEC flag.
When the attached program runs, the expected output is:
errno=9=EBADF
How to reproduce on hppa:
- Compile the program: hppa-linux-gnu-gcc-5
** Attachment added: "Statically compiled test program for hppa"
https://bugs.launchpad.net/qemu/+bug/1704658/+attachment/4915666/+files/testdup3-hppa
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I see this bug for hppa, sparc64.
I don't see it for m68k, mips, mips64, powerpc, powerpc64.
Most likely because the binary values of O_CLOEXEC on hppa and sparc64 are
different than on other platforms. Looking in the glibc source code:
$ grep -r 'define.*O_CLOEXEC' glibc
glibc/bits/fcntl.h:# def
On 16/07/2017 11:29, Dmitry Fleytman wrote:
According to PCI spec. bit 1 of command
register (PCI_COMMAND_MEMORY) controls
a device's response to memory space accesses.
A value of 0 disables the device response.
A value of 1 allows the device to respond
to memory space accesses.
Hi Dmitry,
Hello I have just made a new Unicore32 page and was wondering if the
information on it was correct. Any feedback or additions you wish to add would
be appreciated. Thank you.
http://wiki.qemu.org/Documentation/Platforms/Unicore32
On 14/07/17 19:56, Eduardo Habkost wrote:
>>> Why do you need the full struct declaration to be exposed in the
>>> header?
>>
>> Different board code wants to hook up "comb_iomem" manually to different
>> address spaces, so they need to access the field directly. This is the
>> ultimate goal of th
On 16/07/17 08:28, Marcel Apfelbaum wrote:
>>> As in prev version, other than the minor comment
>>> on replacing "if (...) return true; else return false"
>>> with the actual value, I am OK with it.
>>
>> Okay great! So change pci_bus_devfn_available() to something like this?
>>
>> static bool pci
On 07/16/2017 05:18 AM, Aurelien Jarno wrote:
That said for further improvements did you consider decoding the gUSA
section in a helper. It might avoid having to emulate the atomic
sequence with 3 TBs in the worst case (the original one, the one to
decode the sequence and the one holding the excl
On (Thu) 13 Jul 2017 [18:32:07], Marc-André Lureau wrote:
> I used the clang-tidy qemu-round check to generate the fix:
> https://github.com/elmarco/clang-tools-extra
>
> Signed-off-by: Marc-André Lureau
Reviewed-by: Amit Shah
Amit
--
http://log.amitshah.net/
Reusing the have_tb_lock name, which is also defined in translate-all.c,
makes code reviewing unnecessarily harder.
Avoid potential confusion by renaming the local have_tb_lock variable
to something else.
Signed-off-by: Emilio G. Cota
---
accel/tcg/cpu-exec.c | 10 +-
1 file changed, 5
Groundwork for supporting multiple TCG contexts.
Note that having n_tcg_ctxs is unnecessary. However, it is
convenient to have it, since it will simplify iterating over the
array: we'll have just a for loop instead of having to iterate
over a NULL-terminated array (which would require n+1 elems)
o
v1:
https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg02059.html
Thanks all for your comments on v1.
This v2 patchset applies on top of stefanha's tracing tree (9212a18e371):
https://github.com/stefanha/qemu/tree/tracing
That tree has some changes (per-vcpu TCG tracing) that would conf
Commit e7b161d573 ("vl: add tcg_enabled() for tcg related code") adds
a check to exit the program when !tcg_enabled() while parsing the -tb-size
flag.
It turns out that when the -tb-size flag is evaluated, tcg_enabled() can
only return 0, since it is set (or not) much later by configure_accelerato
Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried
the increment of tlb_flush_count under TLB_DEBUG. This results in
"info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG.
Besides, under MTTCG tlb_flush_count is updated by several threads,
so in order not to lose counts we
This gets rid of some ifdef checks while ensuring that the debug code
is compiled, which prevents bit rot.
Suggested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/tr
This check is redundant because it is already performed by the only
caller of dump_exec_info -- the caller was updated by b7da97eef
("monitor: Check whether TCG is enabled before running the "info jit"
code").
Checking twice wouldn't necessarily be too bad, but here the check also
returns with tb_
This avoids duplicating code. cpu_exec_step will also use the
new common function once we integrate parallel_cpus into tb->cflags.
Performance-wise, I measured a small improvement when booting debian-arm.
Note that inlining pays off:
Performance counter stats for 'taskset -c 0 qemu-system-arm \
Whenever there is an overflow in code_gen_buffer (e.g. we run out
of space in it and have to flush it), the code_time profiling counter
ends up with an invalid value (that is, code_time -= profile_getclock(),
without later on getting += profile_getclock() due to the goto).
Fix it by using the ti v
Thereby decoupling the resulting translated code from the current state
of the system.
Signed-off-by: Emilio G. Cota
---
target/sparc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index aa6734d..0274e83 100644
It is only used by this object, and it's not exported to any other.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/tran
Groundwork for supporting multiple TCG contexts.
Compile-tested for all targets on an x86_64 host.
Suggested-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
tcg/tci.c | 552 +++---
1 file changed, 279 insertions(+), 273 deletions(
This gets rid of the need to check the tb->invalid bit during lookups.
After this change we do not need atomics to operate on tb->invalid: setting
and checking its value is serialised with tb_lock.
Signed-off-by: Emilio G. Cota
---
accel/tcg/cpu-exec.c | 3 +--
accel/tcg/translate-all.c |
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Emilio G. Cota
---
tcg/i386/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 01e3b4e..06df0
Now that all code generation has been converted to check CF_PARALLEL, we can
generate !CF_PARALLEL code without having yet set !parallel_cpus --
and therefore without having to be in the exclusive region during
cpu_exec_step_atomic.
While at it, merge cpu_exec_step into cpu_exec_step_atomic.
Sign
Thereby decoupling the resulting translated code from the current state
of the system.
The tb->cflags field is not passed to tcg generation functions. So
we add a bit to TCGContext, storing there whether CF_PARALLEL is set
before translating every TB.
Most architectures have <= 32 registers, whic
This gets rid of a hole in struct TranslationBlock.
Signed-off-by: Emilio G. Cota
---
include/exec/exec-all.h | 3 +--
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/translate-all.c | 3 +--
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/exec/exec-all.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 887d7b3..28e3a24 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-a
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Emilio G. Cota
---
tcg/mips/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 85756b8..56db2
This will enable us to decouple code translation from the value
of parallel_cpus at any given time. It will also help us minimize
TB flushes when generating code via EXCP_ATOMIC.
Note that the declaration of parallel_cpus is brought to exec-all.h
to be able to define there the inlines. The inlines
This prevents bit rot by ensuring the debug code is compiled when
building a user-mode target.
Unfortunately the helpers are user-mode-only so we cannot fully
get rid of the ifdef checks. Add a comment to explain this.
Suggested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/trans
We don't really free anything in this function anymore; we just remove
the TB from the binary search tree.
Suggested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/exec/exec-all.h | 2 +-
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/translate-all.c | 6 +++---
3 files changed, 5 ins
Groundwork for supporting multiple TCG contexts.
The hash table becomes read-only after it is filled in,
so we can save space by keeping just a global pointer to it.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
tcg/tcg.h | 2 --
tcg/tcg.c | 10 +++
This gets rid of an ifdef check while ensuring that the debug code
is compiled, which prevents bit rot.
Suggested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/translate-all.
Since commit 6e3b2bfd6 ("tcg: allocate TB structs before the
corresponding translated code") we are not fully utilizing
code_gen_buffer for translated code, and therefore are
incorrectly reporting the amount of translated code as well as
the average host TB size. Address this by:
- Making the cons
Groundwork for supporting multiple TCG contexts.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/exec/gen-icount.h | 7 +++
tcg/tcg.h | 2 ++
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/exec/gen-ic
Groundwork for supporting multiple TCG contexts.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/exec/tb-context.h | 2 ++
tcg/tcg.h | 2 --
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/translate-all.c | 57 +++
Thereby decoupling the resulting translated code from the current state
of the system.
Signed-off-by: Emilio G. Cota
---
target/s390x/helper.h | 3 +++
target/s390x/mem_helper.c | 50 +++
target/s390x/translate.c | 20 +++
3 files
And fix the following warning when DEBUG_TB_INVALIDATE is enabled
in translate-all.c:
CC mipsn32-linux-user/accel/tcg/translate-all.o
/data/src/qemu/accel/tcg/translate-all.c: In function ‘tb_alloc_page’:
/data/src/qemu/accel/tcg/translate-all.c:1201:16: error: format ‘%lx’ expects
argumen
Thereby decoupling the resulting translated code from the current state
of the system.
Signed-off-by: Emilio G. Cota
---
target/m68k/helper.h| 2 ++
target/m68k/op_helper.c | 32
target/m68k/translate.c | 12 ++--
3 files changed, 40 insertions(+), 6
It is unlikely that we will ever want to call this helper passing
an argument other than the current PC. So just remove the argument,
and use the pc we already get from cpu_get_tb_cpu_state.
This change paves the way to having a common "tb_lookup" function.
Signed-off-by: Emilio G. Cota
---
tcg
These only depend on the host and therefore belong in the common
osdep, not in a target-dependent object.
Signed-off-by: Emilio G. Cota
---
include/exec/cpu-all.h | 2 --
include/qemu/osdep.h | 8
exec.c | 5 +
util/osdep.c | 9 +
4 files changed,
Thereby decoupling the resulting translated code from the current state
of the system.
Signed-off-by: Emilio G. Cota
---
target/i386/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 291c577..c5e4d77 100644
For some machines it is impossible to plug devices into a particular PCI bus
slot, e.g. for a real Ultra 5 there are 2 PCI bridges attached to the root
bus behind which all devices must be plugged. Ignoring this rule will cause
problems with interrupt routing since the interrupt numbers are calcula
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 49 ++-
1 file changed, 6 insertions(+), 43 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index fd3e4a0..913b1c5 100644
--- a/accel/tcg/translate-all.c
+++
Thereby decoupling the resulting translated code from the current state
of the system.
Signed-off-by: Emilio G. Cota
---
target/hppa/helper.h| 2 ++
target/hppa/op_helper.c | 32
target/hppa/translate.c | 12 ++--
3 files changed, 40 insertions(+), 6
Will come in handy very soon.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
tcg/tcg.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5afb80a..e8aae1f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -115,6
In preparation for adding tc.size to be able to keep track of
TB's using the binary search tree implementation from glib.
Signed-off-by: Emilio G. Cota
---
include/exec/exec-all.h | 20 ++--
accel/tcg/cpu-exec.c | 6 +++---
accel/tcg/translate-all.c | 20 ++---
TCG regions already have a guard page.
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 47 ---
1 file changed, 12 insertions(+), 35 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index c30d400..98aa63e 10
Thereby decoupling the resulting translated code from the current state
of the system.
Signed-off-by: Emilio G. Cota
---
target/arm/helper-a64.h| 4
target/arm/helper-a64.c| 38 --
target/arm/op_helper.c | 7 ---
target/arm/translate-a64
This is groundwork for supporting multiple TCG contexts.
To avoid scalability issues when profiling info is enabled, this patch
makes the profiling info counters distributed via the following changes:
1) Consolidate profile info into its own struct, TCGProfile, which
TCGContext also includes.
Groundwork for supporting multiple TCG contexts.
Signed-off-by: Emilio G. Cota
---
tcg/tcg.h | 12
tcg/optimize.c | 40 +++-
2 files changed, 35 insertions(+), 17 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 569f823..175d4de 100644
Signed-off-by: Emilio G. Cota
---
include/qemu/osdep.h | 2 ++
util/osdep.c | 40
2 files changed, 42 insertions(+)
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index 3cb36e6..dcecfbc 100644
--- a/include/qemu/osdep.h
+++ b/include/qe
Also touch up the logic in do_pci_register_device() accordingly.
Signed-off-by: Mark Cave-Ayland
---
hw/pci/pci.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 0c6f74a..efc9c86 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -9
This is a prerequisite for supporting multiple TCG contexts, since
we will have threads generating code in separate regions of
code_gen_buffer.
For this we need a new field (.size) in struct tb_tc to keep
track of the size of the translated code. This field adds a 4-byte
hole to the struct (and th
This enables parallel TCG code generation. However, we do not take
advantage of it yet since tb_lock is still held during tb_gen_code.
In user-mode we use a single TCG context; see the documentation
added to tcg_region_init for the rationale.
Note that targets do not need any conversion: targets
This is groundwork for supporting multiple TCG contexts.
The naive solution here is to split code_gen_buffer statically
among the TCG threads; this however results in poor utilization
if translation needs are different across TCG threads.
What we do here is to add an extra layer of indirection, a
Groundwork for supporting multiple TCG contexts.
The core of this patch is this change to tcg/tcg.h:
> -extern TCGContext tcg_ctx;
> +extern TCGContext tcg_init_ctx;
> +extern TCGContext *tcg_ctx;
Note that for now we set *tcg_ctx to whatever TCGContext is passed
to tcg_context_init -- in this c
Add a new slot_reserved_mask bitmask to PCIBus indicating whether or not each
PCI slot on the bus is reserved. Ensure that it is initialised to zero to
maintain the existing behaviour that all slots are available by default, and
add the additional check with appropriate error reporting to
do_pci_re
On 2017-07-16 09:35, Richard Henderson wrote:
> On 07/16/2017 05:18 AM, Aurelien Jarno wrote:
> > That said for further improvements did you consider decoding the gUSA
> > section in a helper. It might avoid having to emulate the atomic
> > sequence with 3 TBs in the worst case (the original one, t
On 2017-07-16 01:22, Aurelien Jarno wrote:
> On 2017-07-06 16:20, Richard Henderson wrote:
> > As for other targets, cmpxchg isn't quite right for ll/sc,
> > suffering from an ABA race, but is sufficient to implement
> > portable atomic operations.
> >
> > Signed-off-by: Richard Henderson
> > ---
On 07/16/2017 11:43 AM, Aurelien Jarno wrote:
Indeed, if the same atomic code is used often it might be better to have
it cached. That said it's only true for TB that are recognized, as IIRC
TB with the exclusive lock are not cached.
At the moment they are not.
But in Emilio's multi-threaded t
On 2017-07-16 11:59, Richard Henderson wrote:
> On 07/16/2017 11:43 AM, Aurelien Jarno wrote:
> > Indeed, if the same atomic code is used often it might be better to have
> > it cached. That said it's only true for TB that are recognized, as IIRC
> > TB with the exclusive lock are not cached.
>
>
On Fri, Jul 14, 2017 at 06:13:58PM +0200, Cédric Le Goater wrote:
> But when a guest initializes radix mode, it issues a H_REGISTER_PROC_TBL
> to update the LPCR of all CPUs. Hot-plugged CPUs inherit from the same
> setting under KVM but not under TCG. So, Let's check for radix and update
> the def
On Fri, Jul 14, 2017 at 06:40:34AM +, Bharat Bhushan wrote:
> Hi Peter,
>
> > -Original Message-
> > From: Peter Xu [mailto:pet...@redhat.com]
> > Sent: Friday, July 14, 2017 7:48 AM
> > To: Eric Auger
> > Cc: eric.auger@gmail.com; peter.mayd...@linaro.org;
> > alex.william...@red
On Fri, Jul 14, 2017 at 12:25:13PM +0100, Jean-Philippe Brucker wrote:
> Hi Peter,
>
> On 14/07/17 03:17, Peter Xu wrote:
> >
> > [...]
> >
> >> static int virtio_iommu_unmap(VirtIOIOMMU *s,
> >> @@ -133,10 +227,64 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s,
> >> uint64_t virt_addr = l
On Fri, Jul 14, 2017 at 03:28:09PM +0800, Jason Wang wrote:
>
>
> On 2017年07月14日 12:32, Peter Xu wrote:
> >On Thu, Jul 13, 2017 at 04:48:42PM +0800, Jason Wang wrote:
> >>
> >>On 2017年07月12日 16:13, Peter Xu wrote:
> >>>It is not wise to disgard all the IOTLB cache when cache size reaches
> >>>max
Hi Laszlo
This is a good summary.
One minor comment is:
1) Tcg2Pei/Dxe are arechitecture driver. We do not expect a platform modify
them.
2) Tcg2ConfigPei/Dxe are platform sample driver. A platform may have its own
version based upon platform requirement. For example, if a platform supports
fTP
> From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com]
> Sent: Friday, July 14, 2017 7:26 PM
>
> On 14/07/17 08:20, Tian, Kevin wrote:
> >> From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com]
> >> Sent: Friday, July 7, 2017 11:15 PM
> >>
> >> On 07/07/17 07:21, Tian, K
Signed-off-by: Fam Zheng
---
hw/intc/arm_gicv3_its_kvm.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index 1f8991b..39903d5 100644
--- a/hw/intc/arm_gicv3_its_kvm.c
+++ b/hw/intc/arm_gicv3_its_k
Signed-off-by: Fam Zheng
---
hw/arm/xlnx-zynqmp.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 64f52f8..cd8a4aa 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -140,11 +140,6 @@ static void xlnx_zynqmp
Signed-off-by: Fam Zheng
---
hw/arm/armv7m.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index c8a11f2..8efc4e8 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -97,12 +97,6 @@ static void bitband_init(Object *obj)
BitBan
This is the arm part that was left out from:
https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg04006.html
Make use of the new DEFINE_PROP_LINK, in favor of open coded the
object_property_add_link. The advantage of it is the property now get reflected
in the info qtree output, for a bit mor
Signed-off-by: Fam Zheng
---
hw/net/xilinx_axienet.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 5ffa739..d4c2c89 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -989,18 +989,6
Signed-off-by: Fam Zheng
---
hw/arm/armv7m.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 8efc4e8..1c837da 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -132,12 +132,6 @@ static void armv7m_instance_init(Object *obj)
Signed-off-by: Fam Zheng
---
hw/dma/xilinx_axidma.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index 3987b5f..9b48103 100644
--- a/hw/dma/xilinx_axidma.c
+++ b/hw/dma/xilinx_axidma.c
@@ -562,18 +562,6 @@ st
On Fri, Jul 14, 2017 at 06:15:54PM +0100, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > On Wed, Jun 28, 2017 at 08:00:34PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > Stash the RAMBlock and offset for later use looki
On Fri, Jul 14, 2017 at 05:32:10PM +0100, Dr. David Alan Gilbert wrote:
> * Eduardo Habkost (ehabk...@redhat.com) wrote:
> > On Fri, Jul 14, 2017 at 01:04:23PM +0800, Peter Xu wrote:
> > > On Wed, Jul 12, 2017 at 04:05:58PM -0300, Eduardo Habkost wrote:
> > > > On Wed, Jul 12, 2017 at 02:53:40PM +0
Hello all,
Recently, I met a werid question when i run a VM in the following platfrom:
Vmware Vsphere 6.0/6.5
|-- centos 7.3 nested VM (with qemu 2.8, kmod 4.4.11, seabios 1.10)
|-- VM (with virtio-scsi controller, modern mode)
VM MUST hang in seabios when try to mmio write during virt
On Fri, Jul 14, 2017 at 12:57:15PM -0300, Eduardo Habkost wrote:
> On Fri, Jul 14, 2017 at 12:23:06PM +0800, Peter Xu wrote:
> > On Wed, Jul 12, 2017 at 08:02:40PM +0100, Dr. David Alan Gilbert wrote:
> > > * Peter Xu (pet...@redhat.com) wrote:
> > > > We have the MigrationState as QDev now (which
On Thu, 06/29 15:27, Paolo Bonzini wrote:
> diff --git a/block/qed.c b/block/qed.c
> index db390efdbd..8228a50f68 100644
> --- a/block/qed.c
> +++ b/block/qed.c
> @@ -363,6 +363,15 @@ static void coroutine_fn
> bdrv_qed_co_drain(BlockDriverState *bs)
> }
> }
>
> +static void bdrv_qed_init_
From: Paolo Bonzini
This will let the callback take a CoMutex in the next patch.
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Fam Zheng
Signed-off-by: Paolo Bonzini
Message-Id: <20170629132749.997-8-pbonz...@redhat.com>
Signed-off-by: Fam Zheng
---
block/io.c| 42 ++
From: Paolo Bonzini
Reviewed-by: Eric Blake
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Fam Zheng
Signed-off-by: Paolo Bonzini
Message-Id: <20170629132749.997-2-pbonz...@redhat.com>
Signed-off-by: Fam Zheng
---
block/qcow2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --gi
The following changes since commit 4871b51b9241b10f4fd8e04bbb21577886795e25:
vmgenid-test: use boot-sector infrastructure (2017-07-14 17:03:03 +0100)
are available in the git repository at:
git://github.com/famz/qemu.git tags/block-and-testing-pull-request
for you to fetch changes up to 978
From: "Daniel P. Berrange"
When trying to debug problems with tests it is natural to set
DEBUG=1 when starting the docker environment. Unfortunately
this has a side-effect of enabling an eth0 network interface
in the container, which changes the operating environment of
the test suite. IOW tests
From: Paolo Bonzini
These functions are more efficient in the presence of contention.
qemu_co_rwlock_downgrade also guarantees not to block, which may
be useful in some algorithms too.
Reviewed-by: Eric Blake
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Fam Zheng
Signed-off-by: Paolo Bonzini
Me
From: Paolo Bonzini
This will be used in the next patch, which will call bdrv_qed_do_open
with a CoMutex taken. bdrv_qed_init_state provides a nice place to
initialize it.
Signed-off-by: Paolo Bonzini
Message-Id: <20170629132749.997-9-pbonz...@redhat.com>
Reviewed-by: Eric Blake
Reviewed-by:
From: Paolo Bonzini
Reviewed-by: Eric Blake
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Fam Zheng
Signed-off-by: Paolo Bonzini
Message-Id: <20170629132749.997-6-pbonz...@redhat.com>
Signed-off-by: Fam Zheng
---
block/vvfat.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff -
From: Paolo Bonzini
This part is never called for in-place writes, move it away to avoid
the "backwards" coding style typical of callback-based code.
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Fam Zheng
Signed-off-by: Paolo Bonzini
Message-Id: <20170629132749.997-7-pbonz...@redhat.com>
Signed-
From: Paolo Bonzini
The VirtualBox driver is using a mutex to order all allocating writes,
but it is not protecting accesses to the bitmap because they implicitly
happen under the AioContext mutex. Change this to use a CoRwlock
explicitly.
Reviewed-by: Eric Blake
Reviewed-by: Stefan Hajnoczi
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