From: Bharata B Rao
Ensure that the unplugged CPU thread is destroyed and the waiting
thread is notified about it. This is needed for CPU unplug to work
correctly in MTTCG mode.
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
cpus.c | 6 ++
1
From: Nikunj A Dadhania
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 50b6d4d..4a1f24a 100644
--- a/target
From: Sam Bobroff
ics_get_kvm_state() "or"s set bits into irq->status but does not mask
out clear bits.
Correct this by initializing the IRQ status to zero before adding bits
to it.
Signed-off-by: Sam Bobroff
Signed-off-by: David Gibson
---
hw/intc/xics_kvm.c | 1 +
1 file changed, 1 inserti
From: Nikunj A Dadhania
In case where the conditional write is the first write to the page,
TLB_NOTDIRTY will be set and stop_the_world is triggered. Handle this as
a special case and set the dirty bit. After that fall through to the
actual atomic instruction below.
Signed-off-by: Nikunj A Dadha
From: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
hw/ppc/mac_oldworld.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 5df94e2..97bb854 100644
--- a/hw/ppc/mac_oldwo
The following changes since commit dd1559bb267becbb838de41132ef60771d183e5d:
Merge remote-tracking branch 'elmarco/tags/chr-tests-pull-request' into
staging (2017-05-05 17:07:55 +0100)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.10-201
From: Nikunj A Dadhania
Emulating LL/SC with cmpxchg is not correct, since it can suffer from
the ABA problem. However, portable parallel code is written assuming
only cmpxchg which means that in practice this is a viable alternative.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Hender
From: Nikunj A Dadhania
This enables the multi-threaded system emulation by default for PPC64
guests using the x86_64 TCG back-end.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Alex Bennée
Signed-off-by: David Gibson
---
configure| 2 ++
target/ppc/cpu.h | 2 ++
2 files changed, 4 i
From: Suraj Jitindar Singh
Now that we have added all the infrastructure we can enable a pseries TCG
guest to use radix.
In order to do this we have to add the appropriate bits to the
ibm,arch-vec-5-platform-support vector to represent that we support both
hash and radix mmu models.
A radix gue
From: Suraj Jitindar Singh
The Guest Translation Shootdown Enable (GTSE) bit in the Logical Partition
Control Register (LPCR) can be set to enable a guest to use the tlbie
instruction directly to invalidate translations.
When the GTSE bit is set then the tlbie instruction is supervisor
privilege
From: Sam Bobroff
Kernel commit 17d48610ae0f ("KVM: PPC: Book 3S: XICS: Implement ICS
P/Q states") added new bits to the state used by KVM IRQs. Currently,
QEMU does not preserve these bits, so migrating (or otherwise saving
and restoring) the guest state causes the P and Q bits to be cleared.
C
From: Cédric Le Goater
Today, when a PowerNV guest runs, it uses the sensor definitions of
the BMC simulator to populate the device tree. But an external IPMI
BMC could also be used and, in that case, it is not (yet) possible to
retrieve the sensor list. Generating the OEM SEL event for shutdown
From: Nikunj A Dadhania
In case when atomic operation is not supported, exit_atomic is called
and we stop the world and execute the atomic operation. This results
in a following call chain:
tcg_gen_atomic_cmpxchg_tl()
-> gen_helper_exit_atomic()
-> HELPER(exit_atomic)
-> cpu_loop_
From: Mark Cave-Ayland
The QemuMacDrivers project provides virtualisation drivers for PPC MacOS
guests.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
.gitmodules | 3 +++
pc-bios/README | 3 +++
roms/QemuMacDrivers | 1 +
3 files changed, 7 insertions(+)
create
On 2017-05-09 14:13, Richard Henderson wrote:
> On 05/06/2017 04:14 AM, Aurelien Jarno wrote:
> > +void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> > +MMUAccessType access_type,
> > +int mmu_idx, uintptr_t retadd
This makes some changes to fix build failures on the 'min-glib' docker
image, and maybe other platforms with a buildchain that's less tolerant
about duplicated typedefs.
Signed-off-by: David Gibson
---
include/hw/ppc/pnv.h | 3 +--
include/hw/ppc/pnv_lpc.h | 4 ++--
include/hw/ppc/pnv_occ.h
From: Suraj Jitindar Singh
The tlbie[l] instructions are used to invalidate TLB entries used to cache
address translations.
In ISAv3.00 (POWER9) more fields were added to the tblie[l] instructions
which were previously invalid. We don't care about any of these new fields
since we just invalidate
From: Paolo Bonzini
The PowerPCCPU typedef is included twice if a file includes
both hw/ppc/xics.h and target/ppc/cpu-qom.h.
Signed-off-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
include/hw/ppc/xics.h | 2 +-
1 file changed, 1 insertion(+), 1 deleti
POWER9 DD1 silicon has some bugs which mean it a) isn't really compliant
with the ISA v3.00 and b) require a number of special workarounds in the
kernel.
At the moment, qemu isn't aware of DD1. For TCG we don't really want it to
be (why bother emulating buggy silicon). But with KVM, the guest do
From: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
Makefile | 3 ++-
pc-bios/qemu_vga.ndrv | Bin 0 -> 14752 bytes
2 files changed, 2 insertions(+), 1 deletion(-)
create mode 100644 pc-bios/qemu_vga.ndrv
diff --git a/Makefile b/Makefile
inde
From: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
hw/ppc/mac_newworld.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 68aaedc..bae1c0a 100644
--- a/hw/ppc/mac_newwo
From: Suraj Jitindar Singh
The UPRT and GTSE bits are set when a guest calls H_REGISTER_PROCESS_TABLE
to choose determine how address translation is performed. Currently these
bits in the LPCR are only set for the cpu which handles the H_CALL, however
they need to be set for all cpus for that gue
On Mon, May 08, 2017 at 03:32:17PM +0800, Peter Xu wrote:
> On Mon, May 08, 2017 at 04:07:44PM +1000, David Gibson wrote:
> > On Mon, May 08, 2017 at 01:48:14PM +0800, Peter Xu wrote:
> > > On Mon, May 01, 2017 at 02:58:22PM +1000, David Gibson wrote:
> > > > On Thu, Apr 27, 2017 at 05:34:18PM +080
From: Suraj Jitindar Singh
ISA V3.00 introduced a new radix mmu model. Implement the page fault
handler for this so we can run a tcg guest in radix mode and perform
address translation correctly.
In real mode (mmu turned off) addresses are masked to remove the top
4 bits and then are subject to
Logic in spapr_populate_pa_features() enables the bit advertising
Hardware Transactional Memory (HTM) in the guest's device tree only when
KVM advertises its availability with the KVM_CAP_PPC_HTM feature.
However, this assumes that the HTM bit is off in the base template used for
the device tree v
On Wed, May 10, 2017 at 06:19:32AM +0200, Thomas Huth wrote:
> When running with KVM, we update the "family" CPU alias to point
> to the right host CPU type, so that it for example possible to
> use "-cpu POWER8" on a POWER8NVL host. However, the function for
> printing the list of available CPU mo
It is the same as previous pull request (from 2017-05-07),
but with author of single patch fixed. I've no idea how
it happened, I don't touch patches manually, only add
S-o-b and R-o-b using commit --amend. Either way, it
is fixed now. Not resending everything, only the fixed
patch.
/mjt
The fo
From: "sochin.jiang"
Signed-off-by: sochin.jiang
Reviewed-by: Marc-André Lureau
Signed-off-by: Michael Tokarev
---
include/io/channel-file.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/io/channel-file.h b/include/io/channel-file.h
index d2462c2ed7..79245f1183 1
On Mon, May 08, 2017 at 09:32:42AM -0500, Eric Blake wrote:
> On 05/08/2017 12:26 AM, David Gibson wrote:
> > On Fri, May 05, 2017 at 02:38:08PM -0500, Eric Blake wrote:
> >> Time to wire up all the call sites that request a shutdown or
> >> reset to use the enum added in the previous patch.
> >>
>
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20170510070115.13063-1-da...@gibson.dropbear.id.au
Type: series
Subject: [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total
On Tue, May 09, 2017 at 09:31:12PM +0200, Laurent Vivier wrote:
> When the VM is used behind a firewall, This allows
> the use of a SOCKS5 proxy server to connect the VM IP stack
> directly to the Internet.
>
> This implementation doesn't manage UDP packets, so they
> are simply dropped (as with r
CC: "Michael S. Tsirkin"
CC: Paolo Bonzini
CC: Richard Henderson
CC: Eduardo Habkost
Reviewed-by: Eduardo Habkost
Signed-off-by: Peter Xu
---
hw/i386/pc_piix.c| 15 ---
hw/i386/pc_q35.c | 13 +++--
include/hw/i386/pc.h | 3 +++
3 files changed, 26 insertions(+),
v3:
- add one patch to provide machine type 2.10 for pc, add r-b for Edurado
- add r-b/a-b for David on the two memory patches
- add a-b for Paolo on the two memory patches
- remove useless if in vtd_switch_address_space() [Jason]
- check pt_supported when needed [Yi]
- one more patch to check whet
This patch converts the old "is_write" bool into IOMMUAccessFlags. The
difference is that "is_write" can only express either read/write, but
sometimes what we really want is "none" here (neither read nor write).
Replay is an good example - during replay, we should not check any RW
permission bits s
Helper to fetch VT-d context entry type.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 4628f04..c8751ba 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
We were always passing in that one as "false" to assume that's an read
operation, and we also assume that IOMMU translation would always have
that read permission. A better permission would be IOMMU_NONE since the
replay is after all not a real read operation, but just a page table
rebuilding proce
This function has an assumption that we will definitely call translate()
once (or say, the addr will be located inside one IOMMU memory region),
otherwise an empty IOTLB will be returned. Nevertheless, this is not
what we want. When there is no IOMMU memory region, we should build up a
static mappi
We have that now, so why not use it.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c8751ba..05ae631 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1010,
The old names are too long and less ordered. Let's start to use
vtd_ce_*() as a pattern.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index ea54ec3..4
This patch pre-heat vhost iotlb cache when passthrough mode enabled.
Sometimes, even if user specified iommu_platform for vhost devices,
IOMMU might still be disabled. One case is passthrough mode in VT-d
implementation. We can detect this by observing iommu_list. If it's
empty, it means IOMMU tra
No reason to keep tens of lines if we can do it actually far shorter.
Signed-off-by: Peter Xu
---
hw/i386/x86-iommu.c | 47 +++
1 file changed, 7 insertions(+), 40 deletions(-)
diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c
index 23dcd3f..02b8
When device-iotlb is not specified, we should fail this check.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 05ae631..1a7eba2 100644
--- a/hw/i386/intel_iommu
This is for compatibility.
Signed-off-by: Peter Xu
---
include/hw/compat.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/compat.h b/include/hw/compat.h
index 846b90e..ff08ec8 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -2,7 +2,11 @@
#defin
Hardware support for VT-d device passthrough. Although current Linux can
live with iommu=pt even without this, but this is faster than when using
software passthrough.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 210 -
hw/i386/intel_iommu_
From: Xiao Guangrong
Currently, the timer is updated whenever RegA or RegB is written
even if the periodic timer related configuration is not changed
This patch optimizes it slightly to make the update happen only
if its period or enable-status is changed, also later patches are
depend on this o
From: Tai Yunfang
There are two issues in current code:
1) If the period is changed by re-configuring RegA, the coalesced
irq will be scaled to reflect the new period, however, it
calculates the new interrupt number like this:
s->irq_coalesced = (s->irq_coalesced * s->period) / period;
From: Xiao Guangrong
Any tick policy specified on other platforms rather on TARGET_I386
will fall back to LOST_TICK_POLICY_DISCARD silently, this patch makes
sure only TARGET_I386 can enable LOST_TICK_POLICY_SLEW
After that, we can enable LOST_TICK_POLICY_SLEW in the common code
which need not u
From: Xiao Guangrong
If the code purely depends on LOST_TICK_POLICY_SLEW, we can simply
drop '#ifdef TARGET_I386' as only x86 can enable this tick policy
Signed-off-by: Xiao Guangrong
---
hw/timer/mc146818rtc.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git
From: Xiao Guangrong
Changelog in v3:
Thanks to Paolo's the elaborate review comments, this version
simplifies the logic of periodic_timer_update() significantly
that includes:
1) introduce rtc_periodic_clock_ticks() that takes both regA and
regB into account and returns the period clock
2) co
From: Xiao Guangrong
Introduce a function, rtc_policy_slew_deliver_irq(), which delivers
irq if LOST_TICK_POLICY_SLEW is used, as which is only supported on
x86, other platforms call it will trigger a assert
After that, we can move the x86 specific code to the common place
Signed-off-by: Xiao G
This patch factor out the duplicate qmp throttle interface code
that was present in both block and fsdev device files.
Signed-off-by: Pradeep Jagadeesh
---
blockdev.c | 53 +++-
hmp.c | 21 +++-
includ
This patch enables qmp interfaces for the fsdev
devices. This provides two interfaces one
for querying info of all the fsdev devices. The second one
to set the IO limits for the required fsdev device.
Signed-off-by: Pradeep Jagadeesh
---
Makefile| 3 ++
fsdev/qemu-fsdev-dum
This patch factor out the duplicate throttle code that was present in
block and fsdev devices.
Signed-off-by: Pradeep Jagadeesh
---
blockdev.c | 44 +--
fsdev/qemu-fsdev-throttle.c | 43 +-
fsdev/qemu-fsdev-
These patches provide the qmp interface, to query the io throttle
status of the all fsdev devices that are present in a vm.
also, it provides an interface to set the io throttle parameters of a
fsdev to a required value. some of the patches also remove the duplicate
code that was present in block
This patch enables qmp interfaces for the fsdev
devices. This provides two interfaces one
for querying info of all the fsdev devices. The second one
to set the IO limits for the required fsdev device.
Signed-off-by: Pradeep Jagadeesh
Reviewed-by: Greg Kurz
Reviewed-by: Eric Blake
---
qapi/bl
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 1494403315-12760-1-git-send-email-pet...@redhat.com
Type: series
Subject: [Qemu-devel] [PATCH v3 00/12] VT-d: PT (passthrough) mode support and
misc fixes
=== TEST SCRIPT BEGIN ===
#!/bi
On 2017年05月07日 12:39, Wang, Wei W wrote:
On 05/06/2017 04:37 AM, Michael S. Tsirkin wrote:
On Fri, May 05, 2017 at 10:27:13AM +0800, Jason Wang wrote:
On 2017年05月04日 18:58, Wang, Wei W wrote:
Hi,
I want to re-open the discussion left long time ago:
https://lists.gnu.org/archive/html/qemu-d
On Wed, May 10, 2017 at 08:48:53AM +0200, Thomas Huth wrote:
> We don't want to carry along old machine types forever. If we are able to
> remove the pc machines up to 0.13 one day for example, this would allow
> us to eventually kill the code for rombar=0 (i.e. where QEMU copies ROM
> BARs directl
Cc: qemu-sta...@nongnu.org
Signed-off-by: Fam Zheng
---
hw/virtio/virtio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 03592c5..a7741f4 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -2515,6 +2515,7 @@ static void virtio_device_un
If we experience large delays between echi timer callbacks (i.e. because
other periodic handlers have taken a lot of time to complete) we get a lot of
skipped frames which then delay ehci timer callback.
Then we will calculation ehci->last_run_ns,but skipped_uframes is int,so
"UFRAME_TIMER_N
This reverts commit dc0ae767700c156894e36fab89a745a2dc4173de.
Disabling the shpc controller has an undesired side effect.
The PCI bridge remains with no attached devices at boot time,
and the guest operating systems do not all allocate any resources
for it leaving the bridge unusable. Note that th
On Wed, 05/10 17:23, Fam Zheng wrote:
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Fam Zheng
> ---
> hw/virtio/virtio.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> index 03592c5..a7741f4 100644
> --- a/hw/virtio/virtio.c
> +++ b/hw/virtio/v
Hi Subbaraya, nice work!
The timer you are modeling is the mss_timer, which is in particular used
in the smartfusion2, I'd rather name it mss_timer.c so it can be reused
by other SoC models.
I added few comments.
On 05/09/2017 01:44 PM, Subbaraya Sundeep wrote:
Modelled System Timer in Micr
Hi Subbaraya,
This is your v4 of this patch set, please don't forget to include the
version in your next set.
Please also include changes between versions in your cover letter, it
eases the review.
On 05/09/2017 01:44 PM, Subbaraya Sundeep wrote:
Hi Qemu-devel,
I am trying to add Smartfus
On 05/07/2017 12:39 PM, Wang, Wei W wrote:
On 05/06/2017 04:37 AM, Michael S. Tsirkin wrote:
On Fri, May 05, 2017 at 10:27:13AM +0800, Jason Wang wrote:
On 2017年05月04日 18:58, Wang, Wei W wrote:
Hi,
I want to re-open the discussion left long time ago:
https://lists.gnu.org/archive/html/qemu-d
[Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510
>
> === TEST SCRIPT BEGIN ===
> #!/bin/bash
>
> BASE=base
> n=1
> total=$(git log --oneline $BASE.. | wc -l)
> failed=0
>
> git config --local diff.renamelimit 0
> git config --local diff.renames True
>
>
Fam Zheng writes:
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Fam Zheng
> ---
> hw/virtio/virtio.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> index 03592c5..a7741f4 100644
> --- a/hw/virtio/virtio.c
> +++ b/hw/virtio/virtio.c
> @@ -2515,
On 10/05/2017 10:32, guangrong.x...@gmail.com wrote:
> From: Xiao Guangrong
>
> Changelog in v3:
> Thanks to Paolo's the elaborate review comments, this version
> simplifies the logic of periodic_timer_update() significantly
> that includes:
> 1) introduce rtc_periodic_clock_ticks() that takes
On Wed, Apr 26, 2017 at 12:04:11AM +0200, Juan Quintela wrote:
> This allows us to remove lots of includes of migration/migration.h
>
> Signed-off-by: Juan Quintela
If without all the "xbzrle.h" changes:
Reviewed-by: Peter Xu
--
Peter Xu
On 05/10/2017 05:00 PM, Jason Wang wrote:
On 2017年05月07日 12:39, Wang, Wei W wrote:
On 05/06/2017 04:37 AM, Michael S. Tsirkin wrote:
On Fri, May 05, 2017 at 10:27:13AM +0800, Jason Wang wrote:
On 2017年05月04日 18:58, Wang, Wei W wrote:
Hi,
I want to re-open the discussion left long time ago
On Wed, 05/10 11:51, Markus Armbruster wrote:
> Fam Zheng writes:
>
> > Cc: qemu-sta...@nongnu.org
> > Signed-off-by: Fam Zheng
> > ---
> > hw/virtio/virtio.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
> > index 03592c5..a7741f4 100644
* Peter Xu (pet...@redhat.com) wrote:
> To dump information about ramblocks. It looks like:
>
> (qemu) info ramblock
> Block NamePSize Offset Used
> Total
> /objects/mem2 MiB 0x 0x8000
> 0x
On 10.05.2017 11:08, Daniel P. Berrange wrote:
> On Wed, May 10, 2017 at 08:48:53AM +0200, Thomas Huth wrote:
>> We don't want to carry along old machine types forever. If we are able to
>> remove the pc machines up to 0.13 one day for example, this would allow
>> us to eventually kill the code for
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20170510083259.3900-1-xiaoguangr...@tencent.com
Type: series
Subject: [Qemu-devel] [PATCH v3 0/5] mc146818rtc: fix Windows VM clock faster
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
> -Original Message-
> From: Eric Blake [mailto:ebl...@redhat.com]
> Sent: Tuesday, May 09, 2017 12:20 AM
> To: qemu-devel@nongnu.org
> Cc: arm...@redhat.com; berra...@redhat.com; alistair.fran...@xilinx.com;
> Pavel Dovgalyuk;
> Paolo Bonzini
> Subject: [PATCH v7 4/5] shutdown: Preserve
* Peter Xu (pet...@redhat.com) wrote:
> Moving the algorithm from print_type_size() into size_to_str() so that
> other component can also leverage it. With that, refactor
> print_type_size().
>
> Signed-off-by: Peter Xu
> ---
> include/qemu-common.h| 1 +
> qapi/string-output-visitor.c
On 2017-05-09 11:07, Richard Henderson wrote:
> From: Eric Bischoff
>
> Reviewed-by: Aurelien Jarno
> Signed-off-by: Eric Bischoff
> Message-Id: <20170228120134.7921-1-ebisch...@suse.com>
> [rth: Combine the two via insn->data; free the address temps.]
> Signed-off-by: Richard Henderson
> ---
* Halil Pasic (pa...@linux.vnet.ibm.com) wrote:
>
>
> On 05/08/2017 06:55 PM, Dr. David Alan Gilbert wrote:
> > * Halil Pasic (pa...@linux.vnet.ibm.com) wrote:
> >> Let us use the freshly introduced vmstate migration helpers instead of
> >> saving/loading the config manually.
> >>
> >> To achieve
On Wed, May 10, 2017 at 12:05:16PM +0200, Thomas Huth wrote:
> On 10.05.2017 11:08, Daniel P. Berrange wrote:
> > On Wed, May 10, 2017 at 08:48:53AM +0200, Thomas Huth wrote:
> >> We don't want to carry along old machine types forever. If we are able to
> >> remove the pc machines up to 0.13 one da
Hi Subbaraya,
On 05/09/2017 01:44 PM, Subbaraya Sundeep wrote:
Added Sytem register block of Smartfusion2.
This block has PLL registers which are accessed by guest.
Signed-off-by: Subbaraya Sundeep
---
hw/misc/Makefile.objs | 1 +
hw/misc/msf2-sysreg.c | 131
On Tue, 9 May 2017 19:05:28 +0200
Halil Pasic wrote:
> From e92135590ab95cc565b37913de77a9ed17012933 Mon Sep 17 00:00:00 2001
> From: Halil Pasic
> Date: Tue, 9 May 2017 16:01:50 +0200
> Subject: [PATCH 1/2] virtio-ccw: replace info with VMSTATE_WITH_TMP
>
> Convert s VMSatateInfo based solutio
On 05/09/2017 03:07 PM, Richard Henderson wrote:
All of the interlocked access facility instructions raise a
specification exception for unaligned accesses. Do this by
using the (previously unused) unaligned_access hook.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
Reviewed-
On 05/09/2017 03:00 AM, Peter Xu wrote:
Meanwhile, abstract a function to detect msix masked bit.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/msix.c | 11 +--
hw/pci/trace-events | 3 +++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --g
On 05/09/2017 03:00 AM, Peter Xu wrote:
It'll be nice to know which virq belongs to which device/vector when
adding msi routes, so adding two more parameters for the add trace.
Meanwhile, releasing virq has no tracing before. Add one for it.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Math
On 05/08/2017 05:57 PM, Eduardo Habkost wrote:
There's no reason to keep the soundhw table in arch_init.c. Move
that code to a new hw/audio/soundhw.c file.
While moving the code, trivial coding style issues were fixed.
Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
---
On 05/09/2017 05:27 AM, Aurelien Jarno wrote:
For that move the definition from kvm.c to cpu.h
Signed-off-by: Aurelien Jarno
Reviewed-by: Philippe Mathieu-Daudé
---
target/s390x/cpu.h | 3 +++
target/s390x/kvm.c | 2 --
target/s390x/misc_helper.c | 3 +--
3 files changed,
On 05/09/2017 06:09 PM, Richard Henderson wrote:
On 05/06/2017 04:14 AM, Aurelien Jarno wrote:
+tcg_gen_extrl_i64_i32(cpu_fregs[reg + 1], t);
+tcg_gen_extrh_i64_i32(cpu_fregs[reg], t);
This is
tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);
nicer :)
Otherwise,
Rev
Hi,
Any findings on this case? Is there any chance PetaLinux 2017.1 addressed this
issue?
Thank you,
Constantin
On Friday, April 21, 2017 at 10:23:07 PM UTC+3, Edgar E. Iglesias wrote:
> On Fri, Apr 21, 2017 at 10:04:56AM +0300, Constantin Petra wrote:
> > OK,
> >
> > Changed configs for inma
From: Prasad J Pandit
When processing completed commands, if SCSIRequest object
'cmd->req' was null, it could lead to null pointer dereference
in megasas_complete_command. Add check to avoid it.
Reported-by: Zhangyanyu
Signed-off-by: Prasad J Pandit
---
hw/scsi/megasas.c | 8 +---
1 file
The deprecation of features in QEMU is totally adhoc currently,
with no way for the user to get a list of what is deprecated
in each release. There is also no guidance on the duration of
support for features such as versioned machine types, which
have a finite useful life.
This adds two new append
Hi Subbaraya,
On 05/09/2017 01:44 PM, Subbaraya Sundeep wrote:
Emulated Emcraft's Smartfusion2 System On Module starter
kit.
Signed-off-by: Subbaraya Sundeep
---
hw/arm/Makefile.objs | 1 +
hw/arm/msf2-som.c| 67
2 files changed, 68 in
Changes since v2:
* rebased on top of numa-next tree
* add comment to spapr_cpu_index_to_props() explaining why
cpu_index can't used as index in possible_cpus[] (Eduardo)
* remove obsolete comment in parse_numa_opts() (Eduardo)
* add to commit message of "pc: add node-id property t
it will allow switching from cpu_index to core based numa
mapping in follow up patches.
Signed-off-by: Igor Mammedov
Reviewed-by: David Gibson
---
include/hw/ppc/spapr_cpu_core.h | 1 +
include/qom/cpu.h | 2 ++
hw/ppc/spapr.c | 17 +
hw/ppc/spap
Default node mapping initialization already checks that board
supports cpu_index to node mapping and refuses to start if
it's not supported. Do the same for explicitly provided
mapping "-numa node,cpus=..."
Signed-off-by: Igor Mammedov
Reviewed-by: Andrew Jones
Reviewed-by: David Gibson
---
v3:
Introduce machine_set_cpu_numa_node() helper that stores
node mapping for CPU in MachineState::possible_cpus.
CPU and node it belongs to is specified by 'props' argument.
Patch doesn't remove old way of storing mapping in
numa_info[X].node_cpu as removing it at the same time
makes patch rather big
it will allow switching from cpu_index to property based
numa mapping in follow up patches.
PS:
patch changes default value of CPUState::numa_node from 0
to CPU_UNSET_NUMA_NODE_ID. The only place for x86 that
would affected is monitor's 'infor numa' command which
uses that field. However legacy 0
Signed-off-by: Igor Mammedov
Reviewed-by: David Gibson
Reviewed-by: Andrew Jones
---
numa.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/numa.c b/numa.c
index 7db5dde..c89fc2d 100644
--- a/numa.c
+++ b/numa.c
@@ -458,6 +458,7 @@ void numa_default_aut
Signed-off-by: Igor Mammedov
Reviewed-by: Andrew Jones
---
v3:
drop numa_[has_]node_id() wrappers (ehabkost, dwg)
v2:
use numa_[has_]node_id() wrappers (Drew)
---
hw/acpi/cpu.c| 7 +++
hw/i386/acpi-build.c | 11 ---
hw/i386/pc.c | 18 ++
3 files
CPUState::numa_node is still in use but now it's set by
board when it creates CPU objects. So there isn't any
need to set it again after all CPU's are created,
since it's been already set.
Signed-off-by: Igor Mammedov
Reviewed-by: David Gibson
Reviewed-by: Andrew Jones
---
include/sysemu/numa.
Originally CPU threads were by default assigned in
round-robin fashion. However it was causing issues in
guest since CPU threads from the same socket/core could
be placed on different NUMA nodes.
Commit fb43b73b (pc: fix default VCPU to NUMA node mapping)
fixed it by grouping threads within a socke
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