When rounding a floating point result to float64 precision, the
existing code doesn't re-calculate the required round increment
for the underflow case. Fix this.
Signed-off-by: Bharata B Rao
---
fpu/softfloat.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/fpu/softfloat.
Hi,
Here is the next version of round-to-odd rounding mode implementation.
In this version I have addressed the reveiw comments from v1 and added
a new patch to take care of 64 bit rounding in underflow case. This
fix was found necessary when comparing the result of PowerPC ISA 3.0
instruction xs
Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:
Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exactly in the target form
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [RFC PATCH v2 0/2] softfloat: Add round-to-odd rounding
mode
Message-id: 1485504213-21632-1-git-send-email-bhar...@linux.vnet.ibm.com
=== TEST SCRIPT BEGIN ===
#!/
On Fri, Jan 27, 2017 at 12:09:13AM -0800, no-re...@patchew.org wrote:
> Hi,
>
> Your series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Subject: [Qemu-devel] [RFC PATCH v2 0/2] softfloat: Add round-to-odd rounding
> mode
> Message-id: 148
Fixes the booting of ss20 roms.
Reported-by: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 655060c..aa6734d
> This is a port to ppc of the i386 commit:
> 00f4d64 kvmclock: clock should count only if vm is running
>
> We remove timebase_/pre_save/post_load/ functions,
> and use the VM state change handler to save and restore
> the guest_timebase (on stop and continue).
>
> Time base offset has orig
On 26/01/17 22:21, Peter Maydell wrote:
> On 26 January 2017 at 20:47, Peter Maydell wrote:
>> On 26 January 2017 at 19:36, Stefano Stabellini
>> wrote:
>>> It should be just a matter of replacing qdev_init_nofail with something
>>> that can fail. I couldn't find a regular qdev_init that can ret
On 27/01/2017 09:52, Paolo Bonzini wrote:
>
>> This is a port to ppc of the i386 commit:
>> 00f4d64 kvmclock: clock should count only if vm is running
>>
>> We remove timebase_/pre_save/post_load/ functions,
>> and use the VM state change handler to save and restore
>> the guest_timebase (on s
On Tue, Jan 24, 2017 at 05:02:25PM -0500, Brian Rak wrote:
> We've been considering switching over to using qemu's built in websockets
> support (to avoid the overhead of needing websockify running). We've been
> seeing very poor performance after the switch (it takes the console 4-5
> seconds to
On Thu, Jan 26, 2017 at 02:46:52PM +0530, Ashijeet Acharya wrote:
> Migration of a "none" machine with no RAM crashes abruptly as
> bitmap_new() fails and thus aborts. Instead, place a check for
> last_ram_offset() being '0' at the start of ram_save_setup() and
> error out with a meaningful error m
Marc-André Lureau writes:
> Add type information to the generated documentation. Without it the
> written documentation is not explicit enough to know how to handle
> the various arguments and members.
This is actually a regression of sorts: the type information we used to
have in qmp-commands.t
On Thu, Jan 26, 2017 at 05:07:16PM -0800, Ed Swierk wrote:
> Interactive access to a guest serial console can be enabled by hooking
> the serial device to a pty backend, e.g. -device
> isa-serial,chardev=cs0 -chardev pty,id=cs0. With libvirt this can be
> configured via port='0'/>.
>
> Output fro
The QEMU manual page states that Cirrus Logic is the default video
card if the user doesn't specify any. However this is not true since
QEMU 2.2.
Signed-off-by: Alberto Garcia
---
qemu-options.hx | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qemu-options.hx b/qemu-optio
On 26.01.2017 21:45, Laurent Vivier wrote:
> This is a port to ppc of the i386 commit:
> 00f4d64 kvmclock: clock should count only if vm is running
>
> We remove timebase_/pre_save/post_load/ functions,
> and use the VM state change handler to save and restore
> the guest_timebase (on stop and
* Daniel P. Berrange (berra...@redhat.com) wrote:
> On Thu, Jan 26, 2017 at 02:46:52PM +0530, Ashijeet Acharya wrote:
> > Migration of a "none" machine with no RAM crashes abruptly as
> > bitmap_new() fails and thus aborts. Instead, place a check for
> > last_ram_offset() being '0' at the start of
Okay
On Friday, 27 January 2017, Daniel P. Berrange wrote:
> On Thu, Jan 26, 2017 at 02:46:52PM +0530, Ashijeet Acharya wrote:
> > Migration of a "none" machine with no RAM crashes abruptly as
> > bitmap_new() fails and thus aborts. Instead, place a check for
> > last_ram_offset() being '0' at t
On Fri, Jan 27, 2017 at 09:46:13AM +, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrange (berra...@redhat.com) wrote:
> > On Thu, Jan 26, 2017 at 02:46:52PM +0530, Ashijeet Acharya wrote:
> > > Migration of a "none" machine with no RAM crashes abruptly as
> > > bitmap_new() fails and thus abo
On Fri, Jan 27, 2017 at 03:22:38PM +0530, Ashijeet Acharya wrote:
> Okay
>
> On Friday, 27 January 2017, Daniel P. Berrange wrote:
>
> > On Thu, Jan 26, 2017 at 02:46:52PM +0530, Ashijeet Acharya wrote:
> > > Migration of a "none" machine with no RAM crashes abruptly as
> > > bitmap_new() fails
The "qemu/queue.h" data structures provide static initializer macros.
The QLIST version just initializes to NULL so code happens to work when
the initializer is forgotten. Other types like SLIST are not so
forgiving because they set fields to non-NULL values.
The initializer macro should always b
Code added in commit 6349c15410361d3fe52c9beee309954d606f8ccd ("block/gluster:
memory usage: use one glfs instance per volume") does not follow conventions
and violates QEMU coding style. Although any single issue in isolation is not
worth patching, there are several of these and I think it's wort
The "qemu/queue.h" data structures are used without intermediate list
node structs. They are designed to be embedded in the main struct.
Drop the unnecessary ListElement struct.
Signed-off-by: Stefan Hajnoczi
---
block/gluster.c | 39 +--
1 file changed, 17 i
QEMU uses 4-space indentation. Fix this now so checkpatch.pl is happy
with future code changes.
Signed-off-by: Stefan Hajnoczi
---
block/gluster.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/block/gluster.c b/block/gluster.c
index 1a22f29..516a1e1 100644
--- a/block/
The naming of GlfsPreopened functions is a little unusual:
glfs_set_preopened() appends items to the list. Normally this operation
is called "add".
glfs_find_preopened() is paired with glfs_clear_preopened(). Normally
this is called "get" and "put" (or "ref" and "unref").
This patch renames th
On 27 January 2017 at 06:51, Markus Armbruster wrote:
> "What can we cut" is the wrong question. The right one is "what are our
> requirements". Here's my try:
>
> HTML: required
> nroff with an macros: required
> PDF: wanted (try printing a website)
> plain text: nice to have (for me personally
IOThread AioContexts are likely to consist only of event sources like
virtqueue ioeventfds and LinuxAIO completion eventfds that are pollable
from userspace (without system calls).
We recently merged the AioContext polling feature but didn't enable it
by default yet. I have gone back over the per
>> Slightly off-topic, but: Is fulong2e still maintained? I did not spot an
>> entry in MAINTAINERS...?
>
> It's covered by the general MIPS stanza:
>
> $ scripts/get_maintainer.pl -f hw/mips/mips_fulong2e.c
> Aurelien Jarno (maintainer:MIPS)
> Yongbok Kim (maintainer:MIPS)
>
On 27.01.2017 11:21, Yongbok Kim wrote:
>
>>> Slightly off-topic, but: Is fulong2e still maintained? I did not spot an
>>> entry in MAINTAINERS...?
>>
>> It's covered by the general MIPS stanza:
>>
>> $ scripts/get_maintainer.pl -f hw/mips/mips_fulong2e.c
>> Aurelien Jarno (maintainer:MI
From: Pranith Kumar
The recent patch enabling lock assertions uncovered the missing lock
acquisition in cpu_exec_step(). This patch adds them.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
---
cpu-exec.c | 4
1 file changed, 4 insertions(+)
diff --git a/cpu-exec.c
From: Pranith Kumar
Enable tcg lock debug asserts in a debug build by default instead of
relying on DEBUG_LOCKING. None of the other DEBUG_* macros have
asserts, so this patch removes DEBUG_LOCKING and enable these asserts
in a debug build.
CC: Richard Henderson
Signed-off-by: Pranith Kumar
[A
Currently we rely on the side effect of the main loop grabbing the
iothread_mutex to give any long running basic block chains a kick to
ensure the next vCPU is scheduled. As this code is being re-factored and
rationalised we now do it explicitly here.
Signed-off-by: Alex Bennée
Reviewed-by: Richa
From: Jan Kiszka
This finally allows TCG to benefit from the iothread introduction: Drop
the global mutex while running pure TCG CPU code. Reacquire the lock
when entering MMIO or PIO emulation, or when leaving the TCG loop.
We have to revert a few optimization for the current TCG threading
mode
We'll be using the memory ordering definitions to define values for
both the host and guest. To avoid fighting with circular header
dependencies just move these types into their own minimal header.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
tcg/tcg-mo.h | 45 +
From: KONRAD Frederic
We know there will be cases where MTTCG won't work until additional work
is done in the front/back ends to support. It will however be useful to
be able to turn it on.
As a result MTTCG will default to off unless the combination is
supported. However the user can turn it on
This documents the current design for upgrading TCG emulation to take
advantage of modern CPUs by running a thread-per-CPU. The document goes
through the various areas of the code affected by such a change and
proposes design requirements for each part of the solution.
The text marked with (Curren
There are a couple of changes that occur at the same time here:
- introduce a single vCPU qemu_tcg_cpu_thread_fn
One of these is spawned per vCPU with its own Thread and Condition
variables. qemu_tcg_rr_cpu_thread_fn is the new name for the old
single threaded function.
- the TLS curre
From: Pranith Kumar
The patch enables handling atomic code in the guest. This should be
preferably done in cpu_handle_exception(), but the current assumptions
regarding when we can execute atomic sections cause a deadlock.
Signed-off-by: Pranith Kumar
[AJB: tweak title]
Signed-off-by: Alex Benn
From: KONRAD Frederic
Some architectures allow to flush the tlb of other VCPUs. This is not a problem
when we have only one thread for all VCPUs but it definitely needs to be an
asynchronous work when we are in true multithreaded work.
We take the tb_lock() when doing this to avoid racing with o
..and make the definition local to cpus. In preparation for MTTCG the
concept of a global tcg_current_cpu will no longer make sense. However
we still need to keep track of it in the single-threaded case to be able
to exit quickly when required.
qemu_cpu_kick_no_halt() moves and becomes qemu_cpu_ki
When switching a new vCPU on we want to complete a bunch of the setup
work before we start scheduling the vCPU thread. To do this cleanly we
defer vCPU setup to async work which will run the vCPUs execution
context as the thread is woken up. The scheduling of the work will kick
the vCPU awake.
Thi
tb_lock() has long been used for linux-user mode to protect code
generation. By enabling it now we prepare for MTTCG and ensure all code
generation is serialised by this lock. The other major structure that
needs protecting is the l1_map and its PageDesc structures. For the
SoftMMU case we also use
We'll be using the memory ordering definitions to define values for
both the host and guest. To avoid fighting with circular header
dependencies just move these types into their own minimal header.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
tcg/tcg-mo.h | 45 +
This introduces support to the cputlb API for flushing all CPUs TLBs
with one call. This avoids the need for target helpers to iterate
through the vCPUs themselves.
An additional variant of the API (_synced) do not return from the
caller and will cause the work to be scheduled as "safe work". The
There are now only two uses of the global exit_request left.
The first ensures we exit the run_loop when we first start to process
pending work and in the kick handler. This is just as easily done by
setting the first_cpu->exit_request flag.
The second use is in the round robin kick routine. The
From: Pranith Kumar
The recent patch enabling lock assertions uncovered the missing lock
acquisition in cpu_exec_step(). This patch adds them.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
---
cpu-exec.c | 4
1 file changed, 4 insertions(+)
diff --git a/cpu-exec.c
Hi,
All of the changes in this revision are addressing comments from v7
posted last week. A new pre-cursor patch was added:
cputlb and arm/sparc targets: convert mmuidx flushes from varg to
bitmap
To change the cputlb API to use a bitmap instead of vargs. This has
generated quite a bit of
From: Pranith Kumar
Enable tcg lock debug asserts in a debug build by default instead of
relying on DEBUG_LOCKING. None of the other DEBUG_* macros have
asserts, so this patch removes DEBUG_LOCKING and enable these asserts
in a debug build.
CC: Richard Henderson
Signed-off-by: Pranith Kumar
[A
This moves the helper function closer to where it is called and updates
the error message to report via error_report instead of the deprecated
fprintf.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
cputlb.c | 24
1 file changed, 12 insertions(+), 12 dele
tb_lock() has long been used for linux-user mode to protect code
generation. By enabling it now we prepare for MTTCG and ensure all code
generation is serialised by this lock. The other major structure that
needs protecting is the l1_map and its PageDesc structures. For the
SoftMMU case we also use
Currently we rely on the side effect of the main loop grabbing the
iothread_mutex to give any long running basic block chains a kick to
ensure the next vCPU is scheduled. As this code is being re-factored and
rationalised we now do it explicitly here.
Signed-off-by: Alex Bennée
Reviewed-by: Richa
This documents the current design for upgrading TCG emulation to take
advantage of modern CPUs by running a thread-per-CPU. The document goes
through the various areas of the code affected by such a change and
proposes design requirements for each part of the solution.
The text marked with (Curren
There are now only two uses of the global exit_request left.
The first ensures we exit the run_loop when we first start to process
pending work and in the kick handler. This is just as easily done by
setting the first_cpu->exit_request flag.
The second use is in the round robin kick routine. The
From: KONRAD Frederic
We know there will be cases where MTTCG won't work until additional work
is done in the front/back ends to support. It will however be useful to
be able to turn it on.
As a result MTTCG will default to off unless the combination is
supported. However the user can turn it on
..and make the definition local to cpus. In preparation for MTTCG the
concept of a global tcg_current_cpu will no longer make sense. However
we still need to keep track of it in the single-threaded case to be able
to exit quickly when required.
qemu_cpu_kick_no_halt() moves and becomes qemu_cpu_ki
For SoftMMU the TLB flushes are an example of a task that can be
triggered on one vCPU by another. To deal with this properly we need to
use safe work to ensure these changes are done safely. The new assert
can be enabled while debugging to catch these cases.
Signed-off-by: Alex Bennée
Reviewed-b
This is a purely mechanical change to make the ARM_CP flags neatly
align and use a consistent format so it is easier to see which bit
each flag is.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/t
From: KONRAD Frederic
Some architectures allow to flush the tlb of other VCPUs. This is not a problem
when we have only one thread for all VCPUs but it definitely needs to be an
asynchronous work when we are in true multithreaded work.
We take the tb_lock() when doing this to avoid racing with o
From: Jan Kiszka
This finally allows TCG to benefit from the iothread introduction: Drop
the global mutex while running pure TCG CPU code. Reacquire the lock
when entering MMIO or PIO emulation, or when leaving the TCG loop.
We have to revert a few optimization for the current TCG threading
mode
This moves the helper function closer to where it is called and updates
the error message to report via error_report instead of the deprecated
fprintf.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
cputlb.c | 24
1 file changed, 12 insertions(+), 12 dele
For SoftMMU the TLB flushes are an example of a task that can be
triggered on one vCPU by another. To deal with this properly we need to
use safe work to ensure these changes are done safely. The new assert
can be enabled while debugging to catch these cases.
Signed-off-by: Alex Bennée
Reviewed-b
From: Pranith Kumar
The patch enables handling atomic code in the guest. This should be
preferably done in cpu_handle_exception(), but the current assumptions
regarding when we can execute atomic sections cause a deadlock.
Signed-off-by: Pranith Kumar
[AJB: tweak title]
Signed-off-by: Alex Benn
While the vargs approach was flexible the original MTTCG ended up
having munge the bits to a bitmap so the data could be used in
deferred work helpers. Instead of hiding that in cputlb we push the
change to the API to make it take a bitmap of MMU indexes instead.
This change is fairly mechanical b
Some helpers may trigger an immediate exit of the cpu_loop. If this
happens the PC need to be rectified to ensure the restart will begin
on the next instruction.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 3 ++-
target/arm/translate-a64.c | 4
target/arm/translate.c | 4
This enables the multi-threaded system emulation by default for ARMv7
and ARMv8 guests using the x86_64 TCG backend. This is because on the
guest side:
- The ARM translate.c/translate-64.c have been converted to
- use MTTCG safe atomic primitives
- emit the appropriate barrier ops
- Th
There are a couple of changes that occur at the same time here:
- introduce a single vCPU qemu_tcg_cpu_thread_fn
One of these is spawned per vCPU with its own Thread and Condition
variables. qemu_tcg_rr_cpu_thread_fn is the new name for the old
single threaded function.
- the TLS curre
When switching a new vCPU on we want to complete a bunch of the setup
work before we start scheduling the vCPU thread. To do this cleanly we
defer vCPU setup to async work which will run the vCPUs execution
context as the thread is woken up. The scheduling of the work will kick
the vCPU awake.
Thi
On 01/26/2017 10:09 AM, Markus Armbruster wrote:
> We've traditionally rejected orphans here and there, but not
> systematically. For instance, the sun4m machines have an onboard SCSI
> HBA (bus=0), and have always rejected bus>0. Other machines with an
> onboard SCSI HBA don't.
>
> Commit a66
This is a purely mechanical change to make the ARM_CP flags neatly
align and use a consistent format so it is easier to see which bit
each flag is.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/t
The main use case for tlb_reset_dirty is to set the TLB_NOTDIRTY flags
in TLB entries to force the slow-path on writes. This is used to mark
page ranges containing code which has been translated so it can be
invalidated if written to. To do this safely we need to ensure the TLB
entries in question
Some helpers may trigger an immediate exit of the cpu_loop. If this
happens the PC need to be rectified to ensure the restart will begin
on the next instruction.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 3 ++-
target/arm/translate-a64.c | 4
target/arm/translate.c | 4
The WFE and YIELD instructions are really only hints and in TCG's case
they were useful to move the scheduling on from one vCPU to the next. In
the parallel context (MTTCG) this just causes an unnecessary cpu_exit
and contention of the BQL.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderso
This converts the remaining TLB flush routines to use async work when
detecting a cross-vCPU flush. The only minor complication is having to
serialise the var_list of MMU indexes into a form that can be punted
to an asynchronous job.
The pending_tlb_flush field on QOM's CPU structure also becomes
This enables the multi-threaded system emulation by default for ARMv7
and ARMv8 guests using the x86_64 TCG backend. This is because on the
guest side:
- The ARM translate.c/translate-64.c have been converted to
- use MTTCG safe atomic primitives
- emit the appropriate barrier ops
- Th
The main use case for tlb_reset_dirty is to set the TLB_NOTDIRTY flags
in TLB entries to force the slow-path on writes. This is used to mark
page ranges containing code which has been translated so it can be
invalidated if written to. To do this safely we need to ensure the TLB
entries in question
While the vargs approach was flexible the original MTTCG ended up
having munge the bits to a bitmap so the data could be used in
deferred work helpers. Instead of hiding that in cputlb we push the
change to the API to make it take a bitmap of MMU indexes instead.
This change is fairly mechanical b
This converts the remaining TLB flush routines to use async work when
detecting a cross-vCPU flush. The only minor complication is having to
serialise the var_list of MMU indexes into a form that can be punted
to an asynchronous job.
The pending_tlb_flush field on QOM's CPU structure also becomes
On 27/01/2017 10:31, Thomas Huth wrote:
> On 27.01.2017 11:21, Yongbok Kim wrote:
>>
Slightly off-topic, but: Is fulong2e still maintained? I did not spot an
entry in MAINTAINERS...?
>>>
>>> It's covered by the general MIPS stanza:
>>>
>>> $ scripts/get_maintainer.pl -f hw/mips/mips
The WFE and YIELD instructions are really only hints and in TCG's case
they were useful to move the scheduling on from one vCPU to the next. In
the parallel context (MTTCG) this just causes an unnecessary cpu_exit
and contention of the BQL.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderso
On 27/01/2017 10:45, Thomas Huth wrote:
> On 26.01.2017 21:45, Laurent Vivier wrote:
>> This is a port to ppc of the i386 commit:
>> 00f4d64 kvmclock: clock should count only if vm is running
>>
>> We remove timebase_/pre_save/post_load/ functions,
>> and use the VM state change handler to save
On 27/01/2017 07:09, Pavel Dovgalyuk wrote:
>> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
>> On 26/01/2017 15:32, Pavel Dovgalyuk wrote:
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
On 26/01/2017 14:37, Pavel Dovgalyuk wrote:
>> Simpler:
>>
>> use_icount &&
>>
* Pavel Butsykin (pbutsy...@virtuozzo.com) wrote:
> After the start of postcopy migration there are some non-dirty pages which
> have
> already been migrated. These pages are no longer needed on the source vm so
> that
> we can free them and it doen't hurt to complete the migration.
>
> Signed-o
This introduces support to the cputlb API for flushing all CPUs TLBs
with one call. This avoids the need for target helpers to iterate
through the vCPUs themselves.
An additional variant of the API (_synced) do not return from the
caller and will cause the work to be scheduled as "safe work". The
On 01/26/2017 04:37 AM, Paul Durrant wrote:
> The Xen HVM unplug protocol [1] specifies a mechanism to allow guests to
> request unplug of 'aux' disks (which is stated to mean all IDE disks,
> except the primary master). This patch adds support for that unplug request.
>
> NOTE: The semantics of
* Pavel Butsykin (pbutsy...@virtuozzo.com) wrote:
> This feature frees the migrated memory on the source during postcopy-ram
> migration. In the second step of postcopy-ram migration when the source vm
> is put on pause we can free unnecessary memory. It will allow, in particular,
> to start relaxi
On 24/01/17 17:42, Roger Pau Monné wrote:
> Hello,
>
> The following commit:
>
> commit 3a6c9172ac5951e6dac2b3f6cbce3cfccdec5894
> Author: Juergen Gross
> Date: Tue Nov 22 07:10:58 2016 +0100
>
> xen: create qdev for each backend device
>
> Prevents me from running QEMU on FreeBSD/Xen, the f
John Snow writes:
> On 01/26/2017 10:09 AM, Markus Armbruster wrote:
>> We've traditionally rejected orphans here and there, but not
>> systematically. For instance, the sun4m machines have an onboard SCSI
>> HBA (bus=0), and have always rejected bus>0. Other machines with an
>> onboard SCSI HB
On 26 January 2017 at 02:48, Fam Zheng wrote:
> The following changes since commit c7f1cf01b8245762ca5864e835d84f6677ae8b1f:
>
> Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging
> (2017-01-25 17:54:14 +)
>
> are available in the git repository at:
>
> git://gith
From: Prasad J Pandit
When setting dma channel 'data_type', if (value & 3) == 3,
the set 'data_type' is said to be bad. This also leads to an
OOB access in 'omap_dma_transfer_generic', while doing
cpu_physical_memory_r/w operations. Add check to avoid it.
Reported-by: Jiang Xin
Signed-off-by: P
* Chao Fan (fanc.f...@cn.fujitsu.com) wrote:
> Hi all,
>
> This is a test for this RFC patch.
>
> Start vm as following:
> cmdline="./x86_64-softmmu/qemu-system-x86_64 -m 2560 \
> -drive if=none,file=/nfs/img/fedora.qcow2,format=qcow2,id=foo \
> -netdev tap,id=hn0,queues=1 \
> -device virtio-net-
This is a port to ppc of the i386 commit:
00f4d64 kvmclock: clock should count only if vm is running
We remove timebase_post_load function, and use the VM state
change handler to save and restore the guest_timebase (on stop
and continue).
We keep timebase_pre_save to reduce the clock differen
Peter Maydell writes:
> Add the structure fields, VMState fields, reset code and macros for
> the v7M system control registers CCR, CFSR, HFSR, DFSR, MMFAR and
> BFAR.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/cpu.h | 54
>
>
Peter Maydell writes:
> We only use the IS_M() macro in two places, and it's a bit of a
> namespace grab to put in cpu.h. Drop it in favour of just explicitly
> calling arm_feature() in the places where it was used.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
> ---
> target/a
Peter Maydell writes:
> From: Michael Davidsaver
>
> Many NVIC operations access the CPU state, so store a pointer in
> struct nvic_state rather than fetching it via qemu_get_cpu() every
> time we need it.
>
> As with the arm_gicv3_common code, we currently just call
> qemu_get_cpu() in the NVI
Jitendra Kolhe wrote:
> Using "-mem-prealloc" option for a very large guest leads to huge guest
> start-up and migration time. This is because with "-mem-prealloc" option
> qemu tries to map every guest page (create address translations), and
> make sure the pages are available during runtime. vir
On Fri, Jan 27, 2017 at 9:15 AM, Richard Henderson wrote:
> Fixes the booting of ss20 roms.
Mike, can you please test this fix?
> Reported-by: Mark Cave-Ayland
Initially Reported-by: Michael Russo
> Signed-off-by: Richard Henderson
> ---
> target/sparc/translate.c | 27
* Jitendra Kolhe (jitendra.ko...@hpe.com) wrote:
> Using "-mem-prealloc" option for a very large guest leads to huge guest
> start-up and migration time. This is because with "-mem-prealloc" option
> qemu tries to map every guest page (create address translations), and
> make sure the pages are ava
On Fri, Jan 27, 2017 at 11:34 AM, Alex Bennée wrote:
> While the vargs approach was flexible the original MTTCG ended up
> having munge the bits to a bitmap so the data could be used in
> deferred work helpers. Instead of hiding that in cputlb we push the
> change to the API to make it take a bitm
On 27/01/2017 13:53, Juan Quintela wrote:
>> +static void *do_touch_pages(void *arg)
>> +{
>> +PageRange *range = (PageRange *)arg;
>> +char *start_addr = range->addr;
>> +uint64_t numpages = range->numpages;
>> +uint64_t hpagesize = range->hpagesize;
>> +uint64_t i = 0;
>> +
On 27 January 2017 at 12:28, Alex Bennée wrote:
>
> Peter Maydell writes:
>
>> Add the structure fields, VMState fields, reset code and macros for
>> the v7M system control registers CCR, CFSR, HFSR, DFSR, MMFAR and
>> BFAR.
>>
>> Signed-off-by: Peter Maydell
>> ---
>> target/arm/cpu.h | 54
On 27 January 2017 at 12:41, Alex Bennée wrote:
>> @@ -349,7 +347,6 @@ static void nvic_writel(nvic_state *s, uint32_t offset,
>> uint32_t value)
>> }
>> break;
>> case 0xd08: /* Vector Table Offset. */
>> -cpu = ARM_CPU(qemu_get_cpu(0));
>> cpu->env.v7m.v
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