Public bug reported:
My Specs:
Slackware 14.2 x86_64 > Host
QEMU 2.7.0
Ubuntu 16.04.1 x86_64 > Guest
Start options for Ubuntu:
qemu-system-x86_64 -drive format=raw,file=ubuntu.img \
-cpu host \
--enable-kvm \
-smp 2 \
-m 4096 \
-vga vmware \
-soundhw ac97 \
-usbdevice tablet \
-rtc base=localt
Public bug reported:
My Specs:
Slackware 14.2 x86_64 > Host
Nvidia GPU GTX660M
nvidia-driver-352.63
QEMU 2.7.0
Ubuntu 16.04.1 x86_64 > Guest
Unity
Xorg nouveau - 1:1.0.12-1build2
These are the startup options for Ubuntu:
qemu-system-x86_64 -drive format=raw,file=ubuntu.img \
-cpu host \
--enab
On Fri, Dec 09, 2016 at 11:08:02AM -0600, Michael Roth wrote:
> Quoting David Gibson (2016-12-08 20:23:11)
> > This introduces stub implementations of the H_RESIZE_HPT_PREPARE and
> > H_RESIZE_HPT_COMMIT hypercalls which we hope to add in a PAPR
> > extension to allow run time resizing of a guest's
Without the mips32r2 instructions to perform swapping, bswap is quite large,
dominating the size of each reverse-endian qemu_ld/qemu_st operation.
Create two subroutines in the prologue block. The subroutines require extra
reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means that
tcg_out_mov: using OPC_OR as most mips assemblers do;
tcg_out_movi: extended to 64-bit immediate.
Tested-by: Aurelien Jarno
Tested-by: James Hogan
Tested-by: YunQiang Su
Signed-off-by: Richard Henderson
Signed-off-by: Jin Guojie
---
tcg/mips/tcg-target.inc.c | 34 +---
Without the mips32r2 instructions to perform swapping, bswap is quite large,
dominating the size of each reverse-endian qemu_ld/qemu_st operation.
Create a subroutine in the prologue block. The subroutine requires extra
reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means that
we
Since the mips manual tables are in octal, reorg all of the opcodes
into that format for clarity. Note that the 64-bit opcodes are as
yet unused.
Tested-by: Aurelien Jarno
Tested-by: James Hogan
Tested-by: YunQiang Su
Signed-off-by: Richard Henderson
Signed-off-by: Jin Guojie
---
tcg/mips/t
Bulk patch adding 64-bit opcodes into tcg_out_op. Note that
mips64 is as yet neither complete nor enabled.
Tested-by: Aurelien Jarno
Tested-by: James Hogan
Tested-by: YunQiang Su
Signed-off-by: Richard Henderson
Signed-off-by: Jin Guojie
---
tcg/mips/tcg-target.h | 41 ++
tcg/mips/
Tested-by: Aurelien Jarno
Tested-by: James Hogan
Tested-by: YunQiang Su
Signed-off-by: Richard Henderson
Signed-off-by: Jin Guojie
---
tcg/mips/tcg-target.inc.c | 44
1 file changed, 44 insertions(+)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mi
Changes in v6:
* Update against master(v2.8.0-rc3)
* Fix two bugs according to Richard Henderson's review comments
(1) mask: extend TARGET_PAGE_MASK to the proper type
(2) zero-extend the guest address, not the address loaded from CMP_OFF
* MIPS R6: tested successfully on a qemu mipse
Tested-by: Aurelien Jarno
Tested-by: James Hogan
Tested-by: YunQiang Su
Signed-off-by: Richard Henderson
Signed-off-by: Jin Guojie
---
tcg/mips/tcg-target.inc.c | 203 +-
1 file changed, 146 insertions(+), 57 deletions(-)
diff --git a/tcg/mips/tcg-
tcg_out_ldst: using a generic ALIAS_PADD to avoid ifdefs
tcg_out_ld: generates LD or LW
tcg_out_st: generates SD or SW
Tested-by: Aurelien Jarno
Tested-by: James Hogan
Tested-by: YunQiang Su
Signed-off-by: Richard Henderson
Signed-off-by: Jin Guojie
---
tcg/mips/tcg-target.inc.c | 14 +++
Take stack frame parameters out from the function body.
Tested-by: Aurelien Jarno
Tested-by: James Hogan
Tested-by: YunQiang Su
Signed-off-by: Richard Henderson
Signed-off-by: Jin Guojie
---
tcg/mips/tcg-target.inc.c | 54 ++-
1 file changed, 25 in
Tested-by: Aurelien Jarno
Tested-by: James Hogan
Tested-by: YunQiang Su
Signed-off-by: Richard Henderson
Signed-off-by: Jin Guojie
---
tcg/mips/tcg-target.h | 19 +++
tcg/mips/tcg-target.inc.c | 21 +++--
2 files changed, 30 insertions(+), 10 deletions(-)
On Fri, Dec 09, 2016 at 04:30:20PM +, Peter Maydell wrote:
> The architectural timers in ARM CPUs all have level triggered interrupts
> (unless you're using KVM on a host kernel before 4.4, which misimplemented
> them as edge-triggered).
>
> We were incorrectly describing them in the device tr
Hi,
I am getting a strange compilation error lately for aarch64-linux-user. I
think it is somehow related to TYPE_PTRVOID handling but my investigation has
not led to anything concrete. I think this is a compiler error since the build
passes on an other system with gcc-6.
Info: ubuntu 16.04 x86_6
On Sun, Dec 11, 2016 at 2:09 PM, Pranith Kumar wrote:
> Hi,
>
> I am getting a strange compilation error lately for aarch64-linux-user. I
> think it is somehow related to TYPE_PTRVOID handling but my investigation has
> not led to anything concrete. I think this is a compiler error since the build
On 11 December 2016 at 16:35, Christoffer Dall
wrote:
> On Fri, Dec 09, 2016 at 04:30:20PM +, Peter Maydell wrote:
>> + * For backwards-compatibility, virt-2.8 and earlier will continue
>> + * to say these are edge-triggered, but later machines will report
>> + * the correct inform
On 11 December 2016 at 19:09, Pranith Kumar wrote:
> I am getting a strange compilation error lately for aarch64-linux-user. I
> think it is somehow related to TYPE_PTRVOID handling but my investigation has
> not led to anything concrete. I think this is a compiler error since the build
> passes o
** Summary changed:
- Passthrough of UAS devices fails with Windows (10) guests
+ [usb-host] Passthrough of UAS devices fails with Windows (10) guests
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/16
On Sat, Dec 10, 2016 at 11:59:09AM +0100, Laurent Vivier wrote:
> Le 09/12/2016 à 17:51, Thomas Huth a écrit :
> > On 09.12.2016 13:24, Laurent Vivier wrote:
> >> Le 09/12/2016 à 13:17, Thomas Huth a écrit :
> >>> To be able to compile the CPU targets from within a subfolder
> >>> of the target/ fo
On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
> xxextractuw: VSX Vector Extract Unsigned Word
>
> Signed-off-by: Nikunj A Dadhania
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 21 +
> target-ppc/translate/vsx
On Fri, Dec 09, 2016 at 05:47:19PM +0530, Nikunj A Dadhania wrote:
> This series contains 6 new instructions for POWER9 ISA3.0
> VSX Vector Insert/Extract Word
> VSX Load/Store with length
>
> Although, lxvl/lxvll and stxvl/stxvll can be combined as single patch,
> have left it for detai
On Fri, Dec 09, 2016 at 11:08:02AM -0600, Michael Roth wrote:
> Quoting David Gibson (2016-12-08 20:23:11)
> > This introduces stub implementations of the H_RESIZE_HPT_PREPARE and
> > H_RESIZE_HPT_COMMIT hypercalls which we hope to add in a PAPR
> > extension to allow run time resizing of a guest's
On Sun, Dec 11, 2016 at 5:59 PM, Peter Maydell wrote:
>
>> Error:
>> /home/pranith/devops/code/qemu/linux-user/ioctls.h:224:9: error:
>> ‘SNDCTL_DSP_MAPINBUF’ undeclared here (not in a function)
>>IOCTL(SNDCTL_DSP_MAPINBUF, IOC_R, MK_PTR(MK_STRUCT(STRUCT_buffmem_desc)))
>> ^
>
> SNDC
On Thu, Dec 08, 2016 at 10:21:35AM +0800, Jason Wang wrote:
>
>
> On 2016年12月08日 10:16, Peter Xu wrote:
> >On Thu, Dec 08, 2016 at 10:02:15AM +0800, Jason Wang wrote:
> >>
> >>On 2016年12月07日 13:52, Peter Xu wrote:
> >>>Currently vt-d Context Entry (CE) only allows 39/48 bits address width.
> >>>I
On Sun, Dec 11, 2016 at 05:13:45AM +0200, Michael S. Tsirkin wrote:
> On Wed, Dec 07, 2016 at 01:52:45PM +0800, Peter Xu wrote:
> > Previously vt-d codes only supports 39 bits iova address width. It won't
> > be hard to extend it to 48 bits.
> >
> > After enabling this, we should be able to map la
ping...
Thanks,
Chao Fan
On Tue, Dec 06, 2016 at 04:52:11PM +0800, Chao Fan wrote:
>Hi all,
>
>Here is an issue in auto-converge feature of migration.
>
>When migrating a guest which consumes too much CPU & memory, dirty
>pages amount will increase significantly, so does the migration
>time, migr
On Fri, Dec 09, 2016 at 10:18:59AM +0100, Thomas Huth wrote:
> On 09.12.2016 10:09, David Gibson wrote:
> > On Fri, Dec 09, 2016 at 09:18:51AM +0100, Thomas Huth wrote:
> >> On 09.12.2016 03:23, David Gibson wrote:
> >>> This introduces stub implementations of the H_RESIZE_HPT_PREPARE and
> >>> H_R
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Signed-off-by: Peter Xu
---
lib/libcflat.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index c622198..8455c3d 100644
--- a/lib/libcflat.h
+++ b/lib/libcflat.h
@@ -104,4 +104,9 @@ do {
This will be useful to be put inside loops.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Signed-off-by: Peter Xu
---
lib/x86/asm/barrier.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/lib/x86/asm/barrier.h b/lib/x86/asm/barrier.h
index 7c108bd..193fb4c 100644
--- a/
Suggested-by: Andrew Jones
Signed-off-by: Peter Xu
---
lib/pci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/pci.h b/lib/pci.h
index 30f5381..86d6b42 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -43,7 +43,7 @@ extern bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
These macros will be useful to do page alignment checks.
Reviewed-by: Andrew Jones
Signed-off-by: Peter Xu
---
lib/libcflat.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index 8455c3d..88b10e2 100644
--- a/lib/libcflat.h
+++ b/lib/libcflat.h
@@ -33,
Adding fundamental init test for Intel IOMMU. This includes basic
initialization of Intel IOMMU device, like DMAR (DMA Remapping),
IR (Interrupt Remapping), QI (Queue Invalidation), etc.
Further tests can use vtd_init() to initialize Intel IOMMU environment.
x86/unittests is updated to add this t
This is v8 of vt-d unit test series.
(CC qemu-devel list this time.)
Patch "libcflat: add IS_ALIGNED() macro, and page sizes" is picked up
by Drew in the ARM GIC framework series, so please feel free to drop
it when needed.
Online repo:
https://github.com/xzpeter/kvm-unit-tests.git iommu-ut-v
To extend current PCI framework, we need a per-device struct to store
device specific information. Time to have a pci_dev struct. Most of the
current PCI APIs are converted to use this pci_dev object as the first
argument. Currently it only contains one field "bdf", which is the bdf
of current devi
One helper function to set/clear specific bit in PCI_COMMAND register is
introduced. Then, provide a function to do most of the common PCI init
work.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Signed-off-by: Peter Xu
---
lib/pci.c | 19 +++
lib/pci.h | 2 ++
2 files
That's something can be used outside alloc.c.
Reviewed-by: Andrew Jones
Signed-off-by: Peter Xu
---
lib/alloc.c| 3 ---
lib/libcflat.h | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/alloc.c b/lib/alloc.c
index e1d7b8a..58af52b 100644
--- a/lib/alloc.c
+++ b/lib/
Let's provide a more general way to scan PCI bars, rather than read the
config registers every time.
Then let x86/vmexit.c leverage pci_scan_bars()
Reviewed-by: Andrew Jones
Signed-off-by: Peter Xu
---
lib/pci-host-generic.c | 2 +-
lib/pci.c | 17 -
lib/pci.h
This can be used in further patches.
Reviewed-by: Andrew Jones
Signed-off-by: Peter Xu
---
lib/x86/asm/page.h | 3 +++
lib/x86/vm.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/lib/x86/asm/page.h b/lib/x86/asm/page.h
index 5044a49..c43bab2 100644
--- a/lib/x86/
QEMU edu device is a pci device that is originally written for
educational purpose, however it also suits for IOMMU unit test. Adding
helpers for this specific device to implement the device logic.
The device supports lots of functions, here only DMA operation is
supported.
The spec of the device
DMAR test is based on QEMU edu device. A 4B DMA memory copy is carried
out as the simplest DMAR test.
Signed-off-by: Peter Xu
---
lib/pci.h | 5 ++
lib/x86/intel-iommu.c | 133 ++
lib/x86/intel-iommu.h | 4 ++
x86/Makefile.common
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Sunday, December 11, 2016 10:51 AM
> To: Eric Blake
> Cc: Gonglei (Arei); qemu-devel@nongnu.org; stefa...@redhat.com
> Subject: Re: [PATCH for-2.9 v2] virtio-crypto: zeroize the key material before
> free
>
pci_cap_walk() is provided to allow walk through all the capability bits
for a specific PCI device. If a cap handler is provided, it'll be
triggered if the cap is detected along the cap walk.
MSI cap handler is the first one supported. We can add more cap handler
in the future.
Meanwhile, pci_set
First of all, vtd_setup_msi() is provided. It setup IRTE entries,
meanwhile, setup PCI device MSI vectors corresponding to VT-d spec.
Meanwhile, IR MSI test is added to intel IOMMU unit test. The basic IR
test is carried out by a edu INTR raise request. When write to the intr
raise register, inter
>
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Sunday, December 11, 2016 11:38 AM
> To: Gonglei (Arei)
> Cc: qemu-devel@nongnu.org; Wubin (H); longpeng
> Subject: Re: [PATCH for-2.9 0/3] cryptodev: prepare works for hotplug
>
> On Mon, Dec 05, 2016 at 11:27:09AM +0800, Gonglei wrote
On Sat, 12/10 18:16, Liviu Ionescu wrote:
> conclusions:
>
> - the graphical event loop and all graphical primitives must be called from
> the main thread context
> - in qemu this is not possible directly; an inefficient but functional
> solution uses a timer programmed to call a function every f
This patch implements hypercalls allowing a PAPR guest to resize its own
hash page table. This will eventually allow for more flexible memory
hotplug.
The implementation is partially asynchronous, handled in a special thread
running the hpt_prepare_thread() function. The state of a pending resiz
Signed-off-by: David Gibson
Reviewed-by: Thomas Huth
Reviewed-by: Laurent Vivier
---
hw/ppc/spapr.c | 23 +--
include/hw/compat.h | 3 +++
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index cfadc46..0f25e83 100644
---
This introduces stub implementations of the H_RESIZE_HPT_PREPARE and
H_RESIZE_HPT_COMMIT hypercalls which we hope to add in a PAPR
extension to allow run time resizing of a guest's hash page table. It
also adds a new machine property for controlling whether this new
facility is available, and logi
We've now implemented a PAPR extension allowing PAPR guest to resize
their hash page table (HPT) during runtime.
This patch makes use of that facility to allocate smaller HPTs by default.
Specifically when a guest is aware of the HPT resize facility, qemu sizes
the HPT to the initial memory size,
This series implements the host side of the PAPR ACR to allow runtime
resizing of the Hashed Page Table (HPT) for pseries guests.
Exercising this feature requires a guest OS which is also aware of it.
Patches to implement the guest side in Linux have just been submitted
upstream:
https://lists.ozl
On Mon, Dec 12, 2016 at 09:31:11AM +0530, Nikunj Dadhania wrote:
> On 12 December 2016 at 06:00, David Gibson
> wrote:
> > On Fri, Dec 09, 2016 at 05:47:24PM +0530, Nikunj A Dadhania wrote:
> >> xxextractuw: VSX Vector Extract Unsigned Word
> >>
> >> Signed-off-by: Nikunj A Dadhania
> >> ---
> >
We've now implemented a PAPR extensions which allows PAPR guests (i.e.
"pseries" machine type) to resize their hash page table during runtime.
However, that extension is only enabled if explicitly chosen on the
command line. This patch enables it by default for spapr-2.9, but leaves
it disabled (
On 12/10/2016 04:39 AM, Eduardo Habkost wrote:
> Using latest qemu.git master:
>
> $ qemu-system-x86_64 -machine q35 -readconfig docs/q35-chipset.cfg -monitor
> stdio
> QEMU 2.7.93 monitor - type 'help' for more information
> (qemu) device_add e1000e,bus=ich9-pcie-port-4,addr=00
> (qemu
Hi, Michael & Herbert
Because the virtio-crypto device emulation had been in QEMU 2.8,
would you please merge the virtio-crypto driver for 4.10 if no other
comments? If so, Miachel pls ack and/or review the patch, then
Herbert will take it (I asked him last week). Thank you!
Ps: Note on 4.10 merg
> On 12 Dec 2016, at 05:35, Fam Zheng wrote:
>
> Isn't it possible to notify the main thread with an EventNotifier and process
> the deferred events in its handler?
ideally, the SDL main loop might be re-implemented asynchronously, for example
using a pipe to pass the events, and in this case
This patch introduce HMAC algorithms relevant defination, they will
be used by the following patch.
Signed-off-by: Longpeng(Mike)
---
qapi/crypto.json | 17 +
1 file changed, 17 insertions(+)
diff --git a/qapi/crypto.json b/qapi/crypto.json
index f4fd93b..e63862a 100644
--- a/qa
This patch introduce HMAC algorithms framework.
Signed-off-by: Longpeng(Mike)
---
crypto/Makefile.objs | 4 ++
crypto/hmac-gcrypt.c | 44 ++
crypto/hmac-glib.c | 44 ++
crypto/hmac-nettle.c | 44 ++
crypto/hmac.c| 72 ++
cry
This patch add HMAC algorithms based on libgcrypt support
Signed-off-by: Longpeng(Mike)
---
crypto/hmac-gcrypt.c | 138 +++
1 file changed, 138 insertions(+)
diff --git a/crypto/hmac-gcrypt.c b/crypto/hmac-gcrypt.c
index 26f42bc..6cf3046 100644
--
This patch add nettle-backed HMAC algorithms support
Signed-off-by: Longpeng(Mike)
---
crypto/hmac-nettle.c | 118 +--
1 file changed, 115 insertions(+), 3 deletions(-)
diff --git a/crypto/hmac-nettle.c b/crypto/hmac-nettle.c
index 7a9cd2e..a082bc
Since QEMU has been supported cryptodev, so it is necessary to support
more crypto algorithms(i.e. hmac,aead) in QEMU backend.
This patchset add HMAC algorithms support.
Longpeng(Mike) (7):
qapi: crypto: add defination about HMAC algorithms
crypto: add HMAC algorithms framework
configure: a
This patch add HMAC algorithms testcases
Signed-off-by: Longpeng(Mike)
---
tests/Makefile.include | 2 +
tests/test-crypto-hmac.c | 162 +++
2 files changed, 164 insertions(+)
create mode 100644 tests/test-crypto-hmac.c
diff --git a/tests/Makefil
This item will be used for support libcrypt-backed HMAC algorithms.
Support for hmac has been added in Libgcrypt 1.6.0, but we cannot
use pkg-config to get libcrypt's version. However we can make a
in configure to know whether current libcrypt support hmac.
Signed-off-by: Longpeng(Mike)
---
con
This patch add glibc-backed HMAC algorithms support
Signed-off-by: Longpeng(Mike)
---
crypto/hmac-glib.c | 119 +
1 file changed, 119 insertions(+)
diff --git a/crypto/hmac-glib.c b/crypto/hmac-glib.c
index 42f63c6..6a5f722 100644
--- a/crypto
Hello Marcelo,
>
> Check for KVM_CAP_ADJUST_CLOCK capability KVM_CLOCK_TSC_STABLE, which
> indicates that KVM_GET_CLOCK returns a value as seen by the guest at
> that moment.
>
> For new machine types, use this value rather than reading
> from guest memory.
>
> This reduces kvmclock difference
10.12.2016 17:53, Max Reitz wrote:
On 09.12.2016 18:55, Vladimir Sementsov-Ogievskiy wrote:
09.12.2016 20:05, Max Reitz wrote:
On 22.11.2016 18:26, Vladimir Sementsov-Ogievskiy wrote:
Realize block bitmap storing interface, to allow qcow2 images store
persistent bitmaps.
Signed-off-by: Vladim
On Mon, 12/12 09:18, Liviu Ionescu wrote:
>
> > On 12 Dec 2016, at 05:35, Fam Zheng wrote:
> >
> > Isn't it possible to notify the main thread with an EventNotifier and
> > process
> > the deferred events in its handler?
>
> ideally, the SDL main loop might be re-implemented asynchronously, fo
> On 12 Dec 2016, at 09:39, Fam Zheng wrote:
>
>> any idea how difficult would be to push any changes to SDL?
>
> Not sure I understand this question, could you be more specific?
I guess making SDL run asynchronously will need some major changes to the SDL
source code, not simple patches that
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Subject: [Qemu-devel] [PATCH for-2.9 v1 0/7] crypto: add HMAC algorithms support
Type: series
Message-id: 1481527639-17520-1-g
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