On Tue, Sep 27, 2016 at 09:43:27AM +0200, Laurent Vivier wrote:
>
>
> On 27/09/2016 05:53, David Gibson wrote:
> > On Mon, Sep 26, 2016 at 04:10:49PM +0200, Laurent Vivier wrote:
>
> >> void qusb_pci_init_one(QPCIBus *pcibus, struct qhc *hc, uint32_t devfn,
> >> int bar)
> >> {
> >> hc->
Hello，recently I study qemu source code ,and I have some questions ,can you
help me ?
> 1、what is the meaning of queues in structure NICConf ? I think it is the
> number of queues to a NIC,and I do not where it is.
> 2、In NICConf init Function，I do not found it initulize the queues of
> NICC
This patch adds support for a new block device type called "vxhs".
Source code for the library that this code loads can be downloaded from:
https://github.com/MittalAshish/libqnio.git
Sample command line using JSON syntax:
./qemu-system-x86_64 -name instance-0008 -S -vnc 0.0.0.0:0 -k en-us -vg
On Wed, Sep 28, 2016 at 3:58 AM, John Snow wrote:
>
>
> On 09/27/2016 12:53 PM, Ashijeet Acharya wrote:
>>
>> Fix a memory leak in ide_register_restart_cb() in hw/ide/core.c and add
>> idebus_unrealize() in hw/ide/qdev.c to have calls to
>> qemu_del_vm_change_state_handler() to deal with the dangl
Le 28/09/2016 à 03:37, David Gibson a écrit :
On Tue, Sep 27, 2016 at 08:49:47PM +0200, Hervé Poussineau wrote:
Le 27/09/2016 à 06:11, David Gibson a écrit :
On Mon, Sep 26, 2016 at 10:23:24PM +0200, Hervé Poussineau wrote:
Signed-off-by: Hervé Poussineau
---
hw/intc/i8259.c | 37 +++
On Wed, Sep 21, 2016 at 8:03 AM, Paolo Bonzini wrote:
>
>
> On 21/09/2016 03:07, Ashish Mittal wrote:
>> +int32_t vxhs_qnio_iio_writev(void *qnio_ctx, uint32_t rfd, struct iovec
>> *iov,
>> +int iovcnt, uint64_t offset,
>> +
From: Wanpeng Li
Commit 96193c22a "target-i386: Move xsave component mask to features array"
leverages features array to handle XCR0 processor state component bits,
however, it introduces a regression:
warning: host doesn't support requested feature: CPUID.0DH:EAX [bit 0]
warning: host doesn't
This series contains 7 new instructions for POWER9 ISA3.0
Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x.
GCC was adding epilogue for every VSX instructions causing change in
behaviour. For testing the load vector instructions used mfvsrld/mfvsrd
for loading vsr to registe
From: Ravi Bangoria
mfvsrld: Move From VSR Lower Doubleword
Signed-off-by: Ravi Bangoria
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate/vsx-impl.inc.c | 17 +
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 18 insertions(+)
diff --git a/target-ppc/tran
From: Ravi Bangoria
mtvsrws: Move To VSR Word & Splat
Signed-off-by: Ravi Bangoria
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate/vsx-impl.inc.c | 23 +++
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 24 insertions(+)
diff --git a/target-ppc/tran
From: Ravi Bangoria
mtvsrdd: Move To VSR Double Doubleword
Signed-off-by: Ravi Bangoria
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate/vsx-impl.inc.c | 23 +++
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 24 insertions(+)
diff --git a/target-ppc
stxvh8x: Store VSX Vector Halfword*8
Vector:
+---+---+---+---+---+---+---+---+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+---+---+---+---+---+---+---+---+
Store results in following:
Big-Endian Storage
+
Load 8byte at a time and manipulate.
Big-Endian Storage
+-+-+-+-+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-+-+-+-+
Little-Endian Storage
+-+-+-+--
Manipulate data and store 8bytes instead of 4bytes.
Vector:
+-+-+-+-+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-+-+-+-+
Store results in following:
Big-Endian Storage
+-+
lxvb16x: Load VSX Vector Byte*16
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Vector load results in:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F
stxvb16x: Store VSX Vector Byte*16
Vector:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Store results in following:
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
lxvh8x: Load VSX Vector Halfword*8
Big-Endian Storage
+---+---+---+---+---+---+---+---+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+---+---+---+---+---+---+---+---+
Little-Endian Storage
+---+---+-
Nikunj A Dadhania writes:
> This series contains 7 new instructions for POWER9 ISA3.0
> Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x.
>
> GCC was adding epilogue for every VSX instructions causing change in
> behaviour. For testing the load vector instructions used mfvsr
Signed-off-by: Wen Congyang
Signed-off-by: Changlong Xie
Signed-off-by: Wang WeiWei
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
Reviewed-by: Eric Blake
---
qapi/block-core.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/block-core.json b/qapi/block-core.
The following vector compare not equal instructions are added from ISA 3.0.
vcmpneb - Vector Compare Not Equal Byte
vcmpneh - Vector Compare Not Equal Halfword
vcmpnew - Vector Compare Not Equal Word
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h |6 +++
From: Avinesh Kumar
vextublx: Vector Extract Unsigned Byte Left
vextuhlx: Vector Extract Unsigned Halfword Left
vextuwlx: Vector Extract Unsigned Word Left
Signed-off-by: Avinesh Kumar
[ Remove else part in helper ]
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h
This series contains 15 new instructions for POWER9 described in ISA3.0.
Patches:
01: Adds vector multiply instructions.
vmul10uq : Vector Multiply-by-10 Unsigned Quadword
vmul10euq : Vector Multiply-by-10 Extended Unsigned Quadword
vmul10cuq : Vector M
From: Hariharan T.S
vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form
vextuhrx: Vector Extract Unsigned Halfword Right-Indexed VX-form
vextuwrx: Vector Extract Unsigned Word Right-Indexed VX-form
Signed-off-by: Hariharan T.S.
Signed-off-by: Avinesh Kumar
Signed-off-by: Rajalakshmi
From: Vasant Hegde
vmul10uq : Vector Multiply-by-10 Unsigned Quadword VX-form
vmul10euq : Vector Multiply-by-10 Extended Unsigned Quadword VX-form
vmul10cuq : Vector Multiply-by-10 & write Carry Unsigned Quadword VX-form
vmul10ecuq: Vector Multiply-by-10 Extended & write Carry Unsigned Quadword
From: Avinesh Kumar
cmpl: invalid bit mask should be 0x0041
bctar: invalid bit mask should be 0xE000
Signed-off-by: Avinesh Kumar
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/translate.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target
The following vector instructions are added from ISA 3.0.
vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte
vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte
Signed-off-by: Rajalakshmi Srinivasaraghavan
---
target-ppc/helper.h |2 ++
target-ppc
On Tue, Sep 20, 2016 at 10:53 PM, Jeff Cody wrote:
> On Tue, Sep 20, 2016 at 06:07:45PM -0700, Ashish Mittal wrote:
>> This patch adds support for a new block device type called "vxhs".
>> Source code for the library that this code loads can be downloaded from:
>> https://github.com/MittalAshish/l
On Wed, 28 Sep 2016 10:14:00 +0800
李强 wrote:
> On 2016-09-28 0:40 GMT+08:00 Greg Kurz wrote:
>
> >
> > Talking about robustness was appropriate for your previous patches, but
> > it does not really apply here since v9fs_iov_vunmarshal() does not have
> > any issue with empty strings actually.
>
I also had this problem. You can try to configure the VM with core=1 and
thread=1. See if the "intr->er_full" assertion still exist.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1587970
Title:
QEM
On 28.09.2016 03:59, David Gibson wrote:
> On Tue, Sep 27, 2016 at 09:17:19AM +0200, Thomas Huth wrote:
>> On 27.09.2016 06:17, David Gibson wrote:
>>> On Mon, Sep 26, 2016 at 10:17:46PM +0200, Thomas Huth wrote:
[...]
diff --git a/tests/pxe-test.c b/tests/pxe-test.c
index b2cc355..0bdb7a
Hi Greg,
What about this patch?
It seems you have forget it.
2016-09-27 12:44 GMT+08:00 Li Qiang :
> From: Li Qiang
>
> 9pfs uses g_malloc() to allocate the xattr memory space, if the guest
> reads this memory before writing to it, this will leak host heap
> memory to the guest. This patch avo
On Tue, 27 Sep 2016 20:55:55 +0200
Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
> ---
Just a minor remark below, but anyway:
Reviewed-by: Greg Kurz
Cheers.
--
Greg
> tests/e1000e-test.c | 2 +-
> tests/i440fx-test.c | 2 +-
> tests/ide-test.c| 2 +-
On Tue, 27 Sep 2016 20:55:56 +0200
Laurent Vivier wrote:
> Machine specific shutdown function can be registered by
> the machine specific qtest_XXX_boot() if needed.
>
> So we will not have to test twice the architecture (on boot and on
> shutdown) if the test can be run on several architectures
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