From: Benjamin Herrenschmidt
Power ISA 2.x has deleted the rfi instruction and rfid shoud be used
instead on cpus following this instruction set or later.
This will raise an invalid exception when rfi is used on such
processors: Book3S 64-bit processors.
Signed-off-by: Benjamin Herrenschmidt
R
From: Rajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0.
vinsertb - Vector Insert Byte
vinserth - Vector Insert Halfword
vinsertw - Vector Insert Word
vinsertd - Vector Insert Doubleword
Signed-off-by: Rajalakshmi Srinivasaraghavan
Signed-off-by: Dav
From: Thomas Huth
There are some powerpc related files in the QEMU source tree
which are currently not covered by the MAINTAINERS file and
thus not properly classified by the get_maintainer.pl script.
So let's add them to the proper sections.
Signed-off-by: Thomas Huth
Signed-off-by: David Gibs
From: John Arbuckle
Add the adb-keys.h file. It maps ADB transition key codes with values.
Signed-off-by: John Arbuckle
Signed-off-by: David Gibson
---
include/hw/input/adb-keys.h | 141
1 file changed, 141 insertions(+)
create mode 100644 include
From: Rajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0.
vextractub - Vector Extract Unsigned Byte
vextractuh - Vector Extract Unsigned Halfword
vextractuw - Vector Extract Unsigned Word
vextractd - Vector Extract Unsigned Doubleword
Signed-off-by: R
From: Greg Kurz
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
MAINTAINERS | 4
1 file changed, 4 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a9fab46..847b614 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -628,6 +628,10 @@ F: pc-bios/spapr-rtas.bin
F: pc-bios/sl
From: John Arbuckle
The NO_KEY value should not be sent to the guest. This patch drops that value.
Signed-off-by: John Arbuckle
Signed-off-by: David Gibson
---
hw/input/adb.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/hw/input/adb.c b/hw/input
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Eric Blake
Signed-off-by: David Gibson
---
hw/ppc/spapr_rtas.c | 30 --
hw/ppc/trace-events | 8
2 files changed, 16 insertions(+), 22 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/
From: John Arbuckle
The original pc_to_adb_keycode mapping did have several keys that were
incorrectly mapped. This patch fixes these mappings.
Signed-off-by: John Arbuckle
Signed-off-by: David Gibson
---
hw/input/adb.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff
pc-for-2.8-20160923
for you to fetch changes up to 4814401fa01271235df2ac60fafc831bd3d624f3:
spapr_pci: Add numa node id (2016-09-23 12:39:07 +1000)
ppc patch queue 2016-09-23
This pull request supersedes ppc-for-2.8-20160922. There w
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Eric Blake
Signed-off-by: David Gibson
---
hw/scsi/spapr_vscsi.c | 88 +--
hw/scsi/trace-events | 27
2 files changed, 63 insertions(+), 52 deletions(-)
diff --gi
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Eric Blake
Signed-off-by: David Gibson
---
hw/ppc/spapr_drc.c | 54 -
hw/ppc/trace-events | 21 +
2 files changed, 41 insertions(+), 34 deletions(-)
diff -
From: Laurent Vivier
Check the result of qemu_strtoXX() and assert
if the string cannot be converted.
Signed-off-by: Laurent Vivier
Reviewed-by: David Gibson
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
qtest.c | 49 ++---
1 file changed
From: Nikunj A Dadhania
stxsibx - Store VSX Scalar as Integer Byte Indexed
stxsihx - Store VSX Scalar as Integer Halfword Indexed
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 3 +++
target-pp
From: Nikunj A Dadhania
Implement macro to consolidate load operations using newer
tcg_gen_qemu_ld functions.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 58 +-
1 file changed, 20 insertions(+), 38 d
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Eric Blake
Signed-off-by: David Gibson
---
hw/ppc/spapr_vio.c | 17 +++--
hw/ppc/trace-events | 4
2 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index 4
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Eric Blake
Signed-off-by: David Gibson
---
hw/net/spapr_llan.c | 61 ++---
hw/net/trace-events | 16 ++
2 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/
From: Ravi Bangoria
darn: Deliver A Random Number
Currently return invalid random number for all the case. This needs
proper algorithm to provide cryptographically suitable random data.
Reading from /dev/random can block and that is not an expected behaviour
while the cpu instruction is getting
From: Nikunj A Dadhania
Use macro for ld64 as well, this changes the function signature from
gen_qemu_ld64 => gen_qemu_ld64_i64. Replace this at all the call sites.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 39 +++---
From: Nikunj A Dadhania
Make byte-swap routines use the common GEN_QEMU_LOAD macro
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 27 ++-
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/target-ppc/translate.c b
From: Nikunj A Dadhania
Use tcg_gen_qemu_st store conditional instructions.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 58 +-
1 file changed, 24 insertions(+), 34 deletions(-)
diff --git a/target-p
From: Nikunj A Dadhania
Being a 16byte operation, qemu_ld/st still does not support this. Move
this out so other store operation can use qemu_ld/st in the following
patch. Also, convert it to two MO_Q operations for stqcx.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
targe
From: Nikunj A Dadhania
Introduces bit-flag in CPUPPCState::tlb_need_flush:
TLB_NEED_LOCAL_FLUSH (0x1) - Flush local tlb
This would indicate a pending local tlb flush (isync instructions,
interrupts, ...)
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
Signed-off-by: David Gibso
From: Nikunj A Dadhania
Make byte-swap routines use the common GEN_QEMU_STORE macro
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 32 ++--
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/target-ppc/transla
From: Nikunj A Dadhania
Use tcg_gen_qemu_ld in the load with reservation instructions.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target-ppc/translate.c b/
From: Rajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0.
Signed-off-by: Rajalakshmi Srinivasaraghavan
Signed-off-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 23 +++
target-ppc/translate/vmx-impl.inc
From: Bharata B Rao
Each spapr cpu core type defines an instance_init routine which just
populates the CPU class name. This can be done in the class_init
commonly for all core types which simplifies the registration.
This is inspired by how PowerNV core types are registered.
Certain types of spa
From: Nikunj A Dadhania
lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed
lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 2 ++
From: Nikunj A Dadhania
Use macro for st64 as well, this changes the function signature from
gen_qemu_st64 => gen_qemu_st64_i64. Replace this at all the call sites.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 37 ++
From: Nikunj A Dadhania
tlbie (BookS) and tlbivax (BookE) plus the H_CALLs(pseries) should have
a global effect.
Introduces TLB_NEED_GLOBAL_FLUSH flag. During lazy tlb flush, after
taking care of pending local flushes, check broadcast flush(at context
synchronizing event ptesync/tlbsync, etc) is
From: Nikunj A Dadhania
xxspltib: VSX Vector Splat Immediate Byte
Copy the immediate byte in each byte of target VSR
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 20
ta
From: Michael Walle
Only the POWER[789] CPUs should have the ARCH_206 bit set. This is what the
linux kernel does. I guess this was also the intention of commit 0e019746.
We have to make sure all *206 bits are set.
Before this patch, the flags check in the GET_FEATURES2 macro returned true
if _a
From: Thomas Huth
QEMU currently refuses to start with KVM-PR and only prints out
qemu: fatal: Unknown MMU model 851972
when being started there. This is because commit 4322e8ced5aaac719
("ppc: Fix 64K pages support in full emulation") introduced a new
POWERPC_MMU_64K bit to indicate su
From: Benjamin Herrenschmidt
This will make life easier for dealing with dynamically configured
ICSes such as PHB3
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: David Gibson
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
include/hw/ppc/xics.h | 2 +-
1 file changed, 1
From: Rajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are
added from ISA 3.0.
vctzb - Vector Count Trailing Zeros Byte
vctzh - Vector Count Trailing Zeros Halfword
vctzw - Vector Count Trailing Zeros Word
vctzd - Vector Count Trailing Zeros Doubleword
Signed
From: Nikunj A Dadhania
Fix inconsistent irq status, because of this in the trace logs, for e.g.
LSI status was 0x7, i.e. XICS_STATUS_ASSERTED, XICS_STATUS_SENT and
XICS_STATUS_REJECTED all set, which did not make sense. So the REJECTED
would have been set in earlier interrupt cycle, and then ass
From: Nikunj A Dadhania
Implement macro to consolidate store operations using newer
tcg_gen_qemu_st function.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target-ppc/translate.c | 35 ---
1 file changed, 16 insertions(+), 19 deletions(-)
di
From: Nikunj A Dadhania
We flush the qemu TLB lazily. check_tlb_flush is called whenever we hit
a context synchronizing event or instruction that requires a pending
flush to be performed.
However, we fail to handle broadcast TLB flush operations. In order to
fix that efficiently, we want to diff
From: Nathan Whitehorn
These are mandatory per PAPR and available on Linux 4.3 and newer kernels. The
calls in question are required to run FreeBSD guests with reasonable
performance, so enable them if possible.
Signed-off-by: Nathan Whitehorn
[dwg: Added a stub to fix compile without KVM (e.
From: Rajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0.
Signed-off-by: Rajalakshmi Srinivasaraghavan
Signed-off-by: David Gibson
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 20
target-ppc/translate/vmx-impl.inc.c
Now that we allow CPU hot unplug on a few platforms, we can end up in a
situation where we don't have a CPU with index 0. Or at least we could,
if we didn't have code to explicitly prohibit unplug of CPU 0.
Longer term we want to allow CPU 0 unplug, this patch is an early step in
allowing this, b
From: Benjamin Herrenschmidt
There were a number of bugs in the implementation:
- The structure alignment was wrong for 64-bit.
- Also 64-bit only does RT signals.
- On 64-bit, we need to put a pointer to the (aligned) vector registers
in the frame and use it for restoring
- We had end
From: Laurent Vivier
Define spapr_alloc_init()/spapr_alloc_init_flags()/spapr_alloc_uninit()
to allocate and use SPAPR guest memory
Define qtest_spapr_vboot()/qtest_spapr_boot()/qtest_spapr_shutdown()
to start SPAPR guest with QOSState initialized for it (memory management)
Move qtest_irq
From: Laurent Vivier
Add a first test to validate the protocol:
- rtas/get-time-of-day compares the time
from the guest with the time from the host.
Signed-off-by: Laurent Vivier
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr_rtas.c | 19
include/
into staging (2016-09-22 15:39:54 +0100)
are available in the git repository at:
git://github.com/lalrae/qemu.git tags/mips-20160923
for you to fetch changes up to fea55615b2f924128e115ceb2265069561b03ef8:
linux-user: Add missing Mips syscalls items in strace.list (2016-0
From: Alexey Kardashevskiy
This adds a numa id property to a PHB to allow linking passed PCI device
to CPU/memory. It is up to the management stack to do CPU/memory pinning
to the node with the actual PCI device.
Signed-off-by: Alexey Kardashevskiy
[dwg: Renamed property from "node" to "numa_no
Hello,
On 07/04/2016 07:57 PM, mar.krzeminski wrote:
>
>
> W dniu 04.07.2016 o 14:18, Cédric Le Goater pisze:
>> Some SPI controllers, such as the Aspeed AST2400, have a mode in which
>> accesses to the flash content are no different than doing MMIOs. The
>> controller generates all the necessar
From: André Draszik
Define a new CPU definition supporting 24KEc cores, similar to
the existing 24Kc, but with added support for DSP instructions
and MIPS16e (and without FPU).
Signed-off-by: André Draszik
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 22 ++
From: Aleksandar Markovic
EDQUOT is defined for Mips platform in Linux kernel in such a way
that it has different value than on most other platforms. However,
correspondent TARGET_EDQUOT for Mips is missing in Qemu code. Moreover,
TARGET_EDQUOT is missing from the table for conversion of error co
From: Aleksandar Markovic
This patch corrects target_semid64_ds structure definition for Mips.
See, for example definition of semid64_ds for Mips in Linux kernel:
arch/mips/include/uapi/asm/sembuf.h#L13.
This patch will also fix certain semaphore-related LTP tests for Mips,
if they are executed
From: John Arbuckle
The old pc scancode translation is replaced with QEMU's QKeyCode. This is just
a mechanical substitution, which a number of broken mappings left in.
Signed-off-by: John Arbuckle
Signed-off-by: David Gibson
---
hw/input/adb.c | 234 ++
From: Aleksandar Markovic
Structure flock is defined for Mips in a way different from any
other platform. For reference, see Linux kernel source code files:
arch/mips/include/uapi/asm/fcntl.h, line 63 (for Mips)
include/uapi/asm-generic/fcntl.h, line 195 (for all other platforms)
This patch fix
From: Aleksandar Markovic
The function that is changed in this patch is supposed to indicate that
there was certain argument rearrangement related to 64-bit arguments on
32-bit platforms. The background on such rearrangements can be found,
for example, in the man page for syscall(2).
However, fo
From: Aleksandar Markovic
Without this patch, a number of Mips syscalls will be logged in the following
way (in this example, this is an invocation of accept4()):
86906 Unknown syscall 4334
This patch provides standard Qemu's strace output for such cases, like this:
95861 accept4(3,1996486
On Fri, Sep 23, 2016 at 05:22:03PM +1000, David Gibson wrote:
> I think we're ready to go with this. I still think 3/3 is premature,
> but I don't care that much.
>
> Peter, thanks for your patience with my nitpicking of the interface.
My pleasure to have discussion with you on this. And (always
On 22/09/2016 15:16, Herongguang (Stephen) wrote:
> I have some concern:
> 1. For example, vhost does not know about as_id, I wonder if guests in
> SMM can operate disk or ether card, as in
> that case vhost would not logging dirty pages correctly, without knowing
> as_id.
In the end memory is l
On Fri, Sep 23, 2016 at 01:02:25PM +0800, Peter Xu wrote:
> V7:
> - add comments to memory_region_notify_iommu() to better clarify the
> interface [David]
> - vfio_iommu_map_notify(): remove pointless "IOMMUTLBEntry *iotlb =
> data" [David]
> - typo fix on English [David]
>
> V6:
> - use IOMMU
On Fri, Sep 23, 2016 at 01:02:26PM +0800, Peter Xu wrote:
> IOMMU Notifier list is used for notifying IO address mapping changes.
> Currently VFIO is the only user.
>
> However it is possible that future consumer like vhost would like to
> only listen to part of its notifications (e.g., cache inva
From: Sergey Fedorov
Use async_safe_run_on_cpu() to make tb_flush() thread safe. This is
possible now that code generation does not happen in the middle of
execution.
It can happen that multiple threads schedule a safe work to flush the
translation buffer. To keep statistics and debugging outpu
Changes from v7
patch 1: one more instance to change
patch 4: rename cpu_list_mutex to cpu_list_lock [Emilio]
avoid problems from spurious wakeups [me]
patch 6: rename qemu_cpu_list_mutex to qemu_cpu_list_lock (ripples
to other patches afterwards) [Emilio]
patch 13: adjust com
From: Sergey Fedorov
Make CPU work core functions common between system and user-mode
emulation. User-mode does not use run_on_cpu, so do not implement it.
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <1470158864-
Set cpu->running without taking the cpu_list lock, only requiring it if
there is a concurrent exclusive section. This requires adding a new
field to CPUState, which records whether a running CPU is being counted
in pending_cpus.
When an exclusive section is started concurrently with cpu_exec_star
Make use of memory barrier TCG opcode in MIPS front end.
Signed-off-by: Leon Alrae
Reviewed-by: Richard Henderson
---
target-mips/translate.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
i
From: Sergey Fedorov
Convert pthread_mutex_t and pthread_cond_t to QemuMutex and QemuCond.
This will allow to make some locks and conditional variables common
between user and system mode emulation.
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-of
No need to call exclusive_idle() from cpu_exec_end since it is done
immediately afterwards in cpu_exec_start. Any exclusive section could
run as soon as cpu_exec_end leaves, because cpu->running is false and the
mutex is not taken, so the call does not add any protection either.
Signed-off-by: Pa
This series introduces support for in-kernel GICv3 ITS emulation.
On dt guest the functionality is complete and was tested on Cavium ThunderX
with virtio-net-pci and vhost-net.
On ACPI guest the series was tested with virtio-net-pci only. For vhost-net,
using MSIX we currently miss the ACPI IORT
From: Aleksandar Markovic
This patch fixes wrong definition of TARGET_SIOCATMARK for mips,
alpha, and sh4.
The current definition is:
#define SIOCATMARK 0x8905
while the correct definition is:
#define SIOCATMARK TARGET_IOR('s', 7, int)
See Linux kernel source file arch/mips/inc
Add a mutex for the CPU list to system emulation, as it will be used to
manage safe work. Abstract manipulation of the CPU list in new functions
cpu_list_add and cpu_list_remove.
Signed-off-by: Paolo Bonzini
---
Makefile.objs | 2 +-
bsd-user/main.c | 9 +
cpus-commo
David Gibson writes:
> On Thu, Sep 22, 2016 at 03:03:50PM +0100, Peter Maydell wrote:
>> On 22 September 2016 at 07:36, David Gibson
>> wrote:
>> > The following changes since commit
>> > a008535b9fa396226ff9cf78b8ac5f3584bda58e:
>> >
>> > build-sys: fix make install regression (2016-09-20
From: Pavel Fedin
This is the basic skeleton for both KVM and software-emulated ITS.
Since we already prepare status structure, we also introduce complete
VMState description. But, because we currently have no migratable
implementations, we also set unmigratable flag.
Signed-off-by: Pavel Fedin
From: Aleksandar Markovic
For some reason, Qemu's TARGET_F_GETOWN constant for Mips does not
match the correct value of correspondent F_GETOWN. This patch fixes
this problem.
For reference, see Mips' F_GETOWN definition in Linux kernel at
arch/mips/include/uapi/asm/fcntl.h#L44.
This patch also
Reviewed-by: Alex Bennée
Signed-off-by: Paolo Bonzini
---
cpus-common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpus-common.c b/cpus-common.c
index 2005bfe..d6cd426 100644
--- a/cpus-common.c
+++ b/cpus-common.c
@@ -88,8 +88,7 @@ struct qemu_work_item {
struc
From: Shannon Zhao
ACPI Spec 6.0 introduces GIC Interrupt Translation Service Structure.
Here we add the definition of the Structure.
Signed-off-by: Shannon Zhao
Signed-off-by: Eric Auger
---
v6 -> v7:
- added my Sob
---
include/hw/acpi/acpi-defs.h | 13 -
1 file changed, 12 ins
From: Pavel Fedin
Introduce global kvm_msi_use_devid flag plus associated
kvm_msi_devid_required() macro. Passes the device ID,
if needed, while building the MSI route entry. Device IDs are
required by the ARM GICv3 ITS (IRQ remapping function is based on
this information).
Signed-off-by: Pavel
async_run_on_cpu is only called from the I/O thread, not from CPU threads,
so it doesn't make any difference. It will make a difference however
for async_safe_run_on_cpu.
Reviewed-by: Alex Bennée
Signed-off-by: Paolo Bonzini
---
cpus-common.c | 5 -
1 file changed, 5 deletions(-)
diff --g
Marc-André Lureau writes:
> Hi
>
> - Original Message -
>> Marc-André Lureau writes:
>>
>> > Hi
>> >
>> > - Original Message -
>> >> Marc-André Lureau writes:
>> >>
>> >> > Hi
>> >> >
>> >> > - Original Message -
>> >> >> Marc-André Lureau writes:
>> >> >>
>> >> >> >
On Thu, Sep 22, 2016 at 11:09:55PM +0800, MPRC wrote:
> Hi, I'm fixing the syscall problem for linux-user/unicore32 in qemu.
>
> I write a "hello world" program to test linux-user/unicore32 in qemu 2.7 with
> toolchain of uc4-1.0.5(you can download it through
> http://mprc.pku.edu.cn/~guanxuetao
From: Sergey Fedorov
Move the code common between run_on_cpu() and async_run_on_cpu() into a
new function queue_work_on_cpu().
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <1470158864-17651-4-git-send-email-alex.b
From: Shannon Zhao
If GIC ITS is supported, add description in ACPI MADT table, then guest
could use ITS when booting with ACPI.
Signed-off-by: Shannon Zhao
Signed-off-by: Eric Auger
---
v6 -> v7:
- added my Sob
---
hw/arm/virt-acpi-build.c | 12
1 file changed, 12 insertions(+
Signed-off-by: Paolo Bonzini
---
cpus-common.c | 33 +++--
include/qom/cpu.h | 14 ++
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/cpus-common.c b/cpus-common.c
index 429652c..38b1d55 100644
--- a/cpus-common.c
+++ b/cpus-common.c
@@
Keep track of gl_block state (added in bba19b8 console: block rendering
until client is done) in QemuConsole and allow to query it. This way
we can avoid state inconsistencies in case different code paths make use
of this.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Marc-André Lureau
---
include
From: Sergey Fedorov
To avoid possible confusion, rename flush_queued_work() to
process_queued_cpu_work().
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <1470158864-17651-6-git-send-email-alex.ben...@linaro.org>
Si
Machine.c contains code related to migration. Let's move
gicv3_class_name to kvm_arm.h instead.
Signed-off-by: Eric Auger
Suggested-by: Peter Maydell
Reviewed-by: Peter Maydell
---
v5 -> v6:
- add Peter's R-b
v4 -> v5:
- add #include "qemu/error-report.h"
- rebased on target-arm: Fix unreach
Hi,
Have been sitting on these patches for quite a while. There used to be
problems with this due to bugs in spice. Finally found the time to
re-test this properly with the latest spice-server and spice-gtk
versions. Everything is working fine now, so it is time to get this
finally merged.
c
From: Alex Bennée
CPUState is a fairly common pointer to pass to these helpers. This means
if you need other arguments for the async_run_on_cpu case you end up
having to do a g_malloc to stuff additional data into the routine. For
the current users this isn't a massive deal but for MTTCG this get
From: Pavel Fedin
The ITS control frame is in-kernel emulated while accesses to the
GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
direct MSI injection advertised by the CAP_SIGNAL_MSI capability)
the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
differen
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <1470158864-17651-9-git-send-email-alex.ben...@linaro.org>
Signed-off-by: Paolo Bonzini
---
linux-user/main.c | 10 ++
1 file changed, 10
Eric Blake writes:
> On 09/22/2016 06:51 AM, Markus Armbruster wrote:
>>>
>>> I think the file probably should not have been listed as public domain
>>> in the first place, as its initial contents were copied from qemu-common.h
>>> which is not public domain.
>>
>> Ewww! Needs fixing.
>
> Indee
From: Pavel Fedin
If supported by the configuration, ITS will be added automatically.
This patch also renames v2m_phandle to msi_phandle because it's now used
by both MSI implementations.
Signed-off-by: Pavel Fedin
Signed-off-by: Eric Auger
Reviewed-by: Peter Maydell
--
v3 -> v4:
- added P
This will serve as the base for async_safe_run_on_cpu. Because
start_exclusive uses CPU_FOREACH, merge exclusive_lock with
qemu_cpu_list_lock: together with a call to exclusive_idle (via
cpu_exec_start/end) in cpu_list_add, this protects exclusive work
against concurrent CPU addition and removal.
On 23/09/2016 10:10, Markus Armbruster wrote:
> For me, the similarity (at the conceptual level) to the persistent
> memory case is striking: in both cases, we need a backend to manage
> memory contents. The difference is that for persistent memory, changes
> persist, while for the loader, they
This switches over spice (in opengl mode) to render DisplaySurface
updates into a opengl texture, using the helper functions in
ui/console-gl.c. With this patch applied spice (with gl=on) will
stop using qxl rendering ops, it will use dma-buf passing all the
time, i.e. for bios/bootloader (before
Signed-off-by: Paolo Bonzini
---
docs/tcg-exclusive.promela | 176 +
1 file changed, 176 insertions(+)
create mode 100644 docs/tcg-exclusive.promela
diff --git a/docs/tcg-exclusive.promela b/docs/tcg-exclusive.promela
new file mode 100644
index 00
> - changed PATH_MAX to 128 in sysfs() patch (last remaining item
> that was supposed to be in the previous version)
At first glance of the patch, you didn't change the good PATH_MAX...
Laurent
It slipped through the cracks. Sorry. :( My bad. But all other changes are in.
Rebase is also good, t
On Wed, 09/21 14:24, John Snow wrote:
>
>
> On 08/12/2016 05:19 AM, Fam Zheng wrote:
> > Previously all test cases in a category, such as check-qtest-y, are
> > executed in a single long gtester command. This patch separates each
> > test into its own make target to allow better parallism.
> >
>
It is not necessary to hold qemu_cpu_list_mutex throughout the
exclusive section, because no other exclusive section can run
while pending_cpus != 0.
exclusive_idle() is called in cpu_exec_start(), and that prevents
any CPUs created after start_exclusive() from entering cpu_exec()
during an exclus
> -Original Message-
> From: Zeng, Xin [mailto:xin.z...@intel.com]
> Sent: Friday, September 23, 2016 1:39 PM
> To: Gonglei (Arei); virtio-...@lists.oasis-open.org; qemu-devel@nongnu.org
> Cc: m...@redhat.com; Keating, Brian A; Griffin, John; Ma, Liang J; Hanweidong
> (Randy); Wubin (H)
>
On 2016/9/23 15:17, Paolo Bonzini wrote:
On 22/09/2016 15:16, Herongguang (Stephen) wrote:
I have some concern:
1. For example, vhost does not know about as_id, I wonder if guests in
SMM can operate disk or ether card, as in
that case vhost would not logging dirty pages correctly, without kn
Advertise gsi routing and set up irqchip routing entries for
GIC SPIs.
This is not mandated as long as MSI routing is not used
(because the kernel sets a default irqchip routing table).
However once MSI routing gets used (for VIRTIO-PCI vhost for
example), the first call to KVM_SET_GSI_ROUTING ove
Hi
- Original Message -
> Arguing further about the perfect order feels like a waste of time.
>
> You're free to post this in the order you feel is right. If it differs
> from the order that I feel is right for my review, then please post the
> whole thing, so I can review it effectively
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