Le 11/07/2016 à 18:59, Peter Maydell a écrit :
> On 8 July 2016 at 00:17, Laurent Vivier wrote:
>> TARGET_NR_select can have three different implementations:
>>
>> 1- to always return -ENOSYS
>>
>> microblaze, ppc, ppc64
>>
>> -> TARGET_WANT_NI_OLD_SELECT
>>
>> 2- to take parameters
Hello,
This is another iteration of the virtio-pstore work. I've addressed
comments from Michael S. Tsirkin on the kernel code.
* changes in v5)
- convert __virtioXX to __leXX (Michael)
* changes in v4)
- use qio_channel_file_new_path() (Daniel)
- rename to delete_old_pstore_file (Da
The virtio pstore driver provides interface to the pstore subsystem so
that the guest kernel's log/dump message can be saved on the host
machine. Users can access the log file directly on the host, or on the
guest at the next boot using pstore filesystem. It currently deals with
kernel log (print
From: Namhyung Kim
Add virtio pstore device to allow kernel log files saved on the host.
It will save the log files on the directory given by pstore device
option.
$ qemu-system-x86_64 -device virtio-pstore,directory=dir-xx ...
(guest) # echo c > /proc/sysrq-trigger
$ ls dir-xx
dmesg-1
From: Namhyung Kim
Add virtio pstore device to allow kernel log messages saved on the
host. With this patch, it will save the log files under directory given
by --pstore option.
$ lkvm run --pstore=dir-xx
(guest) # echo c > /proc/sysrq-trigger
$ ls dir-xx
dmesg-1.enc.z dmesg-2.enc.z
On 02/09/2016, 16:05, "Alexander Graf" wrote:
>>>There is a big problem that the control handle logic is synchronization,
>>>but the data queue
>>>handling logic is asynchronization. We can't combine them into one
>>>queue.
>>>It will decrease the performance because you need indentify each pac
Nikunj A Dadhania writes:
> Benjamin Herrenschmidt writes:
>
>> On Fri, 2016-09-02 at 12:02 +0530, Nikunj A Dadhania wrote:
>>> Signed-off-by: Nikunj A Dadhania
>>> ---
>>> cputlb.c| 15 +++
>>> include/exec/exec-all.h |2 ++
>>> target-ppc/mmu-hash64.c |2 +-
>>> 3 files changed, 18
On Sun, 2016-09-04 at 18:00 +0100, Alex Bennée wrote:
> >
> > > We must provide a guarantee that no other processor can see the old
> > > translation when the tlb invalidation sequence completes. With the
> > > current lazy TLB flush, we already delay the invalidation until
> > > we hit that synch
Hi,
A while ago, Dave Airlie started implementing a seperate thread for
virgl (although it didn't work for me and was very much in wip
state). I fixed the code so I could test it, and moved it to use qemu
iothread/aio loops, inspired by the dataplane code in the virtio block
devices.
The benchmar
From: Dave Airlie
This is preparatory work for introducing a thread.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu-3d.c | 68 +++---
include/hw/virtio/virtio-gpu.h | 20 +
2 files changed, 71 insertions(+), 17 deletions(-)
diff
Not all display backends support various opengl contexts in
multi-threads. Add a field to declare it. For now, only spice/egl has
been tested successfully.
Signed-off-by: Marc-André Lureau
---
ui/console.c | 6 ++
ui/spice-display.c | 1 +
include/ui/console.h | 3 ++-
3 files chan
virtio-gpu does a set-scanout at each frame (it might be a driver
regression). qemu_console_resize() recreate a surface even if the size
didn't change, and this shows up in profiling reports because the
surface is cleared. With this patch, I get a +15-20% glmark2
improvement.
Signed-off-by: Marc-A
EGL API binding is per-thread. Make sure an API is bound when creating a
context, creating one from a new thread will not fail for missing API.
virgl requires opengl, and qemu has no complete gles support so far it
seems, so take it by default.
While at it, fix indentation to please check-patch.
Create a thread-specific opengl context for the renderer. This avoids
having to synchronize a single context between the rendering and display
threads.
The display must support calling gl_ctx* functions from a different
thread later on, return an error if it doesn't.
Signed-off-by: Marc-André Lur
For now, this just links the device with an iothread, but doesn't make
use of it yet. (the following commits will create context for it,
messages, and then dispatch virtio queues to run the renderer)
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu-pci.c| 2 ++
hw/display/virtio-gp
There is no much point in storing the vq when it can be accessed easily.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu.c| 7 ---
include/hw/virtio/virtio-gpu.h | 1 -
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/display/virtio-gpu.c b/hw/display/virt
From: Dave Airlie
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu-3d.c | 6 ++
hw/display/virtio-gpu.c| 8
include/hw/virtio/virtio-gpu.h | 2 ++
3 files changed, 16 insertions(+)
diff --git a/hw/display/virtio-gpu-3d.c b/hw/display/virtio-gpu-3d.c
index 036
This will allow to schedule the bh from the iothread, and with the
bitmaps, it will batch the cursors modifications.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu.c| 50 +++---
include/hw/virtio/virtio-gpu.h | 3 +++
2 files changed, 50 i
Use a helper to call virtio notify. If the dataplane is running,
set the notify bit and schedule the bh.
(note: this could eventually be good in non-dataplane too)
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
Each thread may have its own context (having the same context shared
with several threads is wrong).
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu-3d.c | 9 -
hw/display/virtio-gpu.c| 2 +-
ui/console.c | 5 +++--
ui/gtk-egl.c | 9 ++--
Signed-off-by: Marc-André Lureau
---
hw/block/dataplane/virtio-blk.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c
index 704a763..dce2675 100644
--- a/hw/block/dataplane/virtio-
Add a thread "data-plane" structure and callback functions. This is
inspired by virtio-blk data-plane.
The following commits will use and start the data-plane.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu-3d.c | 103 +
hw/display/virtio-
Signed-off-by: Marc-André Lureau
---
include/qemu/bitmap.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/include/qemu/bitmap.h b/include/qemu/bitmap.h
index ec5146f..33bb294 100644
--- a/include/qemu/bitmap.h
+++ b/include/qemu/bitmap.h
@@ -223,6 +223,29 @@ static i
Let's not use a timer but rather an additional thread to wait for sync.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu-3d.c | 22 +++---
hw/display/virtio-gpu.c| 2 +-
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/hw/display/virtio-gpu-3d.c b/hw
If the virtqueues is waiting to be processed, make sure to wake it up.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
index 45fc018..a37d5f2 100644
--- a/hw/di
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu-3d.c | 44 +---
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/hw/display/virtio-gpu-3d.c b/hw/display/virtio-gpu-3d.c
index 6dd44d6..728c940 100644
--- a/hw/display/virtio-gpu-3d.c
Use aio thread context to dispatch the queues.
This code has been written based on virtio-blk data-plane setup.
Signed-off-by: Marc-André Lureau
---
hw/display/virtio-gpu.c| 138 -
include/hw/virtio/virtio-gpu.h | 1 +
2 files changed, 137 inser
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH 00/18] virgl: use a seperate rendering thread
Type: series
Message-id: 20160904222039.11460-1-marcandre.lur...@redhat.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Subject: [Qemu-devel] [PATCH 00/18] virgl: use a seperate rendering thread
Type: series
Message-id: 20160904222039.11460-1-mar
On Sun, 2016-09-04 at 18:00 +0100, Alex Bennée wrote:
> When is the synchronisation point? On ARM we end the basic block on
> system instructions that mess with the cache. As a result the flush
> is done as soon as we exit the run loop on the next instruction.
Talking o this... Nikunj, I notice,
Hi Michael,
On 2016/9/3 6:52, Michael S. Tsirkin wrote:
> On Fri, Sep 02, 2016 at 10:22:55AM +0800, Longpeng(Mike) wrote:
>> From: "Longpeng(Mike)"
>>
>> Some software algorithms are based on the hardware's cache info, for example,
>> for x86 linux kernel, when cpu1 want to wakeup a task on cpu2
On 2016年08月30日 11:06, Jason Wang wrote:
Signed-off-by: Jason Wang
---
include/standard-headers/linux/input-event-codes.h | 32 +
include/standard-headers/linux/input.h | 1 +
include/standard-headers/linux/virtio_config.h | 10 +-
include/standard-head
On Mon, Sep 05, 2016 at 09:24:37AM +0800, Wei Xu wrote:
> Looks this patch includes quite a few misc changes from upstream, it's a bit
> confused to find out which one is related to virtio/vhost dmar support,
> while the upstream header shows a separate commit for new IOTLB api, is it
> possible to
On Fri, Sep 02, 2016 at 09:09:48AM +0200, Laurent Vivier wrote:
>
>
> On 02/09/2016 04:37, David Gibson wrote:
> > On Thu, Sep 01, 2016 at 10:10:49AM +0200, Laurent Vivier wrote:
> >> Since kernel v4.0, linux uses H_CHANGE_LOGICAL_LAN_MAC to change lively
> >> the MAC address of an ibmveth interf
On 2016/9/3 5:46, Wei Huang wrote:
> Current QEMU will stall guest VM booting under ACPI mode when vcpu count
> is >= 12. Analyzing the booting log, it turns out that DSDT table can't
> be loaded correctly due to "Invalid character(s) in name (0x62303043),
> repaired: [C00*]". This is because exi
Third part of scratch.armv7l.0.tar.gz.
** Attachment added: "scratch.armv7l.0.tar.gz.aa.aa"
https://bugs.launchpad.net/qemu/+bug/1617929/+attachment/4734550/+files/scratch.armv7l.0.tar.gz.aa.aa
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscri
On Sat, Sep 03, 2016 at 11:57:49AM +0200, Thomas Huth wrote:
> Since some of the machines that we support in QEMU sometimes get
> broken by other changes, and it then takes a while 'till somebody
> notices the breakage, it would be nice to get some more automatic
> test coverage for various machine
On Tue, Aug 30, 2016 at 09:23:40AM +0200, Cédric Le Goater wrote:
> On 08/30/2016 08:15 AM, Benjamin Herrenschmidt wrote:
> > On Mon, 2016-08-29 at 10:30 -0400, David Gibson wrote:
> >>
> >> Possibly. In fact, I'm planning to eliminate cpu->cpu_dt_id at some
> >> point, in favour of having the mac
Dear Peter.
Thank you for the update.
Please find the attached full chroot environment that I
used(scratch.armv7l.0.tar.gz, split three parts).
You could try make build with below steps;
$ sudo su
$ echo -1 > /proc/sys/fs/binfmt_misc/arm
$ echo
':arm:M::\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00
On 2016年08月30日 11:06, Jason Wang wrote:
@@ -1587,6 +1595,11 @@ static void virtio_pci_device_plugged(DeviceState *d,
Error **errp)
}
if (legacy) {
+if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
+error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was suppor
On Tue, Aug 30, 2016 at 11:06:50AM +0800, Jason Wang wrote:
> @@ -1587,6 +1595,11 @@ static void virtio_pci_device_plugged(DeviceState *d,
> Error **errp)
> }
>
> if (legacy) {
> +if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
> +error_setg(errp, "VIR
On Mon, 08/29 15:30, Max Reitz wrote:
> On 17.08.2016 09:20, Fam Zheng wrote:
> > Use a hash table to keep record of all loaded modules, and return early
> > if the requested module is already loaded.
> >
> > Signed-off-by: Fam Zheng
> > ---
> > util/module.c | 19 +--
> > 1 file
On Fri, Sep 02, 2016 at 01:08:29PM +0200, Paolo Bonzini wrote:
>
>
> On 25/08/2016 12:14, Chao Peng wrote:
> > This patchset is trying to optimize guest startup time by disabling
> > or simplifying some features in QEMU. The version 1 can be found at:
> > https://lists.nongnu.org/archive/html/qem
v4: Remove unused variable in patch 1 and unwanted warning in patch 2. [Max]
v3: Fix typo in copyright header. [Max]
Fix pre-existing type casting. [Max]
v2: Rebase on top of Max's block-next tree, which has Colin's patches to
dynamically load block modules.
Two more tweaks to the mod
dmg.o was moved to block-obj-m in 5505e8b76 to become a separate module,
so that its reference to libbz2, since 6b383c08c, doesn't add an extra
library to the main executable.
Until recently, commit 06e60f70a (blockdev: Add dynamic module loading
for block drivers) moved it back to block-obj-y to
Signed-off-by: Fam Zheng
---
scripts/modules/module_block.py | 7 ---
1 file changed, 7 deletions(-)
diff --git a/scripts/modules/module_block.py b/scripts/modules/module_block.py
index db4fb54..3f73007 100644
--- a/scripts/modules/module_block.py
+++ b/scripts/modules/module_block.py
@@ -37
Use a hash table to keep record of all loaded modules, and return early
if the requested module is already loaded.
Signed-off-by: Fam Zheng
---
util/module.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/util/module.c b/util/module.c
index a5f7fbd..c9097
On Wed, Aug 31, 2016 at 06:34:10PM +0200, Cédric Le Goater wrote:
> This is is an abstraction of a POWER8 chip which is a set of cores
> plus other 'units', like the pervasive unit, the interrupt controller,
> the memory controller, the on-chip microcontroller, etc. The whole can
> be seen as a soc
On Wed, Aug 31, 2016 at 06:34:09PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> The goal is to emulate a PowerNV system at the level of the skiboot
> firmware, which loads the OS and provides some runtime services. Power
> Systems have a lower firmware (HostBoot) that does lo
On Tue, 08/09 10:15, Fam Zheng wrote:
> It's a variation of our existing centos6, plus two more lines to
> downgrade glib2 to version 2.22 which we download from vault.centos.org.
>
> Suggested-by: Paolo Bonzini
> Signed-off-by: Fam Zheng
> ---
> tests/docker/dockerfiles/min-glib.docker | 8 +++
On Wed, Aug 31, 2016 at 06:34:11PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> XSCOM is an interface to a sideband bus provided by the POWER8 chip
> pervasive unit, which gives access to a number of facilities in the
> chip that are needed by the OPAL firmware and to a lesse
** Description changed:
When running multiple VMs with GPU passthrugh, both VMs will crash
unless all virtual disks are on the same physical volume as root, likely
on all X58 chipset motherboards. I've tested with 3.
Expected Behavior: No Crash
- Result: Both VMs GPU drivers fail and
On Wed, Aug 31, 2016 at 06:34:11PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> XSCOM is an interface to a sideband bus provided by the POWER8 chip
> pervasive unit, which gives access to a number of facilities in the
> chip that are needed by the OPAL firmware and to a lesse
On Wed, Aug 31, 2016 at 06:34:15PM +0200, Cédric Le Goater wrote:
> On PowerNV, CPU ids start at 0x8 or 0x20, we don't have a CPU 0
> anymore. So let's use the first_cpu index to initialize the monitor.
>
> Signed-off-by: Cédric Le Goater
So we need a patch like this - amongst other fixes - in o
On Wed, Aug 31, 2016 at 06:34:12PM +0200, Cédric Le Goater wrote:
> This will be used to build real HW ids for the cores and enforce some
> limits on the available cores per chip.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/ppc/pnv.c | 27 +++
> include/hw/ppc/
On Wed, Aug 31, 2016 at 06:34:14PM +0200, Cédric Le Goater wrote:
> Now that we are using real HW ids for the cores in PowerNV chips, we
> can route the XSCOM accesses to them. We just need to attach a
> XScomDevice to each core with the associated ranges in the XSCOM
> address space.
>
> To start
On Wed, Aug 31, 2016 at 06:34:13PM +0200, Cédric Le Goater wrote:
> This is largy inspired by sPAPRCPUCore with some simplification, no
> hotplug for instance. But the differences are small and the objects
> could possibly be merged.
>
> A set of PnvCore objects is added to the PnvChip and the dev
This is a name replacement to prepare ground for other SoCs.
Let's also remove the AST2400_SMC_BASE definition from the address
space mappings, as it is not used. This controller was removed from
the Aspeed SoC AST2500, so this provides us a better common base for
the address space mapping on both
Let's prepare for new Aspeed SoCs and rename the ast2400 file to a
more generic one. There are no changes in the code apart from the
header file include.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Reviewed-by: Peter Maydell
---
hw/arm/Makefile.objs | 2 +-
The AST2500 SoC being very close to the AST2400 SoC, the goal of the
changes below is to modify the existing platform palmetto-bmc and the
AST2400 SoC to take into account the small differences and avoid code
duplication. This is mostly inspired by the realview and the rpi2
platforms.
First patche
We plan to add more Aspeed boards to this file. There are no changes
in the code.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Reviewed-by: Peter Maydell
---
hw/arm/Makefile.objs| 2 +-
hw/arm/{palmetto-bmc.c => aspeed.c} | 0
2 files changed, 1 insertion(+), 1 d
Let's define an object class for each Aspeed SoC we support. A
AspeedSoCInfo struct gathers the SoC specifications which can later be
used by an instance of the class or by a board using the SoC.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
---
Changes since v3:
- use '-1' for
This is mostly a name replacement to prepare ground for other SoCs
specificities. It also adds a TypeInfo struct for the palmetto-bmc
board with a custom initialization for the same reason.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Reviewed-by: Peter Maydell
---
hw/arm/aspeed
aspeed_board_init() now uses a board identifier to customize some values
specific to the board.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Reviewed-by: Peter Maydell
---
Changes since v3:
- added trailing comma to enum
Changes since v2:
- removed silicon-rev and cpu-mod
The ast2500 eval board has a hardware strapping register value of
0xF100C2E6 which we use for a definition of AST2500_EVB_HW_STRAP1
below.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Reviewed-by: Peter Maydell
---
Changes since v3:
- fixed trailing comma.
hw/arm/aspeed.c |
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Reviewed-by: Peter Maydell
---
hw/arm/aspeed.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 2af9fe934441..9013d35a674c 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -145,7 +145,6 @@
Based on previous work done by Andrew Jeffery .
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Reviewed-by: Peter Maydell
---
Changes since v3:
- added brackets around macro parameters
- fixed trailing comma in enum
Changes since v2:
- more precise definitions of the hw-st
>> +static void ppc_powernv_reset(void)
>> +{
>> +MachineState *machine = MACHINE(qdev_get_machine());
>> +PnvMachineState *pnv = POWERNV_MACHINE(machine);
>> +void *fdt;
>> +
>> +pnv->fdt_addr = FDT_ADDR;
>
> Not sure there's any point to pnv->fdt_addr, since it will always have
>
This gives some explanation behind the magic number 0x120CE416.
Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Reviewed-by: Peter Maydell
---
Changes since v3:
- added brackets around macro parameters
Changes since v2:
- more precise definitions of the hw-strap1 register
-
On Fri, Sep 02, 2016 at 09:13:01AM -0600, Alex Williamson wrote:
> Maybe memory_region_register_iommu_notifier() could take an
> IOMMUAccessFlags argument (filter) that is passed to the notify_started
> callback. If a notifier client only cares about IOMMU_NONE
> (invalidations), intel-iommu could
On 2016年08月30日 11:06, Jason Wang wrote:
To avoid duplicated name and ease debugging.
Cc: Michael S. Tsirkin
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Acked-by: Peter Xu
Signed-off-by: Jason Wang
---
hw/i386/intel_iommu.c | 4 +++-
1 file changed, 3 insertions(+), 1 del
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