On Thu, 05/26 14:50, Fam Zheng wrote:
> On Tue, 05/24 16:30, Peter Lieven wrote:
> > in a read-modify-write cycle a small request might cause
> > head and tail to fall into the same aligned block. Currently
> > QEMU reads the same block twice in this case which is
> > not necessary.
> >
> > Signed
On 25/05/2016 22:17, Jianjun Duan wrote:
>
>
> On 05/25/2016 12:22 PM, Paolo Bonzini wrote:
>>> 1 QTAILQ should only be accessed using the interfaces defined in
>>> queue.h. Its structs should not be directly used. So I created
>>> interfaces in queue.h to query about its layout. If the impleme
Hello,respected developers of Qemu. I am new to Qemu,and I have some questions
below.Any help would be highly appreciated!
question 1: How can I add a kind of new device support in Qemu and What is the
steps to do so?(For example,if Qemu can not virtualize the RAM ,what should I
do to make Qemu
> How can I add a kind of new device support in Qemu and What is the steps
to do so?
https://github.com/rafilia/qemu_example_virtual_pcidev
--
Dongli Zhang (张东立)
finallyjustice.github.io
On 26/05/2016 09:10, Fam Zheng wrote:
>
> diff --git a/block/io.c b/block/io.c
> index d480097..a6523cf 100644
> --- a/block/io.c
> +++ b/block/io.c
> @@ -1435,8 +1435,10 @@ int coroutine_fn bdrv_co_pwritev(BlockDriverState *bs,
> * than one aligned block.
> */
> if
On 26/05/2016 08:15, Fam Zheng wrote:
> The rationale is similar to the above mode sense response interception:
> this is practically the only channel to communicate restraints from
> elsewhere such as host and block driver.
>
> The scsi bus we attach onto can have a larger max xfer len than wha
Now that KVM_CAP_MAX_VCPU_ID is in Linux 4.6, we can use it to support
topologies that generate vCPU ids >= KVM_MAX_VCPUS. This is especially
useful for PPC targets when the guest has fewer threads per core than
the host.
The first patch was already posted and accepted by David last month, but
sin
Signed-off-by: Greg Kurz
---
include/standard-headers/linux/pci_regs.h | 20 +++-
include/standard-headers/linux/virtio_config.h |2 ++
linux-headers/asm-arm/unistd.h |2 ++
linux-headers/asm-arm64/unistd.h |3 +++
linux-headers/asm
As stated in linux/Documentation/virtual/kvm/api.txt:
The maximum possible value for max_vcpu_id can be retrieved using the
KVM_CAP_MAX_VCPU_ID of the KVM_CHECK_EXTENSION ioctl() at run-time.
If the KVM_CAP_MAX_VCPU_ID does not exist, you should assume that
max_vcpu_id is the same as the value re
The KVM API restricts vcpu ids to be < KVM_CAP_MAX_VCPUS. On PowerPC
targets, depending on the number of threads per core in the host and
in the guest, some topologies do generate higher vcpu ids actually.
When this happens, QEMU bails out with the following error:
kvm_init_vcpu failed: Invalid ar
On Thu, 05/26 14:50, m13767433329 wrote:
> question 3:how can I develop a kind of software like Qemu which can run on
> Windows?
QEMU _can_ run on Windows:
https://qemu.weilnetz.de/
Fam
On Thu, 05/26 14:50, m13767433329 wrote:
> question 2: What does the architecture of Qemu like ?
To begin with, this is a nice overview:
http://blog.vmsplice.net/2011/03/qemu-internals-big-picture-overview.html
Fam
On Thu, 05/26 09:55, Paolo Bonzini wrote:
>
>
> On 26/05/2016 09:10, Fam Zheng wrote:
> >
> > diff --git a/block/io.c b/block/io.c
> > index d480097..a6523cf 100644
> > --- a/block/io.c
> > +++ b/block/io.c
> > @@ -1435,8 +1435,10 @@ int coroutine_fn bdrv_co_pwritev(BlockDriverState
> > *bs,
>
This removes some more cases where we unnecessarily go through
ram_addr_t. Now that MemoryRegions have a RAMBlock pointer, it is
possible to keep reasoning in terms of MemoryRegion+offset everywhere,
except when managing dirty bitmaps and TCG TLB entries. ram_addr.h
is now included only by cputlb
Move the old qemu_ram_addr_from_host to memory_region_from_host and
make it return an offset within the region. For qemu_ram_addr_from_host
return the ram_addr_t directly, similar to what it was before
commit 1b5ec23 ("memory: return MemoryRegion from qemu_ram_addr_from_host",
2013-07-04).
Signed
Of the two callers, one does not use it, and the other can compute
it itself based on the other output argument (offset) and the RAMBlock.
Signed-off-by: Paolo Bonzini
---
exec.c| 13 ++---
include/exec/cpu-common.h | 2 +-
migration/postcopy-ram.c | 3 +--
3 files
Let users of qemu_get_ram_ptr and qemu_ram_ptr_length pass in an
address that is relative to the MemoryRegion. This basically means
what address_space_translate returns.
Because the semantics of the second parameter change, rename the
function to qemu_map_ram_ptr.
Signed-off-by: Paolo Bonzini
-
Remove direct uses of ram_addr_t and optimize memory_region_{get,set}_fd
now that a MemoryRegion knows its RAMBlock directly.
Signed-off-by: Paolo Bonzini
---
exec.c | 34 --
hw/misc/ivshmem.c | 5 ++---
hw/virtio/vhost-user.c | 15 +++
On Wed, 05/25 21:48, Eric Blake wrote:
> From: "Denis V. Lunev"
>
> We should split requests even if they are less than write_zeroes_alignment.
> For example we can have the following request:
> offset 62k
> size 4k
> write_zeroes_alignment 64k
> The original code sent 1 request covering
Thanks Alex.
I'll consider all the nits and fix those in next version of patch.
More below:
On 5/26/2016 4:09 AM, Alex Williamson wrote:
> On Wed, 25 May 2016 01:28:15 +0530
> Kirti Wankhede wrote:
>
...
>> +
>> +config MDEV
>> +tristate "Mediated device driver framework"
>> +depends
On Wed, 25 May 2016, Paolo Bonzini wrote:
> > From: "Anthony PERARD"
> > To: "Paul Durrant"
> > Cc: qemu-devel@nongnu.org, xen-de...@lists.xenproject.org, "Stefano
> > Stabellini" , "Paolo
> > Bonzini"
> > Sent: Wednesday, May 25, 2016 5:52:32 PM
> > Subject: Re: [PATCH v3] xen-hvm: ignore back
On 26/05/2016 10:30, Fam Zheng wrote:
>> >
>> > This doesn't look too wrong... Should the right sequence of events be
>> > head/after_head or head/after_tail? It's probably simplest to just emit
>> > all four events.
> I've no idea. (That's why I leaned towards fixing the test case).
Well, fi
On Wed, May 25, 2016 at 11:13:24PM -0600, Chris Friesen wrote:
[...]
> However, if I explicitly specify a custom CPU model of "qemu64" the
> instance refuses to boot and I get a log saying:
[Not a direct answer to the exact issue you're facing, but a related
issue that is being investigated pres
print expected file name if it doesn't exists if
verbose mode is enabled*. It helps to avoid running
bios-tables-test under debugger to figure out missing
file name.
*)
verbose mode is enabled if "V" env. variable is set
Signed-off-by: Igor Mammedov
---
v2: replace 'for' loop with more readble
On Mon, 23 May 2016 22:49:46 +0530
Amit Shah wrote:
> From: Greg Kurz
>
> QEMU has currently two ways to prevent migration to occur:
> - migration blocker when it depends on runtime state
> - VMStateDescription.unmigratable when migration is not supported at all
>
> This patch gathers all the
On Mon, 23 May 2016 22:49:47 +0530
Amit Shah wrote:
> From: Greg Kurz
>
> We currently have an error path during migration that can cause
> the source QEMU to abort:
>
> migration_thread()
> migration_completion()
> runstate_is_running() > true if guest is running
> b
Hello.
In my diploma project I'm trying to add VMX to qemu. It is first vmx
incarnation, without ept, unrestricted guest and other improvements.
It seems working in some way. Virtual Box can execute few hundreds of
instructions until crash, but it's tricky for me to build it completely to add
s
On 04/11/2016 11:56 AM, Changlong Xie wrote:
Changelog
v4:
1. Rebased to the lastest code
v3:
1. Addressed on David's commets, fix a bug
v2:
1. Rebased to the lastest code
2. Addressed on Eric's comments, fixed coding style
Wen Congyang (1):
Introduce "xen-load-devices-state"
migration/sav
On 26/05/2016 11:55, Dmitry Poletaev wrote:
> kvm_mmu_page_fault goes to nonpaging_page_fault, which don't find page in
> cache and calls nonpaging_map. nonpaging_map exits after critical section
> before out_unlock label. For me reaction is normal and looks the same on both
> platforms, but I
On 12/05/2016 05:48, Bharata B Rao wrote:
> CPUState *cpu gets added to the cpus list during cpu_exec_init(). It
> should be removed from cpu_exec_exit().
>
> cpu_exec_exit() is called from generic CPU::instance_finalize and some
> archs like PowerPC call it from CPU unrealizefn. So ensure that
Fam Zheng writes:
> docker.py is added with a number of useful subcommands to manager docker
> images and instances for QEMU docker testing. Subcommands are:
>
> run: A wrapper of "docker run" (or "sudo -n docker run" if necessary),
> which takes care of killing and removing the running containe
On 12/05/2016 05:48, Bharata B Rao wrote:
> @@ -1531,6 +1563,9 @@ static void tcg_exec_all(void)
> break;
> }
> } else if (cpu->stop || cpu->stopped) {
> +if (cpu->unplug) {
This "if" is unnecessary. next_cpu is not used anymore after the
"brea
On 12/05/2016 05:48, Bharata B Rao wrote:
> This sync API will be used by the CPU hotplug code to wait for the CPU to
> completely get removed before flagging the failure to the device_add
> command.
>
> Sync version of this call is needed to correctly recover from CPU
> realization failures whe
On 12/05/2016 05:48, Bharata B Rao wrote:
> cpu_exec_init() does vmstate_register for the CPU device. This needs to be
> undone from cpu_exec_exit(). This change is needed to support CPU hot
> removal.
>
> Signed-off-by: Bharata B Rao
> Reviewed-by: Thomas Huth
> Reviewed-by: David Gibson
> -
On Wed, May 25, 2016 at 23:13:24 -0600, Chris Friesen wrote:
> Hi,
>
> If I don't specify a virtual CPU model, it appears to give me a "qemu64" CPU,
> and /proc/cpuinfo in the guest instance looks something like this:
>
> processor 0
> vendor_id GenuineIntel
> cpu family 6
> model 6
> model name
On 25/05/16 15:34, Jeff Epler wrote:
> Hi. Before I take the time to prepare a detailed bug report, I wanted to
> ask whether I'm doing something that is expected to work, or expected not
> to work.
>
> I am a developer of the LinuxCNC, Free and Open Source software for control
> of milling machin
On Thu, May 26, 2016 at 12:19:05PM +0200, Paolo Bonzini wrote:
>
>
> On 12/05/2016 05:48, Bharata B Rao wrote:
> > @@ -1531,6 +1563,9 @@ static void tcg_exec_all(void)
> > break;
> > }
> > } else if (cpu->stop || cpu->stopped) {
> > +if (cpu->unp
On 26/05/2016 12:47, Bharata B Rao wrote:
>>> > > } else if (cpu->stop || cpu->stopped) {
>>> > > +if (cpu->unplug) {
>> >
>> > This "if" is unnecessary. next_cpu is not used anymore after the
>> > "break", so the store is dead.
> next_cpu is a global here. Won't tcg_exec_a
On 05/04/16 18:32, Alex Bennée wrote:
> diff --git a/cpus.c b/cpus.c
> index e118fdf..46732a5 100644
> --- a/cpus.c
> +++ b/cpus.c
(snip)
> @@ -1109,7 +1108,7 @@ static void *qemu_dummy_cpu_thread_fn(void *arg)
> #endif
> }
>
> -static void tcg_exec_all(void);
> +static int tcg_cpu_exec(CPUStat
On 26/05/2016 12:42, Sergey Fedorov wrote:
> I'm afraid even our recent efforts in
> multi-threaded TCG won't change the situation. The problem is that it
> would require to translate somehow ARM's exclusive access monitor to x86
> model.
>
The cmpxchg-based variant would work. It doesn't impl
This is a fixup patch intended to be squashed into the "linux-user:
Provide safe_syscall for fixing races between signalsand syscalls"
patch.
Fix compilation on non-x86-64 hosts by:
* only adding linux-user/host/$ARCH to the include path if it exists
* providing a fallback hostdep.h header in li
On 25 May 2016 at 17:33, Peter Maydell wrote:
> Looks like the C compiler doesn't like nonexistent -I directories.
> I thought I'd tested "does this still build without the host-specific
> .S file", but I guess I must have had the directory floating around
> in my working tree.
>
> I'll sort out a
Hi
On Thu, May 26, 2016 at 10:49 AM, Paolo Bonzini wrote:
> Remove direct uses of ram_addr_t and optimize memory_region_{get,set}_fd
> now that a MemoryRegion knows its RAMBlock directly.
>
> Signed-off-by: Paolo Bonzini
> ---
> exec.c | 34 --
>
On 04/27/2016 04:05 AM, Daniel P. Berrange wrote:
> Currently if an application initiates an outgoing migration,
> it may or may not, get an error reported back on failure. If
> the error occurs synchronously to the 'migrate' command
> execution, the client app will see the error message. This
> is
On 25 May 2016 at 17:37, Sergey Fedorov wrote:
> On 16/05/16 17:36, Sergey Fedorov wrote:
>> On 16/05/16 16:49, Richard Henderson wrote:
>>> On 05/16/2016 06:13 AM, Sergey Fedorov wrote:
It is not safe to make a direct jump to a TB spanning two pages in
system emulation because the mappi
On 26/05/16 14:21, Paolo Bonzini wrote:
>
> On 26/05/2016 12:42, Sergey Fedorov wrote:
>> I'm afraid even our recent efforts in
>> multi-threaded TCG won't change the situation. The problem is that it
>> would require to translate somehow ARM's exclusive access monitor to x86
>> model.
>>
> The cmp
Sergey Fedorov writes:
> On 05/04/16 18:32, Alex Bennée wrote:
>> diff --git a/cpus.c b/cpus.c
>> index e118fdf..46732a5 100644
>> --- a/cpus.c
>> +++ b/cpus.c
> (snip)
>> @@ -1109,7 +1108,7 @@ static void *qemu_dummy_cpu_thread_fn(void *arg)
>> #endif
>> }
>>
>> -static void tcg_exec_all(void
We're using Ubuntu, and we manually patched the version 2.3 with the fix
referenced. It will be soon deployed and I'll see if that fixes the
problem.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1585
Hi
On Thu, May 26, 2016 at 10:49 AM, Paolo Bonzini wrote:
> Of the two callers, one does not use it, and the other can compute
> it itself based on the other output argument (offset) and the RAMBlock.
>
> Signed-off-by: Paolo Bonzini
> ---
> exec.c| 13 ++---
> inclu
Hi
On Thu, May 26, 2016 at 10:49 AM, Paolo Bonzini wrote:
> Move the old qemu_ram_addr_from_host to memory_region_from_host and
> make it return an offset within the region. For qemu_ram_addr_from_host
> return the ram_addr_t directly, similar to what it was before
> commit 1b5ec23 ("memory: ret
On 25 May 2016 at 23:38, Andreas Färber wrote:
> Hello Peter,
>
> This is my QOM (devices) patch queue. Please pull.
>
> I've needed to build-fix it twice by now, so if I fixed the #includes wrongly
> please pick it up as patch and tweak it or apply a cleanup on top.
>
> Thanks,
> Andreas
>
> P.S.
bdrv_replace_in_backing_chain() sometimes does what is advertised (if
the new node does not have a backing file yet and if it hasn't been in
the same backing chain already), but this is not what the mirror block
job (the sole user of that function) actually needs. In fact, it only
needs this behavi
Currently, we are trying to move the backing BDS from the source to the
target in bdrv_replace_in_backing_chain(). However, the conditions used
to decide when to move the backing BDS from source to target are not
really correct.
Basically, we do not have to set the target's backing BDS when doing
Signed-off-by: Max Reitz
---
tests/qemu-iotests/155 | 218 +
tests/qemu-iotests/155.out | 5 ++
tests/qemu-iotests/group | 1 +
3 files changed, 224 insertions(+)
create mode 100755 tests/qemu-iotests/155
create mode 100644 tests/qemu-iotest
On 05/26/2016 06:48 AM, Eric Blake wrote:
is_zero_cluster() and is_zero_cluster_top_locked() are used only
by qcow2_co_write_zeroes(). The former is too broad (we don't
care if the sectors we are about to overwrite are non-zero, only
that all other sectors in the cluster are zero), so it needs t
On Thu, 26 May 2016 14:33:39 +0530
Kirti Wankhede wrote:
> Thanks Alex.
>
> I'll consider all the nits and fix those in next version of patch.
>
> More below:
>
> On 5/26/2016 4:09 AM, Alex Williamson wrote:
> > On Wed, 25 May 2016 01:28:15 +0530
> > Kirti Wankhede wrote:
> >
>
> ...
>
>
On 25 May 2016 at 18:39, Kevin Wolf wrote:
> The following changes since commit 287db79df8af8e31f18e262feb5e05103a09e4d4:
>
> Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into
> staging (2016-05-24 13:06:33 +0100)
>
> are available in the git repository at:
>
>
> git:
Hi,
I had a an set of scripts for setting up and running executable
binaries in a $arch-linux-user powered rootfs. However it has been a
while since I last used them and there was various breakage which
spurred me on to a better way. As Fam has been working with Docker
containers for building I in
Together with some changes to the docker script you can now build an
arbitrary architecture of Debian using debootstrap. To achieve this I
introduce the concept of a HOST_CMD in the docker config file. While
copying the file into workspace the HOST_CMD is run in the docker build
context. This allow
When passed the name of a qemu-$arch binary we copy it and any linked
libraries into the docker build context. These can then be included by a
dockerfile with the line:
# Copy all of context into container
ADD . /
Signed-off-by: Alex Bennée
---
tests/docker/docker.py | 58 ++
If you try to gic-version=host with TCG on a KVM aarch64 host,
qemu segfaults, since host requires KVM APIs.
Explicitly reject gic-version=host if KVM is not enabled
https://bugzilla.redhat.com/show_bug.cgi?id=1339977
Signed-off-by: Cole Robinson
---
hw/arm/virt.c | 6 +-
1 file changed, 5
On 05/26/2016 07:41 AM, Denis V. Lunev wrote:
> On 05/26/2016 06:48 AM, Eric Blake wrote:
>> is_zero_cluster() and is_zero_cluster_top_locked() are used only
>> by qcow2_co_write_zeroes(). The former is too broad (we don't
>> care if the sectors we are about to overwrite are non-zero, only
>> that
Treat non-secure accesses to registers and bits in registers of secure
interrupts as RAZ/WI.
Signed-off-by: Jens Wiklander
---
hw/intc/arm_gic.c | 68 ++-
1 file changed, 62 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/int
On Thu, May 26, 2016 at 10:31:25AM -0400, Cole Robinson wrote:
> If you try to gic-version=host with TCG on a KVM aarch64 host,
> qemu segfaults, since host requires KVM APIs.
>
> Explicitly reject gic-version=host if KVM is not enabled
>
> https://bugzilla.redhat.com/show_bug.cgi?id=1339977
> Si
On 26 May 2016 at 15:46, Richard W.M. Jones wrote:
> The problem with this is if I'm using TCG fallback mode, how
> can I specify the right gic-version? ie:
>
> -M virt,gic-version=host,accel=kvm:tcg
>
> Only qemu knows if KVM is going to be enabled.
>
> The same problem happens with '-cpu host
Wire up the MMIO functions exposed by the distributor and the
redistributor into MMIO regions exposed by the GICv3 device.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gi
Implement the registers in the GICv3 CPU interface which generate
new SGI interrupts.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_cpuif.c | 125 +
hw/intc/arm_gicv3_redist.c | 40 +++
hw/intc/gicv3_internal.h | 1 +
trace-event
Implement the code which updates the GIC state when an interrupt
input into the GIC is asserted.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3.c| 20 +++-
hw/intc/arm_gicv3_dist.c | 21 +
hw/intc/arm_gicv3_redist.c | 21 +
hw
From: Pavel Fedin
This temporary patch adds kernel API definitions. Use proper header update
procedure after these features are released.
FIXME: not-for-upstream
Signed-off-by: Pavel Fedin
---
linux-headers/asm-arm64/kvm.h | 17 +
1 file changed, 13 insertions(+), 4 deletions(
This series implements emulation of the GICv3 interrupt controller.
It is based to some extent on previous patches from Shlomo and
Pavel, but the bulk of it has turned out to be new code. (The
combination of changing the underlying data structures, adding
support for TrustZone and implementing prop
On 05/26/2016 06:48 AM, Eric Blake wrote:
is_zero_cluster() and is_zero_cluster_top_locked() are used only
by qcow2_co_write_zeroes(). The former is too broad (we don't
care if the sectors we are about to overwrite are non-zero, only
that all other sectors in the cluster are zero), so it needs t
From: Shlomo Pongratz
Implement the distributor registers of a GICv3.
Signed-off-by: Shlomo Pongratz
[PMM: significantly overhauled/rewritten:
* use the new bitmap data structures
* restructure register read/write to handle different width accesses
natively, since almost all registers are
On 05/26/2016 12:12 AM, Amit Shah wrote:
> From: "Daniel P. Berrange"
>
> Define two new migration parameters to be used with TLS encryption.
> The 'tls-creds' parameter provides the ID of an instance of the
> 'tls-creds' object type, or rather a subclass such as 'tls-creds-x509'.
> Providing the
Implement the gicv3_cpuif_update() function which deals with correctly
asserting IRQ and FIQ based on the current running priority of the CPU,
the priority of the highest priority pending interrupt and the CPU's
current exception level and security state.
Signed-off-by: Peter Maydell
---
hw/intc
On 05/26/2016 04:41 AM, Jiri Denemark wrote:
The qemu64 CPU model contains svm and thus libvirt will always consider
it incompatible with any Intel CPUs (which have vmx instead of svm). On
the other hand, QEMU by default ignores features that are missing in the
host CPU and has no problem using
On 05/26/2016 12:12 AM, Amit Shah wrote:
> From: "Daniel P. Berrange"
>
> Currently if an application initiates an outgoing migration,
> it may or may not, get an error reported back on failure. If
> the error occurs synchronously to the 'migrate' command
> execution, the client app will see the
On Thu, May 26, 2016 at 03:53:54PM +0100, Peter Maydell wrote:
> On 26 May 2016 at 15:46, Richard W.M. Jones wrote:
> > The problem with this is if I'm using TCG fallback mode, how
> > can I specify the right gic-version? ie:
> >
> > -M virt,gic-version=host,accel=kvm:tcg
> >
> > Only qemu know
On 26 May 2016 at 03:16, Jason Wang wrote:
> The following changes since commit 287db79df8af8e31f18e262feb5e05103a09e4d4:
>
> Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into
> staging (2016-05-24 13:06:33 +0100)
>
> are available in the git repository at:
>
> https:
On 26/05/2016 14:53, Sergey Fedorov wrote:
>>> I'm afraid even our recent efforts in
>>> multi-threaded TCG won't change the situation. The problem is that it
>>> would require to translate somehow ARM's exclusive access monitor to x86
>>> model.
>>>
>> The cmpxchg-based variant would work. It d
Now we have an emulated GICv3, remove the restriction in
gicv3_class_name() so that the user can request a GICv3 with
-machine gic-version=3 even when not using KVM.
Signed-off-by: Peter Maydell
---
target-arm/machine.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target
Move the GICv3 parent_irq and parent_fiq pointers into the
GICv3CPUState structure rather than giving them their own array.
This will make it easy to assert the IRQ and FIQ lines for a
particular CPU interface without having to know or calculate
the CPU index for the GICv3CPUState we are working on
A half-shuffle operation takes a word with zeros in the high half:
ABCD EFGH IJKL MNOP
and spreads the bits out so they are in every other bit of the word:
0A0B 0C0D 0E0F 0G0H 0I0J 0K0L 0M0N 0O0P
A half-unshuffle performs the reverse operation.
Provide functions in bitops.h w
The GICv3 system registers need to know if the CPU is AArch64
in EL3 or AArch32 in Monitor mode. This happens to be the first
part of the check for arm_is_secure(), so factor it out into a
new arm_is_el3_or_mon() function that the GIC can also use.
Signed-off-by: Peter Maydell
---
target-arm/cpu
On 05/26/2016 09:08 AM, Peter Maydell wrote:
>
> Apologies for the lack of any backtraces in the output, but
> this is almost certainly the result of trying to do le64_to_cpu()
> or cpu_to_le64() on a buffer which isn't necessarily aligned
> (usually some pointer into guest memory). Use the functi
From: Pavel Fedin
Add state structure descriptors for the GICv3 state. We mark
the KVM GICv3 device as having a migration blocker until the
code to save and restore the state in the kernel is implemented.
Signed-off-by: Pavel Fedin
[PMM: Adjust to renamed struct fields; switched to using uint32
From: Shlomo Pongratz
This patch includes the device class itself, some ID register
value functions which will be needed by both distributor
and redistributor, and some skeleton functions for handling
interrupts coming in and going out, which will be filled in
in a subsequent patch.
Signed-off-b
From: Pavel Fedin
Add state information to GICv3 object structure and implement
arm_gicv3_common_reset().
This commit includes accessor functions for the fields which are
stored as bitmaps in uint32_t arrays.
Signed-off-by: Pavel Fedin
[PMM: significantly overhauled:
* Add missing qom/cpu.h i
The GICv3 CPU interface needs to know when the CPU it is attached
to makes an exception level or mode transition that changes the
security state, because whether it is asserting IRQ or FIQ can change
depending on these things. Provide a mechanism for letting the GICv3
device register a hook to be c
Implement the GICv3 logic to recalculate the highest priority pending
interrupt for each CPU after some part of the GIC state has changed.
We avoid unnecessary full recalculation where possible.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3.c| 293 +++
Implement the CPU interface registers for the GICv3; these are
CPU system registers, not MMIO registers.
This commit implements all the registers which are simple
accessors for GIC state, but not those which act as interfaces
for acknowledging, dismissing or generating interrupts. (Those
will be a
From: Shlomo Pongratz
Implement the redistributor registers of a GICv3.
Signed-off-by: Shlomo Pongratz
[PMM: significantly overhauled/rewritten:
* use the new data structures
* restructure register read/write to handle different width accesses
natively, since almost all registers are 32-bi
Define a VMSTATE_UINT64_2DARRAY macro, to go with the ones we
already have for other type sizes.
Signed-off-by: Peter Maydell
---
include/migration/vmstate.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 30ecc44..aec9531
From: Pavel Fedin
This actually implements pre_save and post_load methods for in-kernel
vGICv3.
Signed-off-by: Pavel Fedin
[PMM:
* use decimal, not 0bnnn
* fixed typo in names of ICC_APR0R_EL1 and ICC_AP1R_EL1
* completely rearranged the get and put functions to read and write
the state i
From: Pavel Fedin
This allows to override default affinity IDs on a per-machine basis, and
possibility to retrieve IDs will be used by vGICv3 live migration code.
Signed-off-by: Pavel Fedin
Signed-off-by: Peter Maydell
---
target-arm/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/t
On 26 May 2016 at 16:20, Eric Blake wrote:
> On 05/26/2016 09:08 AM, Peter Maydell wrote:
>>
>> Apologies for the lack of any backtraces in the output, but
>> this is almost certainly the result of trying to do le64_to_cpu()
>> or cpu_to_le64() on a buffer which isn't necessarily aligned
>> (usual
Add the CPU interface registers which deal with acknowledging
and dismissing interrupts.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_cpuif.c | 437 ++
hw/intc/gicv3_internal.h | 5 +
trace-events | 7 +
3 files changed, 449 ins
Now we have an emulated GICv3 we should advertise it via the
capabilities in the monitor protocol.
Signed-off-by: Peter Maydell
---
target-arm/monitor.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-arm/monitor.c b/target-arm/monitor.c
index 1ee59a2..299cb80 100644
On 26/05/2016 14:22, Marc-André Lureau wrote:
> Hi
>
> On Thu, May 26, 2016 at 10:49 AM, Paolo Bonzini wrote:
>> Remove direct uses of ram_addr_t and optimize memory_region_{get,set}_fd
>> now that a MemoryRegion knows its RAMBlock directly.
>>
>> Signed-off-by: Paolo Bonzini
>> ---
>> exec.c
Public bug reported:
Hy,
the host system crashes completely, when i try to pass an physical
device without boot option intel_iommu=on set. In older kernel versions
you didn't have to pass that option.
I wonder if this can be easily checked by asking iommu state, avoiding a
crash of the complete
Sorry, i have to cancel this report.
The problem seems to be somewhere else. After some reboots the same
issue came up again.
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https://bugs.launchpad.net/bugs/1585971
Title:
Host syst
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