David Gibson writes:
> On Thu, Jan 28, 2016 at 02:23:28PM +, Alex Bennée wrote:
>> We only ran make check once before it used to be an unreliable target.
>> It was only a stop gap measure and we should be able to revert it now.
>> This also stops us needing a large all-MMU build.
>>
>> We di
Michael Tokarev writes:
> 28.01.2016 17:23, Alex Bennée wrote:
>> Hi,
>>
>> The first patch has been reviewed and signed off. Long term I think
>> it is worth applying but it look like the performance increase it
>> negligible compared to the old style VM builds at the moment. I
>> suspect this
On Sun, Jan 31, 2016 at 08:37:49AM +, Alex Bennée wrote:
>
> David Gibson writes:
>
> > On Thu, Jan 28, 2016 at 02:23:28PM +, Alex Bennée wrote:
> >> We only ran make check once before it used to be an unreliable target.
> >> It was only a stop gap measure and we should be able to revert
Move allocation to virtio functions also when loading/saving a
VirtQueueElement. This will also let the load/save functions
keep backwards compatibility when the VirtQueueElement layout
is changed.
Reviewed-by: Cornelia Huck
Signed-off-by: Paolo Bonzini
---
hw/block/virtio-blk.c | 10 +++
Allocate the arrays for in_addr/out_addr/in_sg/out_sg outside the
VirtQueueElement. For now, virtqueue_pop and vring_pop keep
allocating a very large VirtQueueElement.
Reviewed-by: Cornelia Huck
Signed-off-by: Paolo Bonzini
---
v1->v2: add assertions on sz [Conny]
hw/virtio/dataplane/
This includes two optimization of virtio:
- "slimming down" VirtQueueElements by not including room for
1024 buffers. This makes malloc much faster.
- optimizations to limit the number of address_space_translate
calls in virtio.c, from Vincenzo and myself.
Thanks,
Paolo
v1->v2: improved c
The next patch will make virtqueue_pop/vring_pop allocate memory for
the VirtQueueElement. In some cases (blk, scsi, gpu) the device wants
to extend VirtQueueElement with device-specific fields and, until now,
the place of the VirtQueueElement within the containing struct didn't
matter. When alloca
Build the addresses and s/g lists on the stack, and then copy them
to a VirtQueueElement that is just as big as required to contain this
particular s/g list. The cost of the copy is minimal compared to that
of a large malloc.
When virtqueue_map is used on the destination side of migration or on
l
Build the addresses and s/g lists on the stack, and then copy them
to a VirtQueueElement that is just as big as required to contain this
particular s/g list. The cost of the copy is minimal compared to that
of a large malloc.
Reviewed-by: Cornelia Huck
Signed-off-by: Paolo Bonzini
---
hw/virti
From: Vincenzo Maffione
The virtqueue_pop() implementation needs to check if the avail ring
contains some pending buffers. To perform this check, it is not
always necessary to fetch the avail_idx in the VQ memory, which is
expensive. This patch introduces a shadow variable tracking avail_idx
and
From: Vincenzo Maffione
Fill in an element of the used ring with a single combined access to the
guest physical memory, rather than using two separated accesses.
This reduces the overhead due to expensive address translation.
Signed-off-by: Vincenzo Maffione
Message-Id:
Reviewed-by: Cornelia
Compared to vring, virtio has a performance penalty of 10%. Fix it
by combining all the reads for a descriptor in a single address_space_read
call. This also simplifies the code nicely.
Reviewed-by: Cornelia Huck
Signed-off-by: Paolo Bonzini
---
hw/virtio/virtio.c | 86 ++-
From: Vincenzo Maffione
Accessing used_idx in the VQ requires an expensive access to
guest physical memory. Before this patch, 3 accesses are normally
done for each pop/push/notify call. However, since the used_idx is
only written by us, we can track it in our internal data structure.
Signed-off
The return code of virtqueue_pop/vring_pop is unused except to check for
errors or 0. We can thus easily move allocation inside the functions
and just return a pointer to the VirtQueueElement.
The advantage is that we will be able to allocate only the space that
is needed for the actual size of t
On 31 January 2016 at 08:43, Alex Bennée wrote:
> Maybe what's really needed is a build and test automation tree (and
> associated maintainer)? Peter any comments?
If you want to be the submaintainer for that, be my guest :-)
thanks
-- PMM
Hi Eduardo,
I will try to answer some of your questions at this email and will answer
other questions later.
> Can you clarify what you mean by "TYPE_DEVICE has its own
> properties"? TYPE_DEVICE properties are registered as normal QOM
> properties.
It is possible that I do not understand object
ping
http://patchwork.ozlabs.org/patch/537763
http://patchwork.ozlabs.org/patch/537762
On Mon, Jan 11, 2016 at 2:12 PM, Markus Armbruster
wrote:
> Copying Paolo.
>
> Leonid Bloch writes:
>
> > This series addresses two cases where errors were printed if whitespaces
> > appeared in front of a s
ping
http://patchwork.ozlabs.org/patch/565712
On Mon, Jan 11, 2016 at 11:12 AM, Leonid Bloch wrote:
> With automatically generated GUID, on minor version changes, an error
> occurred, stating that there is a problem with the installer.
> Now, a notification is shown, warning the user that anoth
Hi Daniel,
Commit d0d7708ba29cbcc343364a46bff981e0ff88366f "qemu-char: add logfile
facility to all chardev backends" appears to be causing problems with
the monitor and stdin/stdout on both qemu-system-sparc/qemu-system-ppc here.
On current git master I see the following behaviour changes when
la
On 31 January 2016 at 15:19, Mark Cave-Ayland
wrote:
> Hi Daniel,
>
> Commit d0d7708ba29cbcc343364a46bff981e0ff88366f "qemu-char: add logfile
> facility to all chardev backends" appears to be causing problems with
> the monitor and stdin/stdout on both qemu-system-sparc/qemu-system-ppc here.
Thes
On Friday, January 29, 2016, Christopher Covington
wrote:
> On 10/20/2015 01:22 PM, Shlomo Pongratz wrote:
> > From: Shlomo Pongratz >
> >
> > This patch is a first step multicores support for arm64.
> >
> > This implemntation was tested up to 100 cores.
> >
> > Things left to do:
> >
> > Support
On 31/01/16 15:34, Peter Maydell wrote:
> On 31 January 2016 at 15:19, Mark Cave-Ayland
> wrote:
>> Hi Daniel,
>>
>> Commit d0d7708ba29cbcc343364a46bff981e0ff88366f "qemu-char: add logfile
>> facility to all chardev backends" appears to be causing problems with
>> the monitor and stdin/stdout on
On 29.01.2016 22:17, Sergey Fedorov wrote:
> This series is intended to fix ARM watchpoint emulation misbehavior.
> QEMU hangs when QEMU watchpoint fires but it does not pass additional
> architectural checks in ARM CPU debug exception handler. For details,
> please see individual patches. The most
ARM stops before access to a location covered by watchpoint. Also, QEMU
watchpoint fire is not necessarily an architectural watchpoint match.
Unfortunately, that is hardly possible to ignore a fired watchpoint in
debug exception handler. So move watchpoint check from debug exception
handler to the
When QEMU watchpoint matches, that is not definitely an architectural
watchpoint match yet. If it is a stop-before-access watchpoint then that
is hardly possible to ignore it after throwing a TCG exception.
A special callback is introduced to check for architectural watchpoint
match before raising
This series is intended to fix ARM watchpoint emulation misbehavior.
QEMU hangs when QEMU watchpoint fires but it does not pass additional
architectural checks in ARM CPU debug exception handler. For details,
please see individual patches. The most relevant parts of the original
discussion about AR
On Fri, Jan 29, 2016 at 12:13:59PM +0100, Igor Mammedov wrote:
> On Thu, 28 Jan 2016 14:59:25 +0200
> "Michael S. Tsirkin" wrote:
>
> > On Thu, Jan 28, 2016 at 01:03:16PM +0100, Igor Mammedov wrote:
> > > On Thu, 28 Jan 2016 13:13:04 +0200
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Th
On 31/01/2016 16:54, Mark Cave-Ayland wrote:
> Aha! A quick test here shows that the patch fixes the serial port
> appearing on stdout and entering the monitor, but I still see the
> multiple echo problem in the GTK GUI.
>
> I also notice that with the above commit I lose cycling through history
On Sat, 2016-01-30 at 01:18 +, Kay, Allen M wrote:
>
> > -Original Message-
> > From: iGVT-g [mailto:igvt-g-boun...@lists.01.org] On Behalf Of Alex
> > Williamson
> > Sent: Friday, January 29, 2016 10:00 AM
> > To: Gerd Hoffmann
> > Cc: igv...@ml01.01.org; xen-de...@lists.xensource.com
On 31 January 2016 at 17:19, Paolo Bonzini wrote:
> On 31/01/2016 16:54, Mark Cave-Ayland wrote:
>> I also notice that with the above commit I lose cycling through history
>> in the GTK monitor - even with the multiple echo, instead of the up/down
>> arrow keys cycling through the history instead
From: Wei Xu
Segment is the coalesced packets in a connection.
Status is to indicate the status while do coalescing, such as if a
packet is bypassed or coalesced, etc.
Chain is used to save the segments of different protocols in a VirtIONet
instance.
A timer is used in a chain to help purging
From: Wei Xu
Since this feature also needs to support IPv6, and there are
some protocol specific differences difference for IPv4/6 in the header,
so try to make the interface to be general.
IPv4/6 should set up both the new and old IP/TCP header before invoking
TCP coalescing, and should also te
From: Wei Xu
The chain list is initialized when the device is getting realized,
and the entry of the chain will be inserted dynamically according
to protocol type of the network traffic.
All the buffered packets and chain will be destroyed when the
device is going to be unrealized.
Signed-off-b
From: Wei Xu
Patch v2 add detailed commit log.
This patch is to support WHQL test for Windows guest, while this feature also
benifits other guest works as a kernel 'gro' like feature with userspace
implementation.
Feature information:
http://msdn.microsoft.com/en-us/library/windows/hardware/j
From: Wei Xu
Upon a packet is arriving, a corresponding chain will be selected or created,
or be bypassed if it's not an IPv4 packets.
The callback in the chain will be invoked to call the real coalescing.
Since the coalescing is based on the TCP connection, so the packets will be
cached if the
From: Wei Xu
If a field in the IPv4 header is modified, then the checksum
have to be recalculated before sending it out.
Signed-off-by: Wei Xu
---
hw/net/virtio-net.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 93df0d
From: Wei Xu
The timer will only be triggered if the packets pool is not empty,
and it'll drain off all the cached packets, this is to reduce the
delay to upper layer protocol stack.
Signed-off-by: Wei Xu
---
hw/net/virtio-net.c | 38 ++
1 file changed, 38 i
From: Wei Xu
A few more stuffs should be included to support this
1. Corresponding chain lookup
2. Coalescing callback for the protocol chain
3. Filter & Sanity Check.
Signed-off-by: Wei Xu
---
hw/net/virtio-net.c | 104 +++-
1 file changed, 102
From: Wei Xu
Normally it includes 2 typical way to handle a TCP control flag, bypass
and finalize, bypass means should be sent out directly, and finalize
means the packets should also be bypassed, and this should be done
after searching for the same connection packets in the pool and sending
all
From: Wei Xu
More general exception cases check
1. Incorrect version in IP header
2. IP options & IP fragment
3. Not a TCP packets
4. Sanity size check to prevent buffer overflow attack.
Signed-off-by: Wei Xu
---
hw/net/virtio-net.c | 44
1 file cha
From: Wei Xu
Add statistics to log what happened during the process.
Signed-off-by: Wei Xu
---
hw/net/virtio-net.c| 49 +++---
include/hw/virtio/virtio.h | 33 +++
2 files changed, 79 insertions(+), 3 deletions(-)
dif
On Mon, Feb 01, 2016 at 02:13:21AM +0800, w...@redhat.com wrote:
> From: Wei Xu
>
> The chain list is initialized when the device is getting realized,
> and the entry of the chain will be inserted dynamically according
> to protocol type of the network traffic.
>
> All the buffered packets and c
On Mon, Feb 01, 2016 at 02:13:22AM +0800, w...@redhat.com wrote:
> From: Wei Xu
>
> Upon a packet is arriving, a corresponding chain will be selected or created,
> or be bypassed if it's not an IPv4 packets.
>
> The callback in the chain will be invoked to call the real coalescing.
>
> Since th
On Mon, Feb 01, 2016 at 02:13:19AM +0800, w...@redhat.com wrote:
> From: Wei Xu
>
> Patch v2 add detailed commit log.
>
> This patch is to support WHQL test for Windows guest, while this feature also
> benifits other guest works as a kernel 'gro' like feature with userspace
> implementation.
>
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac_newworld.c |4
hw/ppc/mac_oldworld.c |4
2 files changed, 8 insertions(+)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index f95086b..3283f1d 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -179,6 +1
This patchset allows migration of the PPC timebase for g3beige/mac99
machines under TCG on non-PPC hosts.
The majority of the work is in patch 2: here the existing migration code is
split into PPC and non-PPC host codepaths (where the previous behaviour is
preserved). In effect, non-PPC hosts use
This patch provides support for migration of the PPC guest timebase on non-PPC
host architectures (i.e those using QEMU's virtual emulated timebase).
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/ppc.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff
ns_diff is already clamped to a minimum of 0 to prevent the timebase going
backwards during migration due to misaligned clocks. Following on from this
migration_duration_tb is also subject to the same constraint; hence the
expression MIN(0, migration_duration_tb) always evaluates to 0 and so no
tim
On 31 January 2016 at 19:19, Mark Cave-Ayland
wrote:
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/ppc/mac_newworld.c |4
> hw/ppc/mac_oldworld.c |4
> 2 files changed, 8 insertions(+)
>
> diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
> index f95086b..3283f1d 100644
On 31/01/16 19:58, Peter Maydell wrote:
> On 31 January 2016 at 19:19, Mark Cave-Ayland
> wrote:
>> Signed-off-by: Mark Cave-Ayland
>> ---
>> hw/ppc/mac_newworld.c |4
>> hw/ppc/mac_oldworld.c |4
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/hw/ppc/mac_newworld.c b/h
On 31/01/2016 18:54, Peter Maydell wrote:
> On 31 January 2016 at 17:19, Paolo Bonzini wrote:
>> On 31/01/2016 16:54, Mark Cave-Ayland wrote:
>>> I also notice that with the above commit I lose cycling through history
>>> in the GTK monitor - even with the multiple echo, instead of the up/down
>
On Sat, Jan 30, 2016 at 11:29:43PM +1100, David Gibson wrote:
> On Fri, Jan 29, 2016 at 02:48:23PM +, Peter Maydell wrote:
> > On 29 January 2016 at 05:06, David Gibson
> > wrote:
> > > The following changes since commit
> > > 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
> > >
> > > Merge rem
On Fri, Jan 29, 2016 at 06:40:21PM +, James Clarke wrote:
> Here is the description of the mcrfs instruction from the PowerPC Architecture
> Book, Version 2.02, Book I: PowerPC User Instruction Set Architecture
> (http://www.ibm.com/developerworks/systems/library/es-archguide-v2.html),
> found
> On 31 Jan 2016, at 23:50, David Gibson wrote:
> On Fri, Jan 29, 2016 at 06:40:21PM +, James Clarke wrote:
>> Here is the description of the mcrfs instruction from the PowerPC
>> Architecture
>> Book, Version 2.02, Book I: PowerPC User Instruction Set Architecture
>> (http://www.ibm.com/deve
On 31/01/2016 14:25, Sitsofe Wheeler wrote:
>> > Thanks, queued. Will send a pull request some time next week.
> Just checking - did this one get lost? Nothing's popped up in the QEMU
> git repos yet...
Hmm, yes. Thanks for telling me.
Paolo
On 01/29/2016 11:46 PM, Stefan Hajnoczi wrote:
> On Fri, Jan 29, 2016 at 11:13:42AM +0800, Changlong Xie wrote:
>> On 01/28/2016 11:15 PM, Stefan Hajnoczi wrote:
>>> On Thu, Jan 28, 2016 at 09:13:24AM +0800, Wen Congyang wrote:
On 01/27/2016 10:46 PM, Stefan Hajnoczi wrote:
> On Wed, Jan 1
On 01/29/2016 06:47 PM, Dr. David Alan Gilbert wrote:
> * Wen Congyang (we...@cn.fujitsu.com) wrote:
>> On 01/29/2016 06:07 PM, Dr. David Alan Gilbert wrote:
>>> * Wen Congyang (we...@cn.fujitsu.com) wrote:
On 01/27/2016 07:03 PM, Dr. David Alan Gilbert wrote:
> Hi,
> I've got a bloc
On Sun, Jan 31, 2016 at 07:19:34PM +, Mark Cave-Ayland wrote:
> ns_diff is already clamped to a minimum of 0 to prevent the timebase going
> backwards during migration due to misaligned clocks. Following on from this
> migration_duration_tb is also subject to the same constraint; hence the
> ex
On Sun, Jan 31, 2016 at 08:10:08PM +, Mark Cave-Ayland wrote:
> On 31/01/16 19:58, Peter Maydell wrote:
>
> > On 31 January 2016 at 19:19, Mark Cave-Ayland
> > wrote:
> >> Signed-off-by: Mark Cave-Ayland
> >> ---
> >> hw/ppc/mac_newworld.c |4
> >> hw/ppc/mac_oldworld.c |4
On Sun, Jan 31, 2016 at 07:19:35PM +, Mark Cave-Ayland wrote:
> This patch provides support for migration of the PPC guest timebase on non-PPC
> host architectures (i.e those using QEMU's virtual emulated timebase).
>
> Signed-off-by: Mark Cave-Ayland
We shouldn't need an explicit test for a
On Tue, Jan 26, 2016 at 10:31:19PM +, Mark Cave-Ayland wrote:
> On 25/01/16 11:10, David Gibson wrote:
>
> > Um.. so the migration duration is a complete red herring, regardless
> > of the units.
> >
> > Remember, we only ever compute the guest timebase value at the moment
> > the guest reque
From: Mark Cave-Ayland
Make sure that we include the value of dma_active in the migration stream.
Signed-off-by: Mark Cave-Ayland
Acked-by: John Snow
Signed-off-by: David Gibson
---
hw/ide/macio.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ide/macio.c b/hw/ide/m
From: Mark Cave-Ayland
Otherwise some internal xer variables fail to get set post-migration.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Alexey Kardashevskiy
Signed-off-by: David Gibson
---
target-ppc/machine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/m
rtas_st_buffer_direct() is a not particularly useful wrapper around
cpu_physical_memory_write(). All the callers are in
rtas_ibm_configure_connector, where it's better handled by local helper.
Signed-off-by: David Gibson
Reviewed-by: Alexey Kardashevskiy
---
hw/ppc/spapr_rtas.c| 17 +++
From: Benjamin Herrenschmidt
We never released anything older than POWER8 DD2.0 and POWER8E DD2.1,
so let's use these versions, without that some firmware or Linux code
might fail to use some HW features that were non functional in earlier
internal only spins of the chip.
Signed-off-by: Benjamin
From: Mark Cave-Ayland
Make sure that we include the DBDMA controller state in the migration
stream.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
hw/misc/macio/mac_dbdma.c | 40
1 file changed, 36 insertions(+), 4 deletions(-)
diff
The following changes since commit 0430891ce162b986c6e02a7729a942ecd2a32ca4:
hw: Clean up includes (2016-01-29 15:07:25 +)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.6-20160201
for you to fetch changes up to d1277156b5d3df6d75d138a7eec6ff809
From: Mark Cave-Ayland
Include some fields missed from the previous VMState conversion to the
migration stream, as well as the new SR_INT delay timer.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
hw/misc/macio/cuda.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions
From: Mark Cave-Ayland
Currently the aiocb is held within MACIOIDEState, however the IDE core code
assumes that the current actvie DMA aiocb is held in aiocb in a few places,
e.g. ide_bus_reset() and ide_reset().
Switch over to using IDEDMA aiocb to store the aiocb for the current active
DMA req
Use error_setg() to return an error rather than an explicit exit().
Previously it was an exit(0) instead of a non-zero exit code, which was
simply a bug. Also improve the error message.
While we're at it change the type of spapr_vga_init() to bool since that's
how we're using it anyway.
Signed-o
From: Bharata B Rao
If guest doesn't have any dynamically reconfigurable (DR) logical memory
blocks (LMB), then we shouldn't create ibm,dynamic-reconfiguration-memory
device tree node.
Signed-off-by: Bharata B Rao
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 9 -
1 file changed, 8
This function includes a number of explicit fprintf()s for errors.
Change these to use error_report() instead.
Also replace the single exit(EXIT_FAILURE) with an explicit exit(1), since
the latter is the more usual idiom in qemu by a large margin.
Signed-off-by: David Gibson
Reviewed-by: Alexey
h_client_architecture_support() uses rtas_ld() for general purpose memory
access, despite the fact that it's not an RTAS routine at all and rtas_ld
makes things more awkward.
Clean this up by replacing rtas_ld() calls with appropriate ldXX_phys()
calls.
Signed-off-by: David Gibson
Reviewed-by: A
The implementation of the H_ENTER hypercall for PAPR guests needs to
enforce correct access attributes on the inserted HPTE. This means
determining if the HPTE's real address is a regular RAM address (which
requires attributes for coherent access) or an IO address (which requires
attributes for ca
Currently spapr_cpu_init() is hardcoded to handle any errors as fatal.
That works for now, since it's only called from initial setup where an
error here means we really can't proceed.
However, we'll want to handle this more flexibly for cpu hotplug in future
so generalize this using the error repo
rtas_st_buffer() appears in spapr.h as though it were a widely used helper,
but in fact it is only used for saving data in a format used by
rtas_ibm_get_system_parameter(). This changes it to a local helper more
specifically for that function.
While we're there fix a couple of small defects in
rt
From: Greg Kurz
On VSX capable CPUs, the 32 FP registers are mapped to the high-bits
of the 32 first VSX registers. So if you have:
VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00
then
FPR31 = (uint64) 0x0102030405060708
The kernel stores the VSX registers in the fp_state struct followin
The errors detected in this function necessarily indicate bugs in the rest
of the qemu code, rather than an external or configuration problem.
So, a simple assert() is more appropriate than any more complex error
reporting.
Signed-off-by: David Gibson
Reviewed-by: Thomas Huth
Reviewed-by: Alexe
From: Alyssa Milburn
This avoids MacsBug hanging at startup in the absence of ADB mouse
input, by replying with an error (which is also what MOL does) when
it sends an unknown command (0x1c).
Signed-off-by: Alyssa Milburn
Signed-off-by: David Gibson
---
hw/misc/macio/cuda.c | 5 +
1 file
ppc_store_slb updates the SLB for PPC cpus with 64-bit hash MMUs.
Currently it takes two parameters, which contain values encoded as the
register arguments to the slbmte instruction, one register contains the
ESID portion of the SLBE and also the slot number, the other contains the
VSID portion of
Use the error handling infrastructure to pass an error out from
try_create_xics() instead of assuming &error_abort - the caller is in a
better position to decide on error handling policy.
Also change the error handling from an &error_abort to &error_fatal, since
this occurs during the initial mach
ppc_tlb_invalidate_one() has a big switch handling many different MMU
types. However, most of those branches can never be reached:
It is called from 3 places: from remove_hpte() and h_protect() in
spapr_hcall.c (which always has a 64-bit hash MMU type), and from
helper_tlbie() in mmu_helper.c.
C
From: Greg Kurz
Let's reuse the ppc_maybe_bswap_register() helper, like we already do
with the general registers.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
target-ppc/translate_init.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-p
From: Greg Kurz
This helper will be used to support FP, Altivec and VSX registers when
the guest is little-endian.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
target-ppc/cpu.h | 1 +
target-ppc/gdbstub.c | 10 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff
When HPTEs are removed or modified by hypercalls on spapr, we need to
invalidate the relevant pages in the qemu TLB.
Currently we do that by doing some complicated calculations to work out the
right encoding for the tlbie instruction, then passing that to
ppc_tlb_invalidate_one()... which totally
Now that the TCG and spapr code has been extended to allow (semi-)
arbitrary page encodings in the CPU's 'sps' table, we can add the many
page sizes supported by real POWER7 and POWER8 hardware that we previously
didn't support in TCG.
Signed-off-by: David Gibson
Acked-by: Benjamin Herrenschmidt
From: Anton Blanchard
Add the XML and functions to get and set VSX registers.
Signed-off-by: Anton Blanchard
(fixed little-endian guests)
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
configure | 6 +++---
gdb-xml/power-vsx.xml | 44 +++
Current ppc_set_compat() returns -1 for errors, and also (unconditionally)
reports an error message. The caller in h_client_architecture_support()
may then report it again using an outdated fprintf().
Clean this up by using the modern error reporting mechanisms. Also add
strerror(errno) to the e
From: Greg Kurz
Let's reuse the ppc_maybe_bswap_register() helper, like we already do
with the general registers.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
target-ppc/translate_init.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-ppc/tra
Use error_setg() and return an error, rather than using an explicit exit().
Also improve messages, and be more explicit about which constraint failed.
Signed-off-by: David Gibson
Reviewed-by: Bharata B Rao
Reviewed-by: Thomas Huth
Reviewed-by: Alexey Kardashevskiy
Reviewed-by: Markus Armbrust
Like a lot of places these files include a mixture of functions taking
both the older CPUPPCState *env and newer PowerPCCPU *cpu. Move a step
closer to cleaning this up by standardizing on PowerPCCPU, except for the
helper_* functions which are called with the CPUPPCState * from tcg.
Callers and
From: James Clarke
Signed-off-by: James Clarke
Signed-off-by: David Gibson
---
target-ppc/cpu.h | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 0820390..f300c86 100644
--- a/target-ppc/cpu.h
+++ b/ta
From: Greg Kurz
This helper will be used to support Altivec registers in little-endian guests.
This patch does not change functionnality.
Note: I had to put the helper some lines away from the gdb_*_avr_reg()
routines to get a more readable patch.
Signed-off-by: Greg Kurz
Signed-off-by: David
This stub function is in the !KVM ifdef in target-ppc/kvm_ppc.h. However
no such function exists on the KVM side, or is ever used.
I think this originally referenced a function which read host page size
information from /proc, for we we now use the KVM GET_SMMU_INFO extension
instead.
In any cas
h_enter() in the spapr code needs to know the page size of the HPTE it's
about to insert. Unlike other paths that do this, it doesn't have access
to the SLB, so at the moment it determines this with some open-coded
tests which assume POWER7 or POWER8 page size encodings.
To make this more flexibl
From: Greg Kurz
Altivec registers are 128-bit wide. They are stored in memory as two
64-bit values that must be byteswapped when the guest is little-endian.
Let's reuse the ppc_maybe_bswap_register() helper for this.
We also need to fix the ordering of the 64-bit elements according to
the target
From: Programmingkid
Darwin/OS X use the undocumented kMacRISCPCIAddressSelect (0x48) to
configure PCI memory space size for mac99 machines. Without this
register, warnings similar to below are emitted to the console during boot:
AppleMacRiscPCI: bad range 2(8000:0100)
AppleMacRiscPCI: b
On Fri, 01/29 11:31, Stefan Hajnoczi wrote:
> On Fri, Jan 29, 2016 at 10:19:49AM +0800, Fam Zheng wrote:
> > @@ -402,6 +407,10 @@ typedef void BlockJobDeferToMainLoopFn(BlockJob *job,
> > void *opaque);
> > * AioContext acquired. Block jobs must call bdrv_unref(), bdrv_close(),
> > and
> > *
The functions for migrating the hash page table on pseries machine type
(htab_save_setup() and htab_load()) can report some errors with an
explicit fprintf() before returning an appropriate error code. Change some
of these to use error_report() instead. htab_save_setup() is omitted for
now to avoi
At present the 64-bit hash MMU code uses information from the SLB to
determine the page size of a translation. We do need that information to
correctly look up the hash table. However the MMU also allows a
possibly larger page size to be encoded into the HPTE itself, which is used
to populate the
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