On 15 June 2015 at 16:36, Alex Züpke wrote:
> So this is the way to go:
>
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -4084,6 +4084,7 @@ static void gen_nop_hint(DisasContext *s, int val)
> gen_set_pc_im(s, s->pc);
> s->is_jmp = DISAS_WFI;
> break;
On 06/11/2015 01:59 AM, Artyom Tarasenko wrote:
This is a very promising approach. Would it also work on a large
numbers of MMU modes?
Particulary I wonder if it would work for SPARC, where 32-bit
processors have up to 65536 MMU contexts.
No, it wouldn't.
r~
On 06/12/2015 08:05 AM, Don Slutz wrote:
> This adds one new inject command:
>
> inject-vmport-action
>
> And three guest info commands:
>
> vmport-guestinfo-set
> vmport-guestinfo-get
> query-vmport-guestinfo
>
> More details in qmp-commands.hx
>
> Signed-off-by: Don Slutz
> CC: Don Slutz
>
From: Alexander Graf
The ioinst_schib_valid gets a SCHIB in guest endianness, we should
byteswap the fields we access.
Cc: Christian Borntraeger
Cc: Cornelia Huck
Signed-off-by: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-s390x/ioinst.c | 6 +++---
1 file changed, 3 insertions(+
DIAG IPL is already implemented for KVM, but not wired from TCG. For
that change the format of the instruction so that we can get R1 and R3
numbers in addition to the function code.
The diag function can change plenty of things, including CC, so we
should enter with a static CC. Also it doesn't se
This patchset adds support for CCW in TCG mode, allowing a s390-ccw
machine to boot using the s390-ccw firmware and zipl, and the Linux
kernel to access the virtio-ccw devices.
The way to do that is to wire up all the I/O instructions to the KVM
functions emulating them. This is the purpose of the
The s390_cpu_initial_reset function zeroes a big part of the CPU state
structure, including CPU_COMMON, and thus the QEMU TLB structure. As
they should not be initialized with zeroes only, we need to call the
tlb_flush to initialize it correctly.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-o
env->io_index[] should be set to -1 during CPU reset to mark the
I/O interrupt queue as empty.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index
The I/O-Interruption Subclass field corresponds to bits 2 to 5 (BE
notation) of the Interruption-Identification Word. The value should
be shift by 27 instead of 24.
Cc: Christian Borntraeger
Cc: Cornelia Huck
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-s390x/ioinst.h | 2 +-
1
On Sat, 13 Jun 2015 16:20:51 +0200
Markus Armbruster wrote:
> Error classes other than ERROR_CLASS_GENERIC_ERROR should not be used
> in new code. Hiding them in QERR_ macros makes new uses hard to spot.
> Fortunately, there's just one such macro left. Eliminate it with this
> coccinelle semant
This remove the corresponding error messages in TCG mode, and allow to
simplify the s390_assign_subch_ioeventfd() function.
CC: Cornelia Huck
Cc: Christian Borntraeger
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
hw/s390x/virtio-ccw.c | 4
target-s390x/cpu.h| 6 +-
2 file
From: Alexander Graf
The code handling the I/O instructions for KVM decodes the instruction
itself. In TCG mode also pass the full instruction word to the helpers.
Cc: Richard Henderson
Signed-off-by: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 11 ++
ta
env->ext_index should be initialized to -1 to mark the external
interrupt queue as emtpy. This should not be done in s390_cpu_initfn
as all the interrupt fields are later reset to 0 by the memset in
s390_cpu_initial_reset or s390_cpu_full_reset. Move the initialization
there.
Cc: Alexander Graf
C
On Mon, Jun 15, 2015 at 5:50 PM, Richard Henderson wrote:
> On 06/11/2015 01:59 AM, Artyom Tarasenko wrote:
>>
>> This is a very promising approach. Would it also work on a large
>> numbers of MMU modes?
>> Particulary I wonder if it would work for SPARC, where 32-bit
>> processors have up to 6553
In TCG mode we should store the CC value in env->cc_op. However do it
inconditionnaly because:
- the tcg_enabled function is not inlined
- it's probably faster to always store the value, especially given it
is likely in the same cache line than env->psw.mask.
Cc: Alexander Graf
Cc: Richard Hend
On Sat, 13 Jun 2015 16:20:47 +0200
Markus Armbruster wrote:
> After a bit over a year and many patches, QError is finally ripe. All
> that's left of qerror.h after this series is a bunch of QERR_ macros.
> Killing them is left for another day.
Excellent!
I did my best to review this series, bu
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/misc_helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index e36d957..3addde5 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s39
On 06/13/2015 08:20 AM, Markus Armbruster wrote:
> These macros expand into error class enumeration constant, comma,
> string. Unclean. Has been that way since commit 13f59ae.
>
> The error class is always ERROR_CLASS_GENERIC_ERROR since the previous
> commit.
>
> Clean up as follows:
>
> * Pr
On Mon, Jun 15, 2015 at 04:45:58PM +0100, Peter Maydell wrote:
> On 10 June 2015 at 10:52, Andrew Jones wrote:
> > Signed-off-by: Andrew Jones
> > Tested-by: Shannon Zhao
> > ---
> > hw/arm/virt-acpi-build.c | 43 ++-
> > 1 file changed, 42 insertions(+),
Am 15.06.2015 um 17:49 schrieb Peter Maydell:
> On 15 June 2015 at 16:36, Alex Züpke wrote:
>> So this is the way to go:
>>
>> --- a/target-arm/translate.c
>> +++ b/target-arm/translate.c
>> @@ -4084,6 +4084,7 @@ static void gen_nop_hint(DisasContext *s, int val)
>> gen_set_pc_im(s, s->pc
On Mon, 15 Jun 2015 15:34:24 +0300
Fahri Cihan Demirci wrote:
> On Mon, Jun 15, 2015 at 11:10:31AM +0200, Igor Mammedov wrote:
> > On Thu, 11 Jun 2015 10:39:05 +0300
> > Fahri Cihan Demirci wrote:
> >
> > > On Tue, Jun 09, 2015 at 05:44:15PM +0200, Eduardo Otubo wrote:
> > > > Hello all,
> > >
On 06/15/15 11:09, Eric Blake wrote:
> On 06/15/2015 07:53 AM, Don Slutz wrote:
>> On 06/12/15 18:38, Eric Blake wrote:
>
+/* Only support 1 address */
+if (addr) {
+return ~0U;
+}
>>>
>>> Different answer on 32-bit platforms (there, ~0U is 0x
On 12 June 2015 at 15:06, Peter Maydell wrote:
> Convert the pxa2xx-fir device to QOM, including using a
> VMState for its migration info.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/pxa2xx.c | 140
> ++--
> 1 file changed, 85 insertions(+
On 12/06/2015 15:02, Yongbok Kim wrote:
> Signal a Reserved Instruction exception for removed instruction encoding
> in microMIPS Release 6.
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 68
> +++
> 1 files changed, 68 insertions(
On 12/06/2015 15:02, Yongbok Kim wrote:
> add microMIPS TLBINV, TLBINVF
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c |8
> 1 files changed, 8 insertions(+), 0 deletions(-)
Reviewed-by: Leon Alrae
On 12/06/2015 15:02, Yongbok Kim wrote:
> rt, rs were swapped
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c |4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Leon Alrae
On Sat, Jun 13, 2015 at 04:20:48PM +0200, Markus Armbruster wrote:
> qerror_report_err() is a transitional interface to help with
> converting existing monitor commands to QMP. It should not be used
> elsewhere.
>
> The only remaining user in qemu-option.c is qemu_opts_parse(). Is it
> used in Q
On 12/06/2015 15:02, Yongbok Kim wrote:
> The function will be also used for microMIPS Release 6.
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 472 +++---
> 1 files changed, 236 insertions(+), 236 deletions(-)
Reviewed-by: Leon Alrae
On 06/15/2015 09:00 AM, Artyom Tarasenko wrote:
On Mon, Jun 15, 2015 at 5:50 PM, Richard Henderson wrote:
On 06/11/2015 01:59 AM, Artyom Tarasenko wrote:
This is a very promising approach. Would it also work on a large
numbers of MMU modes?
Particulary I wonder if it would work for SPARC, whe
On Fri, Jun 12, 2015 at 02:30:27PM +0530, Bharata B Rao wrote:
> Store memory address range information of boot memory in address
> range list of numa_info.
>
> This helps to have a common NUMA node lookup by address function that
> works for both boot time memory and hotplugged memory.
>
> Sign
On Mon, Jun 15, 2015 at 06:10:25PM +0200, Michael S. Tsirkin wrote:
> On Mon, Jun 15, 2015 at 04:45:58PM +0100, Peter Maydell wrote:
> > On 10 June 2015 at 10:52, Andrew Jones wrote:
> > > Signed-off-by: Andrew Jones
> > > Tested-by: Shannon Zhao
> > > ---
> > > hw/arm/virt-acpi-build.c | 43 ++
This patch allows the instantiation of the vfio-calxeda-xgmac device
from the QEMU command line (-device vfio-calxeda-xgmac,host="").
A specialized device tree node is created for the guest, containing
compat, dma-coherent, reg and interrupts properties.
Signed-off-by: Eric Auger
---
v12 -> v13
Anticipating for the introduction of new add/remove functions taking
a qemu_irq parameter, let's rename existing ones with a gsi suffix.
Signed-off-by: Eric Auger
Tested-by: Vikram Sethi
---
v15 -> v16:
- added Vikram's T-b
- resolve rebase conflict in kvm.h
---
hw/s390x/virtio-ccw.c | 8 +++
Now that the platform-bus is instantiated in virt, the ARM sysbus-fdt
infrastructure, the VFIO platform device and its first Calxeda xgmac
specialization also are on the master, let's complete the work by
- enabling the instantiation of the VFIO Calxeda xgmac device
- enabling irqfd usage, which i
The arm_gic_kvm now calls kvm_irqchip_set_qemuirq_gsi to build
the hash table storing qemu_irq/gsi mappings. From that point on
irqfd can be setup directly from the qemu_irq using
kvm_irqchip_add_irqfd_notifier.
Signed-off-by: Eric Auger
Tested-by: Vikram Sethi
---
v15 -> v16:
- added Vikram's
VFIO platform device needs to setup irqfd but it does not know the
gsi corresponding to the device qemu_irq. This series proposes to
store a hash table in kvm_state using the qemu_irq as key and the gsi
as a value.
kvm_irqchip_set_qemuirq_gsi allows to insert such a pair. The interrupt
controller
Add a new connect_irq_notifier notifier in the SysBusDeviceClass. This
notifier, if populated, is called after sysbus_connect_irq.
This mechanism is used to setup VFIO signaling once VFIO platform
devices get attached to their platform bus, on a machine init done
notifier.
Signed-off-by: Eric Aug
This patch aims at optimizing IRQ handling using irqfd framework.
Instead of handling the eventfds on user-side they are handled on
kernel side using
- the KVM irqfd framework,
- the VFIO driver virqfd framework.
the virtual IRQ completion is trapped at interrupt controller
This removes the need
On Wed, May 13, 2015 at 11:11:13AM +0800, Fam Zheng wrote:
> Before, we only yield after initializing dirty bitmap, where the QMP
> command would return. That may take very long, and guest IO will be
> blocked.
>
> Add sleep points like the later mirror iterations.
>
> Signed-off-by: Fam Zheng
>
On 06/15/2015 10:05 AM, Vladimir Sementsov-Ogievskiy wrote:
> On 12.06.2015 02:04, John Snow wrote:
>>
>> On 06/08/2015 11:21 AM, Vladimir Sementsov-Ogievskiy wrote:
>>> From: Vladimir Sementsov-Ogievskiy
>>>
>>> Adds dirty-bitmaps feature to qcow2 format as specified in
>>> docs/specs/qcow2.txt
From: Eric Auger
Sent: Monday, June 15, 2015 4:42 PM
To: Yehuda Yitschak; qemu-devel@nongnu.org
Cc: Yuval Caduri; Shadi Ammouri
Subject: Re: Assigning an eth port to a guest VM
Hi Yehuda,
On 06/15/2015 01:01 PM, Yehuda Yitschak wrote:
>> Cc: Eric Auger
>>
On 15 June 2015 at 17:32, Andrew Jones wrote:
> On Mon, Jun 15, 2015 at 06:10:25PM +0200, Michael S. Tsirkin wrote:
>> On Mon, Jun 15, 2015 at 04:45:58PM +0100, Peter Maydell wrote:
>> > I'm still confused about when fields in these ACPI structs
>> > need to be converted to little-endian, and when
Hi Yehuda,
On 06/15/2015 06:52 PM, Yehuda Yitschak wrote:
>
>
> From: Eric Auger
> Sent: Monday, June 15, 2015 4:42 PM
> To: Yehuda Yitschak; qemu-devel@nongnu.org
> Cc: Yuval Caduri; Shadi Ammouri
> Subject: Re: Assigning an eth port to a guest VM
>
> Hi
,
> Gerd
>
> The following changes since commit 0a2df857a7038c75379cc575de5d4be4c0ac629e:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into
> staging (2015-06-12 15:39:05 +0100)
>
> are available in the git repository at:
>
>
&g
On 15 June 2015 at 18:03, Peter Maydell wrote:
> On 15 June 2015 at 13:27, Gerd Hoffmann wrote:
>>
>> audio: remove obsolete backends (esd, fmod, winwave).
>> audio: stop using global variables, small fixes.
>> audio: remove some ob
On Mon, 2015-06-15 at 16:52 +, Yehuda Yitschak wrote:
>
> From: Eric Auger
> Sent: Monday, June 15, 2015 4:42 PM
> To: Yehuda Yitschak; qemu-devel@nongnu.org
> Cc: Yuval Caduri; Shadi Ammouri
> Subject: Re: Assigning an eth port to a guest VM
>
> Hi Ye
The THP faults were not propagating the original fault address. The latest
version of the API with uffd.arg.pagefault.address is supposed to propagate the
full address through THP faults.
This was not a kernel crashing bug and it wouldn't risk to corrupt
user memory, but it would cause a SIGBUS fa
Blocking reads can easily use exclusive wakeups. Poll in theory could
too but there's no poll_wait_exclusive in common code yet.
If a poll() non-exclusive waitqueue is encountered before the
exclusive readblocking waitqueue, then everything will be waken. If a
read exclusive waitqueue is encounter
This is only simple to achieve if the userfault is going to return to
userland (not to the kernel) because we can avoid returning
VM_FAULT_RETRY despite we temporarily released the mmap_sem. The fault
would just be retried by userland then. This is safe at least on x86
and powerpc (the two archs wi
UFFDIO_API was already forced before read/poll could work. This
makes the code more strict to force it also for all other ioctls.
All users would already have been required to call UFFDIO_API before
invoking other ioctls but this makes it more explicit.
This will ensure we can change all ioctls (
During the refile in userfaultfd_read both waitqueues could look empty
to the lockless wake_userfault(). Use a seqcount to prevent this false
negative that could leave an userfault blocked.
Signed-off-by: Andrea Arcangeli
---
fs/userfaultfd.c | 26 --
1 file changed, 24 i
This is an incremental update to the userfaultfd code in -mm.
This fixes two bugs that could cause some malfunction (but nothing
that could cause memory corruption or kernel crashes of any sort,
neither in kernel nor userland).
This also introduces some enhancement: gdb now runs fine, signals can
The architecture defines that when taking an exception trying to
access a coprocessor register, the "preferred return address" for
the exception is the address of the instruction that caused the
exception. Correct an off-by-4 error which meant we were returning
the address after the instruction for
From: Andrew Jones
SPCR is the Serial Port Console Redirection Table. See the document
linked from http://uefi.org/acpi. For serial port types, "Interface
Type", see the documentation for the Debug Port Table 2 (DBG2).
Signed-off-by: Andrew Jones
Tested-by: Shannon Zhao
Reviewed-by: Igor Mamme
From: Johan Karlsson
This patch fixes so that gic_update always updates all the cores with
new pending irq states. If the function returns early it is possible
to get interrupts that has already been acknowledged.
Signed-off-by: Johan Karlsson
[PMM: rebased to apply to current master]
Reviewed
This reverts commit 855c5a9026b0fce58c8de5382ef8ce00f74c1331 and
adapts fs/userfaultfd.c to use the old version of that function.
It didn't look robust to call __wake_up_common with "nr == 1" when we
absolutely require wakeall semantics, but we've full control of what
we insert in the two waitqueu
From: Andrew Jones
Signed-off-by: Andrew Jones
Tested-by: Shannon Zhao
Reviewed-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
Message-id: 1433929959-29530-3-git-send-email-drjo...@redhat.com
Signed-off-by: Peter Maydell
---
hw/arm/virt-acpi-build.c | 43
From: Eric Auger
commit ac9d32e39664e060cd1b538ff190980d57ad69e4 had the consequence to
register the do_cpu_reset after the rom_reset one. Hence they get
executed in the wrong order. This commit restores the registration of
do_cpu_reset in arm_load_kernel.
Signed-off-by: Eric Auger
Reported-by:
From: Peter Crosthwaite
For processors that support MPUs, add a property to de-feature it. This
is similar to the implementation of the EL3 feature.
The processor definition in init sets ARM_FEATURE_MPU if it can support
an MPU. post_init exposes the property, defaulting to true. If cleared
by t
From: Sergey Fedorov
According to ARMv8 ARM, there are additional aliases to MIDR system register in
AArch32 state. So add them to the list.
Signed-off-by: Sergey Fedorov
Message-id: 1433321048-23793-3-git-send-email-serge.f...@gmail.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
This test allocates two virtual areas and bounces the physical memory
across the two virtual areas using only userfaultfd.
This exposed a race condition in the refile of the userfault in
userfaultfd_read and an alignment issue with the address returned to
userland with THP enabled. It also allowed
From: Peter Crosthwaite
Add a boolean for indicating uniprocessors with MP extensions. This
drives the U bit in MPIDR. Prepares support for Cortex-R5.
Signed-off-by: Peter Crosthwaite
Message-id:
a70a80583df265e0174f01fa1fc92b33ea6d1db5.1434066412.git.peter.crosthwa...@xilinx.com
Reviewed-by:
From: Peter Crosthwaite
V6+ PMSA and VMSA share some common registers that are currently
in the VMSA definition block. Split them out into a new def that can
be shared to PMSA.
Signed-off-by: Peter Crosthwaite
Message-id:
284db78a43c63c9bfbb60de539672c361bcb6af8.1434066412.git.peter.crosthwa..
From: Peter Crosthwaite
If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP.
The def is done separately from VMSA registers group as it is affected
by both the OMAP/STRONGARM RW errata and the MIDR backgrounding.
Signed-off-by: Peter Crosthwaite
Message-id:
b03fea3840207edf63
From: Peter Crosthwaite
This get_phys_addr is really for pmsav5. Rename it accordingly.
Reviewed-by: Peter Maydell
Signed-off-by: Peter Crosthwaite
Message-id:
bf4b019aa87d682a45998105ef8e4d4e97a5e117.1434066412.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
---
target-arm/he
From: Alex Bennée
This isn't used by any of the code. In fact it looks like it was never
used as it came in with ARMv7 support.
Signed-off-by: Alex Bennée
Message-id: 1434020015-8868-1-git-send-email-alex.ben...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target-ar
Update the pxa2xx_mmci device to stop using the old_mmio read
and write callbacks in its MemoryRegionOps. This actually
simplifies the code because the separate byte/halfword/word
access functions were all calling into a single function to
do the work anyway.
Signed-off-by: Peter Maydell
Reviewed
From: Peter Crosthwaite
Currently, the return code for get_phys_addr is overloaded for both
success/fail and FSR value return. This doesn't handle the case where
there is an error with a 0 FSR. This case exists in PMSAv7.
So rework get_phys_addr and friends to return a success/failure boolean
re
From: Sergey Fedorov
According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let
REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57.
Signed-off-by: Sergey Fedorov
Message-id: 1433321048-23793-2-git-send-email-serge.f...@gmail.com
Reviewed-by: Peter
From: Peter Crosthwaite
These registers are VMSA specific so they should be conditional on
VMSA (i.e. !MPU).
Signed-off-by: Peter Crosthwaite
Message-id:
7bb8843e45f2635c6b7a583c5bb5da51ed4442a0.1434066412.git.peter.crosthwa...@xilinx.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydel
The pxa2xx-ssp device is already a QOM device but is still
using the old-style register_savevm(); convert to VMState.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
Message-id: 1434117989-7367-5-git-send-email-peter.mayd...@linaro.org
---
hw/arm/pxa2xx.c | 91 +-
The pxa2xx custom coprocessor registers in cp6 and cp14 do device
accesses, so mark the non-constant regs as ARM_CP_IO so that
icount works correctly and doesn't abort.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
Message-id: 1434117989-7367-2-git-send-email-peter.mayd...@linaro.o
From: Shannon Zhao
Since commit e353102(target-arm: cpu64: Add support for Cortex-A53) has
added Cortex-A53 cpu support for target-arm, this patch just enables it
for kvm-arm.
Here adding XGENE_POTENZA just makes the enum continuous.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Mes
Convert the pxa2xx-fir device to QOM, including using a
VMState for its migration info.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
Message-id: 1434117989-7367-3-git-send-email-peter.mayd...@linaro.org
---
hw/arm/pxa2xx.c | 141 ++-
From: Pavel Fedin
When we're using KVM, the kernel's internal idea of the MPIDR
affinity fields must match the values we tell it for the guest
vcpu cluster configuration in the device tree. Since at the moment
the kernel doesn't support letting userspace tell it the correct
affinity fields to use
The pxa2xx_ssp device was missing a reset method; add one.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
Message-id: 1434117989-7367-4-git-send-email-peter.mayd...@linaro.org
---
hw/arm/pxa2xx.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/arm/pxa2xx.
From: Sergey Fedorov
Since ARMv7 with LPAE support, a supersection short translation table
descriptor has had extended base address fields which hold bits 39:32 of
translated address. These fields are IMPDEF in ARMv6 and ARMv7 without
LPAE support.
Signed-off-by: Sergey Fedorov
Message-id: 1433
The old ARMv5-style page table format includes a kind of second level
descriptor named the "extended small page" format, whose primary purpose
is to allow specification of the TEX memory attribute bits on a 4K page.
This exists on ARMv6 and also (as an implementation extension) on XScale
CPUs; it's
From: Shannon Zhao
Add Shannon Zhao as the maintainer for the ARM ACPI Subsystem.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Claudio Fontana
Acked-by: Peter Maydell
Message-id: 1433248318-6076-1-git-send-email-shannon.z...@linaro.org
Signed-off-by: Peter Maydell
--
Mishmash of target-arm stuff; nothing earth-shaking.
-- PMM
The following changes since commit b500e4db8e3e0b5f41a2dd14e2001200e5fc7d6b:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-audio-20150615-1' into
staging (2015-06-15 16:15:32 +0100)
are available in the git rep
From: "Aurelio C. Remonda"
Create an ARM_FEATURE_THUMB_DSP controlling the Thumb encodings of
the 85 DSP instructions (these are all Thumb2). This is enabled for
all non-M-profile CPUs with Thumb2 support, as the instructions are
mandatory for R and A profiles. On M profile they are optional and
From: Shannon Zhao
Add cortex-a53 cpu support in machine virt, so it can be used for TCG
and KVM.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Peter Maydell
Message-id: 1433207452-4512-3-git-send-email-shannon.z...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/v
fimd_swap_data() includes code to reverse the bits in a
64-bit integer, but an off-by-one error meant that it would
try to shift off the top of the integer. Correct the bug
(spotted by Coverity).
Signed-off-by: Peter Maydell
Message-id: 1432912615-23107-1-git-send-email-peter.mayd...@linaro.org
-
According to PAPR+ 3.2.2.2, the TCE is implemented as follows:
bits 0-51: real page number
bits 52-61: reserved for future use
bits 62-63: page protection (read-only, write-only, read-write)
Possible values for the protection bits are necessarly non-zero and thus
H_PUT_TCE
From: Alex Williamson
Sent: Monday, June 15, 2015 8:15 PM
To: Yehuda Yitschak
Cc: Eric Auger; qemu-devel@nongnu.org; Yuval Caduri; Shadi Ammouri
Subject: Re: Assigning an eth port to a guest VM
On Mon, 2015-06-15 at 16:52 +, Yehuda Yitschak wrote:
>>
On 06/15/2015 07:45 PM, Yehuda Yitschak wrote:
>
>
> From: Alex Williamson
> Sent: Monday, June 15, 2015 8:15 PM
> To: Yehuda Yitschak
> Cc: Eric Auger; qemu-devel@nongnu.org; Yuval Caduri; Shadi Ammouri
> Subject: Re: Assigning an eth port to a guest VM
>
On Fri, Jun 12, 2015 at 06:21:35PM +0200, Igor Mammedov wrote:
> On Fri, 12 Jun 2015 15:55:22 +0100
> Peter Maydell wrote:
>
> > On 1 June 2015 at 11:15, wrote:
> > > From: Shannon Zhao
> > >
> > > Add GICv2m description in ACPI MADT table, so guest can use MSI when
> > > booting with ACPI.
>
On Jun 15, 2015 7:22 AM, "Andrea Arcangeli" wrote:
>
> + if (cmd != UFFDIO_API) {
> + if (ctx->state == UFFD_STATE_WAIT_API)
> + return -EINVAL;
> + BUG_ON(ctx->state != UFFD_STATE_RUNNING);
> + }
NAK.
Once again: we don't add BUG_ON(
On Jun 15, 2015 7:22 AM, "Andrea Arcangeli" wrote:
>
> Blocking reads can easily use exclusive wakeups. Poll in theory could
> too but there's no poll_wait_exclusive in common code yet.
NAK.
Tie while commit message is crap, and so us the comment
No, your really cannot "easily use exclusive wai
On Mon, Jun 15, 2015 at 05:59:06PM +0100, Peter Maydell wrote:
> On 15 June 2015 at 17:32, Andrew Jones wrote:
> > On Mon, Jun 15, 2015 at 06:10:25PM +0200, Michael S. Tsirkin wrote:
> >> On Mon, Jun 15, 2015 at 04:45:58PM +0100, Peter Maydell wrote:
> >> > I'm still confused about when fields in
On Mon, 2015-06-15 at 17:45 +, Yehuda Yitschak wrote:
>
> From: Alex Williamson
> Sent: Monday, June 15, 2015 8:15 PM
> To: Yehuda Yitschak
> Cc: Eric Auger; qemu-devel@nongnu.org; Yuval Caduri; Shadi Ammouri
> Subject: Re: Assigning an eth port to a gu
Am 15.06.2015 um 17:57 schrieb Aurelien Jarno:
> The I/O-Interruption Subclass field corresponds to bits 2 to 5 (BE
> notation) of the Interruption-Identification Word. The value should
> be shift by 27 instead of 24.
>
> Cc: Christian Borntraeger
> Cc: Cornelia Huck
> Cc: Alexander Graf
> Sign
On 15 June 2015 at 16:05, Alex Züpke wrote:
> Here's a simple IPI tester sending IPIs from CPU #0 to CPU #1 in an endless
> loop.
> The IPIs are delayed until the timer interrupt triggers the main loop.
>
> http://www.cs.hs-rm.de/~zuepke/qemu/ipi.elf
> 3174 bytes, md5sum 8d73890a60cd9b24a4f913950
Document the behavior of fw_cfg_modify_iXX() for leak-less updating
of integer-type blobs.
Currently only fw_cfg_modify_i16() is coded, but 32- and 64-bit versions
may be added later if necessary..
Signed-off-by: Gabriel Somlo
---
docs/specs/fw_cfg.txt | 11 +++
1 file changed, 11 inser
Implement the YIELD instruction in the ARM and Thumb translators to
actually yield control back to the top level loop rather than being
a simple no-op. (We already do this for A64.)
Signed-off-by: Peter Maydell
---
target-arm/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a
This patchset makes the ARM and Thumb encodings of the YIELD hint
instruction in the ARM cause the TCG CPU to yield control back
to the top level loop. This brings them into line with the A64
encoding which already did this.
Patch 1 splits out DISAS_YIELD from DISAS_WFE, because although
we curren
Currently we use DISAS_WFE for both WFE and YIELD instructions.
This is functionally correct because at the moment both of them
are implemented as "yield this CPU back to the top level loop so
another CPU has a chance to run". However it's rather confusing
that YIELD ends up calling HELPER(wfe), an
On 15 June 2015 at 16:05, Alex Züpke wrote:
> Am 15.06.2015 um 16:51 schrieb Peter Maydell:
>> On 15 June 2015 at 15:44, Alex Züpke wrote:
>>> Am 12.06.2015 um 20:03 schrieb Peter Maydell:
Probably the best approach would be to have something in
arm_cpu_set_irq() which says "if we are C
Am 15.06.2015 um 20:58 schrieb Peter Maydell:
On 15 June 2015 at 16:05, Alex Züpke wrote:
Am 15.06.2015 um 16:51 schrieb Peter Maydell:
On 15 June 2015 at 15:44, Alex Züpke wrote:
Am 12.06.2015 um 20:03 schrieb Peter Maydell:
Probably the best approach would be to have something in
arm_cpu_
This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3,
the main differences being the DSP instructions and an optional FPU.
Created an ARM_FEATURE_THUMB_DSP to be added to any non-M thumb2-compatible
CPU that uses DSP instructions, and manually added it to the M4 in its initfn.
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