Re: [Qemu-devel] clang -fsanitize=undefined warnings in the string visitors

On 11 May 2015 at 10:07, Paolo Bonzini wrote: > On 11/05/2015 10:53, Peter Maydell wrote: >> Paolo: ping^2, since we're out of release freeze now? > > I have some patches, but this isn't really the best time for me to post > them... Ping...has the timing improved? thanks -- PMM

[Qemu-devel] [PATCH v4 1/4] target-arm: Add GIC phandle to VirtBoardInfo

Instead of passing the GIC phandle around between functions, add it to the VirtBoardInfo just like we do for the clock_phandle. We are about to add the v2m phandle as well, and it's easier not having to pass around a bunch of phandles, return multiple values from functions, etc. Reviewed-by: Eric

[Qemu-devel] [PATCH v4 0/4] Add support for for GICv2m and MSIs to arm-virt

Now when we have a host generic PCIe controller in the virt board, it would be nice to be able to use MSIs so that we can eventually enable VHOST with KVM. With these patches you can use MSIs with TCG and with KVM, but you still need some fixes for the mapping of the IRQ index to the GSI number fo

Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase

* Peter Maydell (peter.mayd...@linaro.org) wrote: > On 29 May 2015 at 11:34, Dr. David Alan Gilbert wrote: > > It's the destination I'm worried about here, not the source; lets say > > you have two devices, a & b. 'a' gets serialised, but then 'b' finds > > it has to wait, so we return to running

Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase

Am 29.05.2015 um 12:34 hat Dr. David Alan Gilbert geschrieben: > * Kevin Wolf (kw...@redhat.com) wrote: > > Am 29.05.2015 um 11:38 hat Dr. David Alan Gilbert geschrieben: > > > * Kevin Wolf (kw...@redhat.com) wrote: > > > > Am 29.05.2015 um 10:33 hat Dr. David Alan Gilbert geschrieben: > > > > > *

[Qemu-devel] [PATCH v4 2/4] arm_gicv2m: Add GICv2m widget to support MSIs

The ARM GICv2m widget is a little device that handles MSI interrupt writes to a trigger register and ties them to a range of interrupt lines wires to the GIC. It has a few status/id registers and the interrupt wires, and that's about it. A board instantiates the device by setting the base SPI num

[Qemu-devel] [PATCH v4 4/4] target-arm: Add the GICv2m to the virt board

Add a GICv2m device to the virt board to enable MSIs on the generic PCI host controller. We allocate 64 SPIs in the IRQ space for now (this can be increased/decreased later) and map the GICv2m right after the GIC in the memory map. Reviewed-by: Eric Auger Signed-off-by: Christoffer Dall --- Cha

[Qemu-devel] [PULL 0/1] Block QAPI, monitor, command line patches

The following changes since commit ba7c388963e099c0d2cedb7f048e3074725d: Merge remote-tracking branch 'remotes/spice/tags/pull-spice-20150529-1' into staging (2015-05-29 10:17:49 +0100) are available in the git repository at: git://repo.or.cz/qemu/armbru.git tags/pull-block-

Re: [Qemu-devel] [RFC] extensions to the -m memory option

On 29/05/2015 00:11, Liviu Ionescu wrote: > for more flexibility, in the new Cortex-M implementation I'm working on, I > can overwrite the vendor defined MCU internal SRAM size by using: > > -m sizeK > > I'm trying to find a way to also overwrite the internal flash size and the > first

[Qemu-devel] [PULL 1/1] qapi: add dirty bitmap status

From: John Snow Bitmaps can be in a handful of different states with potentially more to come as we tool around with migration and persistence patches. Management applications may need to know why certain bitmaps are unavailable for various commands, e.g. busy in another operation, busy being mi

Re: [Qemu-devel] [PATCH] configure: don't apply -O2 if extra-cflags sets -O

On 29/05/2015 12:56, Alex Bennée wrote: > If your trying to debug and want to force -O0 then don't allow the > configure script to try and set -O2. You can use --enable-debug but that > enables a lot more stuff by default. > > Signed-off-by: Alex Bennée > --- > configure | 5 - > 1 file ch

Re: [Qemu-devel] clang -fsanitize=undefined warnings in the string visitors

On 29/05/2015 12:56, Peter Maydell wrote: >>> >> Paolo: ping^2, since we're out of release freeze now? >> > >> > I have some patches, but this isn't really the best time for me to post >> > them... > Ping...has the timing improved? Almost. :) Next week, promised. Paolo

Re: [Qemu-devel] [PATCH v6 01/13] block: Add op blocker type "device IO"

On Thu, May 28, 2015 at 3:05 PM, Fam Zheng wrote: > On Thu, 05/28 13:19, Paolo Bonzini wrote: >> >> >> On 28/05/2015 13:11, Fam Zheng wrote: >> > > Whoever uses ioeventfd needs to implement pause/resume, yes---not just >> > > dataplane, also "regular" virtio-blk/virtio-scsi. >> > > >> > > However,

Re: [Qemu-devel] [PATCH 0/3] implement a new icount_no_rt mode

On 29/05/2015 10:54, Victor Clement wrote: > - Mail original - >> De: "Paolo Bonzini" >> À: "Victor CLEMENT" , qemu-devel@nongnu.org >> Cc: "francois guerret" >> Envoyé: Mercredi 27 Mai 2015 14:52:55 >> Objet: Re: [Qemu-devel] [PATCH 0/3] implement a new icount_no_rt mode >> >> [...] Or

Re: [Qemu-devel] [PATCH 0/9] Miscellaneous error reporting improvements

Kevin Wolf writes: > Am 28.05.2015 um 14:21 hat Markus Armbruster geschrieben: >> Touches vl.c, which gives me pretext to ask Paolo: would you be >> willing to take this through your tree? Or should I take it through >> mine? > > After this series we have an ugly half-converted state where > qem

Re: [Qemu-devel] [PATCH] pc: acpi: keep pvpanic backward compatible

2015-05-29 10:51+0200, Igor Mammedov: > On Wed, 27 May 2015 18:29:17 +0200 > Radim Krčmář wrote: > > In the old times, we always had pvpanic in ACPI and a _STA function told > > the guest not to use it. Now, we only include pvpanic in ACPI if it is > > enabled, so the _STA function is useless fro

Re: [Qemu-devel] [RFC PATCH 03/12] blockdev: Lock BDS during internal snapshot transaction

On 29/05/2015 12:53, Fam Zheng wrote: > Signed-off-by: Fam Zheng > --- > blockdev.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/blockdev.c b/blockdev.c > index 5eaf77e..46f8d60 100644 > --- a/blockdev.c > +++ b/blockdev.c > @@ -1262,6 +1262,7 @@ typedef struct InternalSnapsh

Re: [Qemu-devel] [RFC PATCH 01/12] block: Use bdrv_drain to replace uncessary bdrv_drain_all

On 29/05/2015 12:53, Fam Zheng wrote: > There callers work on a single BlockDriverState subtree, where using > bdrv_drain() is more accurate. > > Signed-off-by: Fam Zheng > --- > block.c | 6 +++--- > block/snapshot.c | 2 +- > migration/block.c | 2 +- > 3 files changed, 5 insertio

Re: [Qemu-devel] [PATCH 2/3] migration: create migration event

On Wed, May 20, 2015 at 17:35:23 +0200, Juan Quintela wrote: > We have one argument that tells us what event has happened. > > Signed-off-by: Juan Quintela > --- > docs/qmp/qmp-events.txt | 16 > migration/migration.c | 12 > qapi/event.json | 14 +

Re: [Qemu-devel] [PATCH V15 4/5] i386: add a Virtual Machine Generation ID device

On Mon, 27 Apr 2015 14:19:50 +0300 Gal Hammer wrote: > Based on Microsoft's sepecifications (paper can be dowloaded from > http://go.microsoft.com/fwlink/?LinkId=260709), add a device > description to the SSDT ACPI table and its implementation. > > The GUID is set using a global "vmgenid.uuid" p

[Qemu-devel] [PATCH 2/2] virtio-gpu/2d: add virtio gpu core code

This patch adds the core code for virtio gpu emulation, covering 2d support. Written by Dave Airlie and Gerd Hoffmann. Signed-off-by: Dave Airlie Signed-off-by: Gerd Hoffmann --- hw/display/Makefile.objs | 2 + hw/display/virtio-gpu.c| 918 ++

[Qemu-devel] [PATCH 1/2] virtio: update headers, add virtio-gpu (2d)

Signed-off-by: Gerd Hoffmann --- include/standard-headers/linux/virtio_gpu.h | 204 include/standard-headers/linux/virtio_ids.h | 1 + 2 files changed, 205 insertions(+) create mode 100644 include/standard-headers/linux/virtio_gpu.h diff --git a/include/standard-h

[Qemu-devel] [PATCH 0/2] virtio-gpu/2d: add virtio gpu

Hi, This patch brings basic (2d) virtio-gpu support. Again, as with the virtio-input patches, only for non-pci transports for now. virtio-pci support has dependencies on not-yet merged virtio 1.0 patches. First patch brings the header file, this is generated by scripts/update-linux-headers.sh

Re: [Qemu-devel] [PATCH v2 0/4] tighten conditions for board-implied FDC in pc-q35-2.4+

Laszlo Ersek writes: > Version 2 of > . > > Changes are broken out per-patch; the cumulative changes are: > - more granular structure (several patches in place of 1), > - rename "force_fdctrl" parameter to "create_fdctrl", > -

Re: [Qemu-devel] [RFC PATCH 00/12] block: Protect block jobs with lock / unlock API

On 29/05/2015 12:53, Fam Zheng wrote: > This is the partial work to introduce bdrv_lock / bdrv_unlock and use them in > block jobs where exclusive access to a BDS is necessary. It address the same > category of problems as [1] with a different API, as the idea proposed by > Paolo > and Kevin. >

Re: [Qemu-devel] [PATCH v2 4/4] qmp/hmp: add rocker device support

On Tue, May 19, 2015 at 08:13:18PM -0700, sfel...@gmail.com wrote: > From: Scott Feldman > > v2: > > Address review comments from Stefan Hajnoczi: > > - Add missing qapi/rocker.json file. > - Use PRIx64 for print uint64 value > - when CONFIG_ROCKER is not defined, build qmp-norocker.o stub u

Re: [Qemu-devel] [PATCH] Use Aff1 with mpidr

Hello! > That's what I see as correct way to go > and along the way teach KVM to not derive mpidr encoding from vcpuid > and use QEMU provided mpidr value, that way mpidr would be consistent. Yes, and this would make modelling of real hardware working much better. However, unfortunately, i hav

Re: [Qemu-devel] [PATCH 8/8] qemu-iotests: expand test 093 to support group throttling

On Tue, May 19, 2015 at 03:24:36PM +0300, Alberto Garcia wrote: > @@ -32,26 +34,31 @@ class ThrottleTestCase(iotests.QMPTestCase): > raise Exception("Device not found for blockstats: %s" % device) > > def setUp(self): > -self.vm = iotests.VM().add_drive(self.test_img) > +

Re: [Qemu-devel] [Qemu-block] [PATCH 4/8] throttle: Add throttle group support

On Tue, May 19, 2015 at 03:24:32PM +0300, Alberto Garcia wrote: > The throttle group support use a cooperative round robin scheduling > algorithm. > > The principles of the algorithm are simple: > - Each BDS of the group is used as a token in a circular way. > - The active BDS computes if a wait m

Re: [Qemu-devel] [PATCH 6/8] throttle: add the name of the ThrottleGroup to BlockDeviceInfo

On Tue, May 19, 2015 at 03:24:34PM +0300, Alberto Garcia wrote: > Signed-off-by: Alberto Garcia > --- > block/qapi.c | 3 +++ > hmp.c| 6 -- > qapi/block-core.json | 4 +++- > 3 files changed, 10 insertions(+), 3 deletions(-) Reviewed-by: Stefan Hajnoczi pgpS2RCli6

Re: [Qemu-devel] [PATCH 5/8] throttle: acquire the ThrottleGroup lock in bdrv_swap()

On Tue, May 19, 2015 at 03:24:33PM +0300, Alberto Garcia wrote: > bdrv_swap() touches the fields of a BlockDriverState that are > protected by the ThrottleGroup lock. Although those fields end up in > their original place, they are temporarily swapped in the process, > so there's a chance that an o

Re: [Qemu-devel] [PATCH 7/8] throttle: Update throttle infrastructure copyright

On Tue, May 19, 2015 at 03:24:35PM +0300, Alberto Garcia wrote: > Signed-off-by: Alberto Garcia > --- > include/qemu/throttle.h | 8 +--- > util/throttle.c | 8 +--- > 2 files changed, 10 insertions(+), 6 deletions(-) Reviewed-by: Stefan Hajnoczi pgpWoNuVgedQD.pgp Description:

Re: [Qemu-devel] [PATCH v6 1/3] target-mips: Misaligned memory accesses for R6

On 27/05/2015 14:29, Yongbok Kim wrote: > @@ -2143,7 +2146,8 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, > t1 = tcg_const_tl(pc_relative_pc(ctx)); > gen_op_addr_add(ctx, t0, t0, t1); > tcg_temp_free(t1); > -tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE

Re: [Qemu-devel] [Qemu-block] [PATCH] mirror: Skip block_job_defer_to_main_loop if already in the main context

On Fri, May 29, 2015 at 10:22:13AM +0800, Fam Zheng wrote: > mirror_exit does the replacing, which requires source and target to be > in sync, unfortunately we can't guarantee that before we have a complete > block pause mechanism. So for non-dataplane block jobs, let's do the old > thing as pre co

[Qemu-devel] [PATCH] QemuOpts: increase number of vm_config_groups

Adding the fw_cfg cmd line support patch by Gabriel L. Somlo hits the limit. Fix this by making the array larger. Cc: Gabriel L. Somlo Signed-off-by: Gerd Hoffmann --- util/qemu-config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/qemu-config.c b/util/qemu-config.c

Re: [Qemu-devel] [Qemu-block] [PATCH] blockdev: no need to drain+flush in hmp_drive_del

On Thu, May 28, 2015 at 04:17:09PM +0200, Paolo Bonzini wrote: > bdrv_close already does that, and in fact hmp_drive_del would need > another drain after the flush (which bdrv_close does). So remove > the duplication. > > Signed-off-by: Paolo Bonzini > --- > blockdev.c | 3 --- > 1 file changed

Re: [Qemu-devel] [PATCH V4 0/4] fw-cfg: cleanup and user-provided command line blobs

On Mo, 2015-05-18 at 09:05 -0400, Gabriel L. Somlo wrote: > Ping? Added to fw_cfg queue.

Re: [Qemu-devel] [PATCH 0/9] Miscellaneous error reporting improvements

Am 29.05.2015 um 13:22 hat Markus Armbruster geschrieben: > Kevin Wolf writes: > > > Am 28.05.2015 um 14:21 hat Markus Armbruster geschrieben: > >> Touches vl.c, which gives me pretext to ask Paolo: would you be > >> willing to take this through your tree? Or should I take it through > >> mine?

Re: [Qemu-devel] [PATCH v3] bios-tables-test: handle false-positive smbios signature matches

On Mo, 2015-05-18 at 08:47 -0400, Gabriel L. Somlo wrote: > It has been reported that sometimes the .rodata section of SeaBIOS, > containing the constant string against which the SMBIOS signature > ends up being compared, also falls within the guest f-segment. In > that case, the test obviously fai

Re: [Qemu-devel] [Qemu-block] [PATCH] blockdev: no need to drain in qmp_block_commit

On Thu, May 28, 2015 at 04:21:43PM +0200, Paolo Bonzini wrote: > Draining is not necessary, I/O can happen as soon as the > commit coroutine yields. Draining can be necessary before > reopening the file for read/write, or while modifying the > backing file chain, but that is done separately in > b

Re: [Qemu-devel] [PATCH] Target-arm: Add the Cortex-M4 CPU

2015-05-28 18:22 GMT-03:00 Liviu Ionescu : > > On 29 May 2015, at 00:09, Aurelio C. Remonda > > wrote: > > The optional FPU in the M4 could be added in the future as a "Cortex-M4F" > > CPU. > > in my implementation I had a single name ("cortex-m4") and some flags, but a > separate name is proba

Re: [Qemu-devel] [PATCH] Use Aff1 with mpidr

On Fri, 29 May 2015 15:26:57 +0300 Pavel Fedin wrote: > Hello! > > > That's what I see as correct way to go > > and along the way teach KVM to not derive mpidr encoding from vcpuid > > and use QEMU provided mpidr value, that way mpidr would be consistent. > > Yes, and this would make modellin

[Qemu-devel] [PULL 35/39] hw/acpi/aml-build: Add Unicode macro

From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Message-id: 1432522520-8068-22-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/acpi/aml-build.c | 17 + i

[Qemu-devel] [PULL 23/39] hw/arm/virt-acpi-build: Generate MADT table

From: Shannon Zhao MADT describes GIC enabled ARM platforms. The GICC and GICD subtables are used to define the GIC regions. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Message-id: 1432522520-8068-10-git-send-email-zhaoshengl...@huawei.com Signed-off-by: P

[Qemu-devel] [PULL 28/39] hw/acpi/aml-build: Make aml_buffer() definition consistent with the spec

From: Shannon Zhao According to ACPI spec, DefBuffer can take two parameters: BufferSize and ByteList. Make it consistent with the spec. Uninitialized buffer could be requested by passing ByteList as NULL to reserve space. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Ig

[Qemu-devel] [PULL 30/39] hw/acpi/aml-build: Add aml_or() term

From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Message-id: 1432522520-8068-17-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/acpi/aml-build.c | 10 ++ include/

[Qemu-devel] [PULL 36/39] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table

From: Shannon Zhao Add PCIe controller in ACPI DSDT table, so the guest can detect the PCIe. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Message-id: 1432522520-8068-23-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 154

[Qemu-devel] [PULL 34/39] hw/acpi/aml-build: Add aml_dword_io() term

From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Message-id: 1432522520-8068-21-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/acpi/aml-build.c

[Qemu-devel] [PULL 31/39] hw/acpi/aml-build: Add aml_lnot() term

From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Message-id: 1432522520-8068-18-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/acpi/aml-build.c

[Qemu-devel] [PULL 32/39] hw/acpi/aml-build: Add aml_else() term

From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Message-id: 1432522520-8068-19-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/acpi/aml-build.c

[Qemu-devel] [PULL 29/39] hw/acpi/aml-build: Add ToUUID macro

From: Shannon Zhao Add ToUUID macro, this is useful for generating PCIe ACPI table. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Message-id: 1432522520-8068-16-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter M

[Qemu-devel] [PULL 37/39] ACPI: split CONFIG_ACPI into 4 pieces

From: Shannon Zhao As core.c, piix4.c, ich9.c and pcihp.c are for x86, add CONFIG_ACPI_X86 to make it only for x86. ARM doesn't support cpu and memory hotplug, add CONFIG_ACPI_CPU_HOTPLUG and CONFIG_ACPI_MEMORY_HOTPLUG to exclude them for target-arm. Signed-off-by: Shannon Zhao Signed-off-by: S

[Qemu-devel] [PULL 20/39] hw/acpi/aml-build: Add aml_interrupt() term

From: Shannon Zhao Add aml_interrupt() for describing device interrupt in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Igor Mammedov Message-id: 1432522520-8068-7-git-send-email-zhaoshengl..

[Qemu-devel] [PULL 22/39] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers

From: Shannon Zhao In the case of mach virt, it is used to set the Hardware Reduced bit and enable PSCI SMP booting through HVC. So ignore FACS and FADT points to DSDT. Update the header definitions for FADT taking into account the new additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h` Sig

[Qemu-devel] [PULL 27/39] hw/arm/virt-acpi-build: Generate MCFG table

From: Shannon Zhao Generate MCFG table for PCIe controller. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Message-id: 1432522520-8068-14-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 23

[Qemu-devel] [PULL 26/39] hw/arm/virt-acpi-build: Generate RSDP table

From: Shannon Zhao RSDP points to RSDT which in turn points to other tables. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Message-id: 1432522520-8068-13-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 35

[Qemu-devel] [PULL 13/39] target-arm: Don't halt on WFI unless we don't have any work

Just NOP the WFI instruction if we have work to do. This doesn't make much difference currently (though it does avoid jumping out to the top level loop and immediately restarting), but the distinction between "halt" and "don't halt" will become more important when the decision to halt requires us t

[Qemu-devel] [PULL 08/39] target-arm: Allow cp access functions to indicate traps to EL2 or EL3

Some coprocessor access functions will need to indicate that the instruction should trap to EL2 or EL3 rather than the default target exception level; add corresponding CPAccessResult enum entries and handling code. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/cpu.

[Qemu-devel] [PULL 38/39] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables

From: Shannon Zhao Initialize VirtGuestInfoState and register a machine_init_done notify to call virt_acpi_build(). Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Message-id: 1432522520-8068-25-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/arm/virt.c |

[Qemu-devel] [PULL 19/39] hw/acpi/aml-build: Add aml_memory32_fixed() term

From: Shannon Zhao Add aml_memory32_fixed() for describing device mmio region in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Reviewed-by: Igor Mammedov Reviewed-by: Michael S.

[Qemu-devel] [PULL 03/39] target-arm: Set correct syndrome for faults on MSR DAIF*, imm

If the SCTLR.UMA trap bit is set then attempts by EL0 to update the PSTATE DAIF bits via "MSR DAIFSet, imm" and "MSR DAIFClr, imm" instructions will raise an exception. We were failing to set the syndrome information for this exception, which meant that it would be reported as a repeat of whatever

[Qemu-devel] [PULL 25/39] hw/arm/virt-acpi-build: Generate RSDT table

From: Shannon Zhao RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86. Here we still use RSDT as UEFI puts ACPI tables below 4G address space, and UEFI ignore the RSDT or XSDT. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Message-id

[Qemu-devel] [PULL 11/39] target-arm: Extend FP checks to use an EL

From: Greg Bellows Extend the ARM disassemble context to take a target exception EL instead of a boolean enable. This change reverses the polarity of the check making a value of 0 indicate floating point enabled (no exception). Signed-off-by: Greg Bellows [PMM: Use a common TB flag field for AA

[Qemu-devel] [PULL 39/39] target-arm: Avoid buffer overrun on UNPREDICTABLE ldrd/strd

A LDRD or STRD where rd is not an even number is UNPREDICTABLE. We were letting this fall through, which is OK unless rd is 15, in which case we would attempt to do a load_reg or store_reg to a nonexistent r16 for the second half of the double-word. Catch the odd-numbered-rd cases and UNDEF them in

[Qemu-devel] [PULL 21/39] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices

From: Shannon Zhao DSDT consists of the usual common table header plus a definition block in AML encoding which describes all devices in the platform. After initializing DSDT with header information the namespace is created which is followed by the device encodings. The devices are described usi

[Qemu-devel] [PULL 10/39] target-arm: Make singlestate TB flags common between AArch32/64

Currently we keep the TB flags PSTATE_SS and SS_ACTIVE in different bit positions for AArch64 and AArch32. Replace these separate definitions with a single common flag in the upper part of the flags word. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/cpu.h

[Qemu-devel] [PULL 00/39] target-arm queue

Main thing here is the ACPI patchset landing... -- PMM The following changes since commit ba7c388963e099c0d2cedb7f048e3074725d: Merge remote-tracking branch 'remotes/spice/tags/pull-spice-20150529-1' into staging (2015-05-29 10:17:49 +0100) are available in the git rep

[Qemu-devel] [PULL 18/39] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM

From: Shannon Zhao Introduce a preliminary framework in virt-acpi-build.c with the main ACPI build functions. It exposes the generated ACPI contents to guest over fw_cfg. The required ACPI v5.1 tables for ARM are: - RSDP: Initial table that points to XSDT - RSDT: Points to FADT GTDT MADT tables

[Qemu-devel] [PULL 07/39] target-arm: Update interrupt handling to use target EL

From: Greg Bellows Updated the interrupt handling to utilize and report through the target EL exception field. This includes consolidating and cleaning up code where needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and do_interrupt was updated to use the target_el exception f

[Qemu-devel] [PULL 33/39] hw/acpi/aml-build: Add aml_create_dword_field() term

From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Message-id: 1432522520-8068-20-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/acpi/aml-build.c

[Qemu-devel] [PULL 04/39] target-arm: Move setting of exception info into tlb_fill

Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation f

[Qemu-devel] [PULL 24/39] hw/arm/virt-acpi-build: Generate GTDT table

From: Shannon Zhao ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Message-id: 1432522520-8068-11-git-se

[Qemu-devel] [PULL 17/39] hw/arm/virt: Record PCIe ranges in MemMapEntry array

From: Shannon Zhao To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Message-id: 1432522520-8068

[Qemu-devel] [PULL 05/39] target-arm: Set exception target EL in tlb_fill

Set the exception target EL for MMU faults in tlb_fill. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/op_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index c9f5821..9ab7c61 100644 --- a/target-arm/op_he

[Qemu-devel] [PULL 09/39] target-arm: Add AArch64 CPTR registers

From: Greg Bellows Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2;

[Qemu-devel] [PULL 15/39] hw/acpi/aml-build: Make enum values to be upper case to match coding style

From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Igor Mammedov Message-id: 1432522520-8068-2-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw/acpi/aml-build.c | 12 hw/i386/acpi-build.c| 58 +++

[Qemu-devel] [PULL 12/39] target-arm: Move TB flags down to fill gap

Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2

[Qemu-devel] [PULL 01/39] target-arm: Add exception target el infrastructure

From: Greg Bellows Add a CPU state exception target EL field that will be used for communicating the EL to which an exception should be routed. Add a disassembly context field for tracking the EL3 architecture needed for determining the target exception EL. Add a target EL argument to the gener

[Qemu-devel] [PULL 02/39] target-arm: Extend helpers to route exceptions

From: Greg Bellows Updated the various helper routines to set the target EL as needed using a dedicated function. Signed-off-by: Greg Bellows Acked-by: Edgar E. Iglesias Message-id: 1429722561-12651-3-git-send-email-greg.bell...@linaro.org [PMM: Also set target_el in fault cases in access_chec

[Qemu-devel] [PULL 14/39] target-arm: Add WFx instruction trap support

From: Greg Bellows Add support for trapping WFI and WFE instructions to the proper EL when SCTLR/SCR/HCR settings apply. Signed-off-by: Greg Bellows [PMM: removed unnecessary tweaking of syn_wfx() prototype; use raise_exception(); don't trap on WFE (and add comment explaining why not); remov

Re: [Qemu-devel] [PATCH] Target-arm: Add the Cortex-M4 CPU

On 29 May 2015 at 13:55, aurelio remonda wrote > Perhaps we could commit this now and add the VFP in the future? That's how we've generally worked, yes -- if you just ask for a "Cortex-A9" or whatever you get the maximum set of features that CPU can support (so always Neon & VFP even if some A9 h

Re: [Qemu-devel] [PATCH 1/1] Fix device listener interface for PCI to PCI bridges

On 05/28/15 17:05, Michael S. Tsirkin wrote: > On Thu, May 28, 2015 at 11:03:07PM +0200, Michael S. Tsirkin wrote: >> On Thu, May 28, 2015 at 03:09:48PM -0400, Don Slutz wrote: >>> On 05/28/15 08:28, Michael S. Tsirkin wrote: On Thu, May 28, 2015 at 07:25:50AM -0400, Don Slutz wrote: > On

Re: [Qemu-devel] [PATCH 8/8] qemu-iotests: expand test 093 to support group throttling

On Fri 29 May 2015 02:32:45 PM CEST, Stefan Hajnoczi wrote: >> def setUp(self): >> -self.vm = iotests.VM().add_drive(self.test_img) >> +self.vm = iotests.VM() >> +for i in range(0, self.max_drives): >> +self.vm.add_drive(self.test_img) > > Unique files are

[Qemu-devel] [PULL 16/39] hw/arm/virt: Move common definitions to virt.h

From: Shannon Zhao Move some common definitions to virt.h. These will be used by generating ACPI tables. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée Message-id: 1432522520-8068-3-git-send-email-zhaoshengl...@huawei.com Signed-off-by: Peter Maydell --- hw

[Qemu-devel] [PULL 06/39] target-arm: Make raise_exception() take syndrome and target EL

Rather than making every caller of raise_exception set the syndrome and target EL by hand, make these arguments to raise_exception() and have that do the job. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/op_helper.c | 68 +---

Re: [Qemu-devel] need to create a qemu account

On Wed, May 27, 2015 at 11:04:35AM -0400, Yaelan Wong wrote: > Hi:  Can someone help me to create my account in Qemu? Done. Stefan pgpfPtrWrrQPj.pgp Description: PGP signature

Re: [Qemu-devel] [PATCH 1/1] net: fix queue's purge on VM stop

On Thu, May 28, 2015 at 10:03:14AM +0200, Thibaut Collet wrote: > For netdev backend with no receive callback, packets must not be enqueued. > When > VM stops the enqueued packets are purged (see fixes ca77d85e1dbf). That > causes a > qemu segfault due to a call of a NULL pointer function. virti

Re: [Qemu-devel] [PATCH 1/5] net: add missing "netmap" to host_net_devices[]

On Wed, May 27, 2015 at 07:39:17PM +0200, Thomas Huth wrote: > On Wed, 27 May 2015 17:16:48 +0100 > Stefan Hajnoczi wrote: > > > Although hmp-commands.hx lists "netmap" as a valid host_net_add type, > > the command rejects it because it's missing from the list. > > > > Signed-off-by: Stefan Hajn

Re: [Qemu-devel] [PULL 0/5] input patch queue.

ull, > Gerd > > The following changes since commit ce0274f730eacbd24c706523ddbbabb6b95d0659: > > Revert "gdbstub: Do not kill target in system emulation mode" (2015-05-28 > 16:57:35 +0100) > > are available in the git repository at: > > git://git.kraxel.org

Re: [Qemu-devel] [PATCH] Use Aff1 with mpidr

Hello! > Well KVM side should be fixed instead of driving us along wrong route. It can be fixed... Perhaps... If kernel developers acknowledge this is a problem, which might not happen. But still we will have older kernels, and what? Don't you want 64-bit ARM KVM work on them? Kind regards,

Re: [Qemu-devel] [PULL 00/12] QOM devices patch queue 2015-05-20

On Wed, May 27, 2015 at 08:16:01PM +0200, Andreas Färber wrote: > Am 21.05.2015 um 13:53 schrieb Daniel P. Berrange: > > On Thu, May 21, 2015 at 12:18:30PM +0100, Peter Maydell wrote: > >> On 20 May 2015 at 16:51, Andreas Färber wrote: > >>> Hello Peter, > >>> > >>> This is my QOM (devices) patch

Re: [Qemu-devel] [PULL 00/12] QOM devices patch queue 2015-05-20

On 29 May 2015 at 14:51, Daniel P. Berrange wrote: > Since that caused failure with glib 2.22 could you revert that switch > to g_assert_null/nonnull. BTW, David Gilbert is looking at whether we can use the glib support to make use of "newer than version X" APIs a compile error everywhere rather

Re: [Qemu-devel] [PATCH v3 11/21] monitor: Propagate errors through invalid_qmp_mode()

On Fri, 29 May 2015 11:56:50 +0200 Markus Armbruster wrote: > Signed-off-by: Markus Armbruster > --- > monitor.c | 18 ++ > 1 file changed, 10 insertions(+), 8 deletions(-) > > diff --git a/monitor.c b/monitor.c > index 61ea346..d336b8f 100644 > --- a/monitor.c > +++ b/monitor.

[Qemu-devel] [PATCH v3 1/4] rocker: Add support for phys name

From: David Ahern v2: Review comment from Stefan Hajnoczi: - use private ROCKER_IFNAMSIZ = 16 to avoid breaking Windows build as Windows does not include v1: Add ROCKER_TLV_CMD_PORT_SETTINGS_PHYS_NAME to port settings. This attribute exports the port name to the guest OS allowing it to n

[Qemu-devel] [PATCH v3 0/4] rocker device updates

From: Scott Feldman v3: Address review comments from Stefan Hajnoczi: - Add missing hw/net/rocker/qmp-norocker.c file. - Add missing curly brackets to a for loop v2: Address some review comments by Stefan Hajnoczi: see individual patches for v1->v2 changes. v1: Some rocker device updates

[Qemu-devel] [PATCH v3 2/4] rocker: update tests using hw-derived interface names

From: Scott Feldman With previous patch to support phy name attribute for each port, the OS can name port interfaces using the hw-derived name. So update rocker tests to use the new hw-derived interface names. Signed-off-by: Scott Feldman Reviewed-by: Stefan Hajnoczi --- tests/rocker/bridge

[Qemu-devel] [PATCH v3 4/4] qmp/hmp: add rocker device support

From: Scott Feldman v3: Address review comments from Stefan Hajnoczi: - Add missing hw/net/rocker/qmp-norocker.c file. - Add missing curly brackets to a for loop v2: Address review comments from Stefan Hajnoczi: - Add missing qapi/rocker.json file. - Use PRIx64 for print uint64 value -

Re: [Qemu-devel] [PATCH 0/9] Miscellaneous error reporting improvements

On 05/29/2015 05:22 AM, Markus Armbruster wrote: > Kevin Wolf writes: > >> Am 28.05.2015 um 14:21 hat Markus Armbruster geschrieben: >>> Touches vl.c, which gives me pretext to ask Paolo: would you be >>> willing to take this through your tree? Or should I take it through >>> mine? >> >> After t

[Qemu-devel] [PATCH v3 3/4] rocker: bring link up/down on PHY enable/disable

From: Scott Feldman When the OS driver enables/disables the port, go ahead and set the port's link status to up/down in response to the change. This more closely emulates real hardware when the PHY for the port is brought up/down and the PHY negotiates carrier (link status) with link partner. I

[Qemu-devel] [PATCH] docs/writing-qmp-commands: fix a typo

s/interation/iteration Signed-off-by: Chen Hanxiao --- docs/writing-qmp-commands.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/writing-qmp-commands.txt b/docs/writing-qmp-commands.txt index f3df206..ab1fdd3 100644 --- a/docs/writing-qmp-commands.txt +++ b/docs/writ

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