Re: [Qemu-devel] [PATCH 01/14] memory: Define API for MemoryRegionOps to take attrs and return status

On 09/04/2015 11:04, Peter Maydell wrote: > We discussed this last time round, I think. Whether structs get > passed in registers depends on the host CPU ABI/calling convention. Because of C++, structs up to pointer size are in practice always passed in registers. 64-bit structs may or may not.

Re: [Qemu-devel] seccomp breakage on arm

On Thu, Apr 09, 2015 at 05=01=31AM +0200, Andreas Färber wrote: > Hello, > > I am seeing the following build failure on openSUSE Tumbleweed armv7l > with --enable-seccomp in v2.3.0-rc2: > > [ 551s] In file included from qemu-seccomp.c:16:0: > [ 551s] /usr/include/libseccomp/seccomp.h:177:23: er

[Qemu-devel] [PATCH RFC] mirror: allow mirroring an intermediate image

This extends the drive-mirror command by allowing it to operate on intermediate images. The device parameter can now take the node name of the image to be mirrored. After the operation its overlay image will point to the new one. Signed-off-by: Alberto Garcia --- block.c | 2 ++ bl

Re: [Qemu-devel] [Qemu-block] Migration sometimes fails with IDE and Qemu 2.2.1

Am 07.04.2015 um 21:01 schrieb Dr. David Alan Gilbert: * Peter Lieven (p...@kamp.de) wrote: Am 07.04.2015 um 17:29 schrieb Dr. David Alan Gilbert: * Peter Lieven (p...@kamp.de) wrote: Hi David, Am 07.04.2015 um 10:43 schrieb Dr. David Alan Gilbert: Any particular workload or reproducer? Wor

[Qemu-devel] [Bug 1422307] Re: qemu-nbd corrupts files

Hi, Was the patch abandoned? I haven't seen any further progress on it for a month... Cheers, -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1422307 Title: qemu-nbd corrupts files Status in QEMU:

Re: [Qemu-devel] [PATCH 07/14] exec.c: Add new address_space_ld*/st* functions

On 8 April 2015 at 12:03, Paolo Bonzini wrote: > > > On 07/04/2015 22:09, Peter Maydell wrote: >> +#ifdef NEED_CPU_H >> +uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, >> +MemTxAttrs attrs, MemTxResult *result); >> +uint32_t address_space_ldl(AddressSpace *a

Re: [Qemu-devel] [PATCH 02/12 v9] linux-user: tilegx: Add target features support within qemu

On 27 March 2015 at 10:49, Chen Gang wrote: > They are for target features within qemu which independent from outside. > > Signed-off-by: Chen Gang > --- > linux-user/tilegx/target_cpu.h | 35 +++ > linux-user/tilegx/target_signal.h | 28 ++ > lin

Re: [Qemu-devel] Qemu binary and list of supported arches

On 9 April 2015 at 09:30, Michal Privoznik wrote: > Dear list, > > when trying to solve this bug [1] I've realized qemu is not reporting a > list of supported architectures for given binary. I mean, we do have > 'query-target' but as I understand it it merely reports only the default > architectur

[Qemu-devel] [PATCH 07/10] linux-headers: update

This updates linux-headers against kvm/queue (commit c7f0cf16df59ac98b58af974c3947cac21402e29), with the exception of avoiding undoing 2106ba30105969262a7810417a57524d9a225b91 ("uapi/virtio_scsi: allow overriding CDB/SENSE size"). Signed-off-by: Cornelia Huck --- linux-headers/asm-arm/kvm.h |

[Qemu-devel] [PATCH 04/10] sclp: sort into categories

Sort the sclp consoles into the input category, just as virtio-serial. Various other sclp devices don't have an obvious category, sort them into misc. Reviewed-by: David Hildenbrand Signed-off-by: Cornelia Huck --- hw/char/sclpconsole-lm.c | 1 + hw/char/sclpconsole.c | 1 + hw/s390x/event

Re: [Qemu-devel] [Qemu-block] Migration sometimes fails with IDE and Qemu 2.2.1

* Peter Lieven (p...@kamp.de) wrote: > Am 07.04.2015 um 21:01 schrieb Dr. David Alan Gilbert: > >* Peter Lieven (p...@kamp.de) wrote: > >>Am 07.04.2015 um 17:29 schrieb Dr. David Alan Gilbert: > >>>* Peter Lieven (p...@kamp.de) wrote: > Hi David, > > Am 07.04.2015 um 10:43 schrieb Dr.

[Qemu-devel] [PATCH 0/2] ARM adaptations for vhost irqfd setup

After the introduction of gicv2m, This series adds missing pieces to run VIRTIO-PCI with vhost back-end on ARM. It is proposed to use the kvm_gsi_direct_mapping modality that sets the irqfd gsi to the MSI data value. With that trick there is no need to create a KVM MSI routing entry featuring a di

Re: [Qemu-devel] [PATCH][XSA-126] xen: limit guest control of PCI command register

On 31 March 2015 at 15:18, Stefano Stabellini wrote: > From: Jan Beulich > > Otherwise the guest can abuse that control to cause e.g. PCIe > Unsupported Request responses (by disabling memory and/or I/O decoding > and subsequently causing [CPU side] accesses to the respective address > ranges), w

Re: [Qemu-devel] [PATCH 3/3] arm: semihosting: Wire up A64 HLT 0xf000

On 9 April 2015 at 18:23, Christopher Covington wrote: > On Fri, Mar 27, 2015 at 12:40 PM, Peter Maydell > wrote: >> You need to have the semihosting_enabled check here rather >> than in the do_interrupt code, because otherwise we won't >> behave correctly in the disabled case. > > Do you have su

Re: [Qemu-devel] 64-bit build of qemu-system-arm with mingw-w64 not functional

Am 09.04.2015 um 21:44 schrieb Liviu Ionescu: hmmm... things get complicated, even messier. :-( Windows support _is_ complicated, yes. There is MinGW32, MinGW-w64, Cygwin, Cygwin64 (list incomplete). And some versions of MinGW-w64 are incompatible because they changed their name mangling, so

[Qemu-devel] [PATCH 09/10] s390x/mmu: Use ioctl for reading and writing from/to guest memory

From: Thomas Huth Add code to make use of the new ioctl for reading from / writing to virtual guest memory. By using the ioctl, the memory accesses are now protected with the so-called ipte-lock in the kernel. Signed-off-by: Thomas Huth Signed-off-by: Cornelia Huck --- target-s390x/cpu.h

[Qemu-devel] [PATCH 00/10] first pile of s390x patches for 2.4

Hi, here's the first pile of pending s390x patches I plan to send when 2.4 opens up. Contents include: - some cleanup patches - sort most of the s390x devices into categories - support for the new STSI post handler, used to insert vm name and friends - support for the new MEM_OP ioctl (includin

[Qemu-devel] [PATCH 05/10] s390x/ipl: sort into categories

The s390 ipl device has no real home (it's not really a storage device), so let's sort it into the misc category. Reviewed-by: David Hildenbrand Signed-off-by: Cornelia Huck --- hw/s390x/ipl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 2e26d2a..132

Re: [Qemu-devel] [PATCH 06/14] exec.c: Make address_space_rw take transaction attributes

On 9 April 2015 at 12:40, Paolo Bonzini wrote: > > > On 09/04/2015 12:43, Peter Maydell wrote: >> > At this point, some memory barriers, basically. >> >> So what distinguishes a device that needs the memory barriers >> and does its accesses via dma_* from a device that doesn't and >> uses address_

[Qemu-devel] [PATCH] fw_cfg: add documentation file (docs/specs/fw_cfg.txt)

This document covers the guest-side hardware interface, as well as the host-side programming API of QEMU's firmware configuration (fw_cfg) device. Signed-off-by: Jordan Justen Signed-off-by: Gabriel Somlo Reviewed-by: Laszlo Ersek --- This was the beginning of a series we've been postponing fo

Re: [Qemu-devel] [PATCH 07/14] exec.c: Add new address_space_ld*/st* functions

On 9 April 2015 at 13:00, Paolo Bonzini wrote: > > > On 09/04/2015 13:49, Peter Maydell wrote: >>> > I think we do not want to expose these at all (or at least, all users >>> > should really be CPUs and hence use *_phys functions). >>> > >>> > S390 is always big-endian, and watch_mem_read/write ca

[Qemu-devel] [PATCH 3/3] pflash_cfi01: add secure property

When this property is set, MMIO accesses are only allowed with the MEMTXATTRS_SECURE attribute. This is used for secure access to UEFI variables stored in flash. Signed-off-by: Paolo Bonzini --- hw/block/pflash_cfi01.c | 26 -- 1 file changed, 20 insertions(+), 6 deletio

[Qemu-devel] [PATCH 1/3] pflash_cfi01: change big-endian property to BIT type

Make this consistent with the secure property, added in the next patches. Signed-off-by: Paolo Bonzini --- hw/block/pflash_cfi01.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index d282695..7507a15 100644 --- a

[Qemu-devel] [RFC PATCH 0/3] pflash_cfi01: allow reading/writing it only in secure mode

This is an example of usage of attributes in a device model. It lets you block flash writes unless the CPU is in secure mode. Enabling it currently requires a -readconfig file: [global] driver = "cfi.pflash01" property = "secure" value = "on" because the driver i

Re: [Qemu-devel] [PATCH 01/14] memory: Define API for MemoryRegionOps to take attrs and return status

On Thu, Apr 09, 2015 at 10:04:39AM +0100, Peter Maydell wrote: > On 9 April 2015 at 09:55, Edgar E. Iglesias wrote: > > Did you consider using a struct here? > > e.g: > > > > typedef struct MemTxAttrs { > > unsigned int secure : 1; > > unsigned int master_id : 10; > > unsigned int etc

Re: [Qemu-devel] [Qemu-block] Migration sometimes fails with IDE and Qemu 2.2.1

Am 09.04.2015 um 15:43 schrieb Dr. David Alan Gilbert: * Peter Lieven (p...@kamp.de) wrote: Am 07.04.2015 um 21:01 schrieb Dr. David Alan Gilbert: * Peter Lieven (p...@kamp.de) wrote: Am 07.04.2015 um 17:29 schrieb Dr. David Alan Gilbert: * Peter Lieven (p...@kamp.de) wrote: Hi David, Am 07

[Qemu-devel] [PATCH 01/10] s390x/kvm: Remove message about "switch_amode" kernel parameter

From: Thomas Huth The "switch_amode" parameter has been removed from the Linux kernel sources since version 3.7 - so QEMU should not advise this parameter nowadays anymore. Signed-off-by: Thomas Huth Acked-by: Cornelia Huck Signed-off-by: Cornelia Huck --- kvm-all.c | 5 - 1 file changed

[Qemu-devel] [PATCH 02/10] virtio-ccw: sort into categories

Sort the various virtio-ccw devices into the same categories as their virtio-pci counterparts. Reviewed-by: David Hildenbrand Signed-off-by: Cornelia Huck --- hw/s390x/virtio-ccw.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index d

Re: [Qemu-devel] [Qemu-block] Migration sometimes fails with IDE and Qemu 2.2.1

On 09/04/2015 14:46, Peter Lieven wrote: >>> >>> >> >> BMDMA is the PCI HBA for IDE, I think it's the default for most >> machines that aren't using the AHCI HBA. >> >> To get ISA, try launching with the machine "isapc" which will force >> it, or add the device manually, it's named "isa-ide". >>

Re: [Qemu-devel] 64-bit build of qemu-system-arm with mingw-w64 not functional

On 9 April 2015 at 18:41, Stefan Weil wrote: > I think -mthreads is essential (needed for thread local storage), > and -D_POSIX=1 is also needed for 64 bit builds. My 64-bit builds worked without either of these things... -- PMM

Re: [Qemu-devel] How address_space_rw works?

On 9 April 2015 at 09:34, Kaiyuan wrote: > Hello, guys > > In my understanding, function exec.c:address_space_rw is used to handle read > and write access requests to address space. In order to check my opinion, I > write guest code and debug Qemu to see the path of code execution. > > If I read o

Re: [Qemu-devel] [PATCH 3/7] throttle: Add throttle group infrastructure tests

On Mon, Mar 30, 2015 at 07:19:41PM +0300, Alberto Garcia wrote: > Signed-off-by: Alberto Garcia > --- > tests/test-throttle.c | 79 > --- > 1 file changed, 69 insertions(+), 10 deletions(-) Reviewed-by: Stefan Hajnoczi pgp_pHMQmN0QF.pgp Descrip

Re: [Qemu-devel] [RFC PATCH 0/3] pflash_cfi01: allow reading/writing it only in secure mode

On 04/09/15 16:43, Paolo Bonzini wrote: > > > On 09/04/2015 15:58, Edgar E. Iglesias wrote: >> Hi Paulo, >> >> How would this work with XIP off the romd region? >> Without s/ns address spaces, CPUs in NS state will be able to execute >> and access data while in ROMD state won't they? > > Good p

Re: [Qemu-devel] [PATCH 03/14] Make CPU iotlb a structure rather than a plain hwaddr

On Tue, Apr 07, 2015 at 09:09:49PM +0100, Peter Maydell wrote: > Make the CPU iotlb a structure rather than a plain hwaddr; > this will allow us to add transaction attributes to it. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > cputlb.c| 4 ++-- > in

[Qemu-devel] [PATCH 1/2] qom: strdup() target property name on object_property_add_alias()

With this, object_property_add_alias() callers can safely free the target property name, like what already happens with the 'name' argument to all object_property_add*() functions. Signed-off-by: Eduardo Habkost --- qom/object.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --

Re: [Qemu-devel] 64-bit build of qemu-system-arm with mingw-w64 not functional

> On 09 Apr 2015, at 20:58, Peter Maydell wrote: > > On 9 April 2015 at 18:41, Stefan Weil wrote: >> I think -mthreads is essential (needed for thread local storage), >> and -D_POSIX=1 is also needed for 64 bit builds. > > My 64-bit builds worked without either of these things... hmmm... thin

Re: [Qemu-devel] [PATCH 06/14] exec.c: Make address_space_rw take transaction attributes

On 9 April 2015 at 10:59, Edgar E. Iglesias wrote: > On Tue, Apr 07, 2015 at 09:09:52PM +0100, Peter Maydell wrote: >> Make address_space_rw take transaction attributes, rather >> than always using the 'unspecified' attributes. > > Reviewed-by: Edgar E. Iglesias > > I guess that we eventually wil

Re: [Qemu-devel] [PATCH 04/14] Add MemTxAttrs to the IOTLB

On Tue, Apr 07, 2015 at 09:09:50PM +0100, Peter Maydell wrote: > Add a MemTxAttrs field to the IOTLB, and allow target-specific > code to set it via a new tlb_set_page_with_attrs() function; > pass the attributes through to the device when making IO accesses. > > Signed-off-by: Peter Maydell Rev

Re: [Qemu-devel] [Qemu-block] Migration sometimes fails with IDE and Qemu 2.2.1

Am 09.04.2015 um 14:49 schrieb Peter Lieven: Am 07.04.2015 um 21:01 schrieb Dr. David Alan Gilbert: * Peter Lieven (p...@kamp.de) wrote: Am 07.04.2015 um 17:29 schrieb Dr. David Alan Gilbert: * Peter Lieven (p...@kamp.de) wrote: Hi David, Am 07.04.2015 um 10:43 schrieb Dr. David Alan Gilbert

Re: [Qemu-devel] [PATCH] aio: strengthen memory barriers for bottom half scheduling

On Thu, Apr 09, 2015 at 11:21:10AM +0200, Paolo Bonzini wrote: > There are two problems with memory barriers in async.c. The fix is > to use atomic_xchg in order to achieve sequential consistency between > the scheduling of a bottom half and the corresponding execution. > > First, if bh->schedule

Re: [Qemu-devel] [PATCH v6 0/8] QEMU memory hot unplug support

On 04/09/2015 04:28 PM, Igor Mammedov wrote: On Thu, 9 Apr 2015 09:16:21 +0800 Zhu Guihua wrote: On 04/08/2015 06:47 PM, Paulo Ricardo Paz Vital wrote: On Wed, 2015-04-08 at 11:52 +0200, Michael S. Tsirkin wrote: On Wed, Apr 08, 2015 at 05:49:42PM +0800, Zhu Guihua wrote: Ping... It's onl

Re: [Qemu-devel] [PATCH 0/3] Add support for for GICv2m and MSIs to arm-virt

On Wed, Apr 08, 2015 at 10:31:53PM +0100, Peter Maydell wrote: > On 8 April 2015 at 22:20, Christoffer Dall > wrote: > > Now when we have a host generic PCIe controller in the virt board, it > > would be nice to be able to use MSIs so that we can eventually enable > > VHOST with KVM. > > > > With

Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table

On 9 April 2015 at 17:00, Laszlo Ersek wrote: > On 04/09/15 15:59, Peter Maydell wrote: >> On 9 April 2015 at 14:51, Igor Mammedov wrote: >>> On Thu, 9 Apr 2015 14:27:58 +0100 >>> Peter Maydell wrote: >>> On 9 April 2015 at 14:17, Igor Mammedov wrote: > On Thu, 09 Apr 2015 13:50:52 +01

[Qemu-devel] Wiki account request

Hi guys, This is my first post here, so nice to meet you everyone! I’m wondering if some of you can create a Wiki account for me. I want to add installation guide (e.g. dependencies list etc) for Arch Linux on http://wiki.qemu.org/Hosts/Linux . Thanks.

Re: [Qemu-devel] [PATCH 07/14] exec.c: Add new address_space_ld*/st* functions

On 09/04/2015 14:38, Peter Maydell wrote: > They need to be in memory.h because cpu-all.h doesn't have > all the typedefs. Also, memory.h seems to me clearly the > best place, since it's where we declare the MemoryRegion > and AddressSpace related functions. > > It's certainly true that using ta

Re: [Qemu-devel] [RFC PATCH 0/3] pflash_cfi01: allow reading/writing it only in secure mode

On Thu, Apr 09, 2015 at 03:06:39PM +0200, Paolo Bonzini wrote: > > > On 09/04/2015 14:47, Peter Maydell wrote: > > On 9 April 2015 at 13:20, Paolo Bonzini wrote: > >> This is an example of usage of attributes in a device model. It lets > >> you block flash writes unless the CPU is in secure mod

Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table

On 9 April 2015 at 14:51, Igor Mammedov wrote: > On Thu, 9 Apr 2015 14:27:58 +0100 > Peter Maydell wrote: > >> On 9 April 2015 at 14:17, Igor Mammedov wrote: >> > On Thu, 09 Apr 2015 13:50:52 +0100 >> > Alex Bennée wrote: >> > >> >> >> >> Shannon Zhao writes: >> >> > +for (i = 0; i < table

Re: [Qemu-devel] [PATCH] tcg/tcg-op.c: Fix ld/st of 64 bit values on 32-bit bigendian hosts

On 9 April 2015 at 02:20, Richard Henderson wrote: > On 04/08/2015 12:57 PM, Peter Maydell wrote: >> Switch the ifdef back to HOST_WORDS_BIGENDIAN. >> >> Signed-off-by: Peter Maydell > > Doh. > > Reviewed-by: Richard Henderson Applied to master, thanks. -- PMM

Re: [Qemu-devel] [PATCH 3/3] block: add 'node-name' field to BLOCK_IMAGE_CORRUPTED

On Wed, Apr 08, 2015 at 05:32:47PM -0600, Eric Blake wrote: > > +- "device":Device name (json-string) > > +- "node-name": Node name (json-string, optional) > > +- "msg": Informative message (e.g., reason for the corruption) > > + (json-string) > > +- "offset":If the cor

Re: [Qemu-devel] [PATCH] Fix crash with illegal "-net nic, model=xxx" option

On 04/09/2015 07:32 AM, Thomas Huth wrote: > Current QEMU crashes when specifying an illegal model with the > "-net nic,model=xxx" option, e.g.: > > $ qemu-system-x86_64 -net nic,model=n/a > qemu-system-x86_64: Unsupported NIC model: n/a > > The problem is that pci_nic_init_nofail() does not c

Re: [Qemu-devel] [PATCH] Fix crash with illegal "-net nic, model=xxx" option

On 9 April 2015 at 14:37, Michael S. Tsirkin wrote: > On Thu, Apr 09, 2015 at 03:32:45PM +0200, Thomas Huth wrote: >> Current QEMU crashes when specifying an illegal model with the >> "-net nic,model=xxx" option, e.g.: >> >> $ qemu-system-x86_64 -net nic,model=n/a >> qemu-system-x86_64: Unsuppor

[Qemu-devel] How address_space_rw works?

Hello, guys In my understanding, function exec.c:address_space_rw is used to handle read and write access requests to address space. In order to check my opinion, I write guest code and debug Qemu to see the path of code execution. If I read or write with address of MMIO like UART, it will h

Re: [Qemu-devel] [PATCH 13/14] target-arm: Use attribute info to handle user-only watchpoints

On Tue, Apr 07, 2015 at 09:09:59PM +0100, Peter Maydell wrote: > Now that we have memory access attribute information in the watchpoint > checking code, we can correctly implement handling of watchpoints > which should match only on userspace accesses, where LDRT/STRT/LDT/STT > from EL1 are treated

Re: [Qemu-devel] [PATCH 11/14] target-arm: Use correct memory attributes for page table walks

On Tue, Apr 07, 2015 at 09:09:57PM +0100, Peter Maydell wrote: > Factor out the page table walk memory accesses into their own function, > so that we can specify the correct S/NS memory attributes for them. > This will also provide a place to use the correct endianness and > handle the need for a s

Re: [Qemu-devel] [PATCH] misc: Fix new collection of typos

On 9 April 2015 at 19:32, Stefan Weil wrote: > All of them were reported by codespell. > Most typos are in comments, one is in an error message. > > Signed-off-by: Stefan Weil Reviewed-by: Peter Maydell thanks -- PMM

Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table

On 9 April 2015 at 14:17, Igor Mammedov wrote: > On Thu, 09 Apr 2015 13:50:52 +0100 > Alex Bennée wrote: > >> >> Shannon Zhao writes: >> > +for (i = 0; i < table_offsets->len; ++i) { >> > +/* rsdt->table_offset_entry to be filled by Guest linker */ >> > +bios_linker_loader_ad

Re: [Qemu-devel] [PATCH 02/14] memory: Add MemTxAttrs, MemTxResult to io_mem_read and io_mem_write

On Tue, Apr 07, 2015 at 09:09:48PM +0100, Peter Maydell wrote: > Add a MemTxAttrs argument to the io_mem_read() and io_mem_write() > functions, and make them return MemTxResult rather than bool, > thus pushing these new arguments out one level of the callstack > (all the callers callers currently p

Re: [Qemu-devel] [Qemu-block] [PATCH v2 2/4] block: Pause block jobs in bdrv_drain_all

On Wed, Apr 08, 2015 at 04:56:14PM +0200, Alberto Garcia wrote: > On Wed, Apr 08, 2015 at 11:37:52AM +0100, Stefan Hajnoczi wrote: > > > > +QTAILQ_FOREACH(bs, &bdrv_states, device_list) { > > > +AioContext *aio_context = bdrv_get_aio_context(bs); > > > + > > > +aio_context_acqu

Re: [Qemu-devel] [PATCH 07/14] exec.c: Add new address_space_ld*/st* functions

On Tue, Apr 07, 2015 at 09:09:53PM +0100, Peter Maydell wrote: > Add new address_space_ld*/st* functions which allow transaction > attributes and error reporting for basic load and stores. These > are named to be in line with the address_space_read/write/rw > buffer operations. > > The existing ld

Re: [Qemu-devel] [PATCH v6 0/8] QEMU memory hot unplug support

On Thu, 9 Apr 2015 09:16:21 +0800 Zhu Guihua wrote: > > On 04/08/2015 06:47 PM, Paulo Ricardo Paz Vital wrote: > > On Wed, 2015-04-08 at 11:52 +0200, Michael S. Tsirkin wrote: > >> On Wed, Apr 08, 2015 at 05:49:42PM +0800, Zhu Guihua wrote: > >>> Ping... > >> It's only been 4 days. We are final

[Qemu-devel] [PULL 3/4] aio: strengthen memory barriers for bottom half scheduling

From: Paolo Bonzini There are two problems with memory barriers in async.c. The fix is to use atomic_xchg in order to achieve sequential consistency between the scheduling of a bottom half and the corresponding execution. First, if bh->scheduled is already 1 in qemu_bh_schedule, QEMU does not e

Re: [Qemu-devel] [PATCH 10/14] target-arm: Honour NS bits in page tables

On Tue, Apr 07, 2015 at 09:09:56PM +0100, Peter Maydell wrote: > Honour the NS bit in ARM page tables: > * when adding entries to the TLB, include the Secure/NonSecure >transaction attribute > * set the NS bit in the PAR when doing ATS operations > > Note that we don't yet correctly use the

Re: [Qemu-devel] [PATCH] qemu-config: Accept empty option values

On 08/04/2015 20:16, Eduardo Habkost wrote: > Currently it is impossible to set an option in a config file to an empty > string, because the parser matches only lines containing non-empty > strings between double-quotes. > > As sscanf() "[" conversion specifier only matches non-empty strings, ad

Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table

On Thu, 9 Apr 2015 14:27:58 +0100 Peter Maydell wrote: > On 9 April 2015 at 14:17, Igor Mammedov wrote: > > On Thu, 09 Apr 2015 13:50:52 +0100 > > Alex Bennée wrote: > > > >> > >> Shannon Zhao writes: > >> > +for (i = 0; i < table_offsets->len; ++i) { > >> > +/* rsdt->table_offset_

[Qemu-devel] [PATCH for-2.3] configure: disable by default and warn about libxseg GPLv3 license

libxseg has changed license to GPLv3. QEMU includes GPL "v2 only" code which is not compatible with GPLv3. This means the resulting binaries may not be redistributable! Disable Archipelago (libxseg) by default to prevent accidental license violations. Also warn if linking against libxseg is ena

Re: [Qemu-devel] [PATCH 08/14] Switch non-CPU callers from ld/st*_phys to address_space_ld/st*

On Tue, Apr 07, 2015 at 09:09:54PM +0100, Peter Maydell wrote: > Switch all the uses of ld/st*_phys to address_space_ld/st*, > except for those cases where the address space is the CPU's > (ie cs->as). This was done with the following script which > generates a Coccinelle patch. > > A few over-80-

Re: [Qemu-devel] Last call for release-critical fixes for 2.3...

On Wed, Apr 08, 2015 at 01:48:25PM -0400, John Snow wrote: > > > On 04/08/2015 11:20 AM, Peter Maydell wrote: > >It looks like we have perhaps only a few more issues which need fixes > >to go into 2.3, so what I'd like to do is hold rc3 until we have them > >all fixed and then roll an rc3 which w

Re: [Qemu-devel] [PATCH] Fix crash with illegal "-net nic, model=xxx" option

On 09/04/2015 20:31, Eric Blake wrote: >> diff --git a/hw/pci/pci.c b/hw/pci/pci.c >> index 6941a82..b3d5100 100644 >> --- a/hw/pci/pci.c >> +++ b/hw/pci/pci.c >> @@ -1660,7 +1660,9 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus >> *rootbus, >> >> res = pci_nic_init(nd, rootbus, de

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