This fixes compile error when LIBISCSI_FEATURE_IOVECTOR is not defined:
block/iscsi.c|384 col 13| error: 'iscsi_allocationmap_is_allocated' defined but
not used [-Werror=unused-function]
Signed-off-by: Alexey Kardashevskiy
---
block/iscsi.c | 4 +---
1 file changed, 1 insertion(+), 3 delet
On 05/21/2014 01:49 PM, Alexey Kardashevskiy wrote:
> This fixes compile error when LIBISCSI_FEATURE_IOVECTOR is not defined:
>
> block/iscsi.c|384 col 13| error: 'iscsi_allocationmap_is_allocated' defined
> but not used [-Werror=unused-function]
Oops, never mind. Fix is already on its way.
Hi!
We recently discovered that not entire QEMU is GPL2-compatible, the fpu
emulation has a different license (copied below) which might create legal
problems because of that "INDEMNIFY" statement.
Does anyone else care (except IBM)?
What would the proper solution be? Ask the creator to relicens
Hi,
Nice job. We should avoid running migration_thread and bitmap_logging_thread
simultaneously.
Best regards:
ChenLiang
> Hi,
>
> This is the first part of my gsoc work.
>
> Following patches add the support of dirty bitmap logging and dumping
> to a specified file. These patches provide the
On Wed, May 21, 2014 at 09:36:08AM +0800, Fam Zheng wrote:
> On Tue, 05/20 07:43, Jeff Cody wrote:
> > On Tue, May 20, 2014 at 02:04:29PM +0800, Fam Zheng wrote:
> > > It makes no sense to check for "any" blocker on bs, we are here only
> > > because of the mechanical conversion from in_use to op_b
On Wed, May 21, 2014 at 9:43 AM, ChenLiang wrote:
> Hi,
> Nice job. We should avoid running migration_thread and bitmap_logging_thread
> simultaneously.
>
Any particular suggestion to avoid running simultaneous execution of
the threads?
--
Sanidhya
Fam Zheng writes:
> On Tue, 05/20 13:13, Eric Blake wrote:
>> On 05/20/2014 03:07 AM, Fam Zheng wrote:
>> > Please first take a look at patch 7 to see what is supported by this
>> > series.
>> >
>> > Patch 1 ~ 3 allows some useful basic types in schema.
>> >
>> > Patch 4 ~ 6 implements the new
On Wed, 05/21 00:34, Jeff Cody wrote:
> On Wed, May 21, 2014 at 09:36:08AM +0800, Fam Zheng wrote:
> > On Tue, 05/20 07:43, Jeff Cody wrote:
> > > On Tue, May 20, 2014 at 02:04:29PM +0800, Fam Zheng wrote:
> > > > It makes no sense to check for "any" blocker on bs, we are here only
> > > > because
This moves H_SET_MODE_RESOURCE_LE handler to a separate function
as there are other "resources" coming and this is going to becode ugly.
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr_hcall.c | 67 +++-
1 file changed, 35 insertions(+), 32 de
MMCR0 and MMCR1 have different numbers for 32 and 64 bit POWERPC.
We are going to support 64bit versions too so let's rename 32bit ones
to avoid confusion.
604 uses same SPR number for MMCR0 so it is included in this patch too.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h
This duplicates code of init_proc_POWER7() in init_proc_POWER8() as
there will be registers implemented in POWER7 and missing in POWER8
so we need separate init functions for POWER7 and POWER8.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 27 ---
This moves SPR initialization to helper functions.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 83 +
1 file changed, 62 insertions(+), 21 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
ind
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
This defines AIL flags for LPCR special register.
This changes @excp_prefix according to the mode, takes effect in TCG.
This turns support of a new capability PPC2_ISA207S flag for T
This adds helper which adds TAR/BESCRS/BESCRSU/BESCRR/BESCRRU/
EBBHR/EBBRR/BESCR/TFHAR/TFIAR/TEXASR/TEXASRU SPRs.
This adds MMCR2/FSCR/MMCRS SPRs.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h| 15 ++
target-ppc/translate_init.c | 123
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d23fcc6..82b502a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/trans
This adds migration support for registers saved before transaction started.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h | 19 +++
target-ppc/kvm.c | 38 ++
target-ppc/machine.c | 35 +++
3 fi
This adds TIR/SIAR/SDAR/MMCRA/MMCR0/MMCR1.
This redefines UMMCRA (was MCCRA) and defines hypv version of if.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h| 10 +-
target-ppc/translate_init.c | 41 +
2 files changed, 46 inser
Here is patchset to improve POWER8 support in QEMU.
Patches 1..5 are to enable little-endian guest to boot in TCG mode,
this basically defines a bunch of SPR which modern kernels try using.
Patch 6 enables migration for some SPRs.
Patch 7 enables migration while in transaction.
Patches 8, 9 imp
On 05/15/2014 07:59 PM, Alexey Kardashevskiy wrote:
> The existing interrupt allocation scheme in SPAPR assumes that
> interrupts are allocated at the start time, continously and the config
> will not change. However, there are cases when this is not going to work
> such as:
>
> 1. migration - we
On 2014/5/21 12:56, Sanidhya Kashyap wrote:
> On Wed, May 21, 2014 at 9:43 AM, ChenLiang wrote:
>> Hi,
>> Nice job. We should avoid running migration_thread and bitmap_logging_thread
>> simultaneously.
>>
> Any particular suggestion to avoid running simultaneous execution of
> the threads?
>
>
>
> We can do it like this:
> https://lists.gnu.org/archive/html/qemu-devel/2014-04/msg02185.html
>
Thanks.
If we are using only one of the threads, then I think we do not
require the splitting of the dirty bitmap (
https://lists.gnu.org/archive/html/qemu-devel/2014-05/msg04041.html ).
I can dire
On 05/17/2014 06:47 AM, Alexander Graf wrote:
>
> On 16.05.14 17:17, Alexey Kardashevskiy wrote:
>> On 05/17/2014 12:05 AM, Alexander Graf wrote:
>>> On 15.05.14 13:28, Alexey Kardashevskiy wrote:
This adds basic support for the "compat" CPU option. By specifying
the compat property, the
201 - 222 of 222 matches
Mail list logo
