On 17 March 2014 07:12, Peter Crosthwaite wrote:
> On Fri, Mar 7, 2014 at 5:33 AM, Peter Maydell
> wrote:
>> Support the Cortex-A57 in the virt machine model.
>>
>> Signed-off-by: Peter Maydell
>> ---
>> This should perhaps not be just stealing the a15mpcore_priv
>> on the basis that it's a GIC
On 04/10/2014 07:45 AM, Alexander Graf wrote:
Is this something that can be quickly fixed (perhaps by reverting the
PPC patch until a more complete solution is ready), and if so, is it
worth doing for 2.0 proper, rather than waiting for 2.0.1?
>>> Which way works better for you
On 04/11/2014 12:49 AM, Peter Maydell wrote:
> On 10 April 2014 15:35, Alexey Kardashevskiy wrote:
>> Then what is the purpose of many, many VMSTATE_.*_EQUAL?
>
> Often it's backwards compatibility with a previous vmstate
> or save/load function set which incorrectly sent data it didn't
> need to
On 04/04/2014 11:28 PM, Alexander Graf wrote:
> On 04/04/2014 07:17 AM, Alexey Kardashevskiy wrote:
>> On 03/24/2014 04:28 PM, Alexey Kardashevskiy wrote:
>>> Currently only migration fails if CPU version is different even a bit.
>>> For example, migration from POWER7 v2.0 to POWER7 v2.1 fails beca
On Thu, Apr 10, 2014 at 01:47:08PM +0200, Gerd Hoffmann wrote:
> On Do, 2014-04-10 at 13:55 +0300, Michael S. Tsirkin wrote:
> > On Thu, Apr 10, 2014 at 11:07:52AM +0200, Gerd Hoffmann wrote:
> > > This patch adds the virtio-input-hid base class and
> > > virtio-{keyboard,mouse,tablet} subclasses b
On Thu, Apr 10, 2014 at 01:57:03PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> > > +static void virtio_input_host_event(void *opaque)
> > > +{
> > > +VirtIOInputHost *vhost = opaque;
> >
> > I'd prefer a name that does not imply
> > vhost infrastructure
>
> ok.
>
> > > +rc = ioctl(vhost->fd
On 04/11/2014 12:52 AM, Andreas Färber wrote:
> Am 10.04.2014 16:40, schrieb Alexey Kardashevskiy:
>> On 04/10/2014 10:40 PM, Alexander Graf wrote:
>>>
>>> Juan, is a different command line device order supposed to work with
>>> migration?
>>
>>
>> We discussed this on IRC with Paolo and the conclu
On Thu, Apr 10, 2014 at 02:10:20PM +0200, Gerd Hoffmann wrote:
> On Do, 2014-04-10 at 14:05 +0300, Michael S. Tsirkin wrote:
> > On Thu, Apr 10, 2014 at 11:07:53AM +0200, Gerd Hoffmann wrote:
> > > Device for sending non-input control messages to the guest. For now
> > > this is only a single even
On Thu, Apr 10, 2014 at 01:24:51PM +0200, Alexander Graf wrote:
>
> On 10.04.14 13:17, Peter Maydell wrote:
> >So far I know of at least three fixes which should probably
> >go into 2.0:
> > * my fix for the configure stack-protector checks on MacOSX
> > * MST's pull request updating the ACPI te
On Thu, Apr 10, 2014 at 12:17:55PM +0100, Peter Maydell wrote:
> So far I know of at least three fixes which should probably
> go into 2.0:
> * my fix for the configure stack-protector checks on MacOSX
> * MST's pull request updating the ACPI test blobs
> * MST says we need to update the hex fil
On 10.04.14 17:02, Eric Blake wrote:
On 04/10/2014 07:45 AM, Alexander Graf wrote:
Is this something that can be quickly fixed (perhaps by reverting the
PPC patch until a more complete solution is ready), and if so, is it
worth doing for 2.0 proper, rather than waiting for 2.0.1?
Which way wo
On 08.04.2014 18:20, Eric Blake wrote:
On 04/08/2014 06:50 AM, Max Reitz wrote:
Allow QMP users to manipulate the granularity used in the block-commit
command.
Signed-off-by: Max Reitz
---
+++ b/include/block/block_int.h
@@ -426,6 +426,7 @@ void stream_start(BlockDriverState *bs, BlockDrive
Hi Gerd,
On 04/10/2014 05:07 AM, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> content.tex | 2 +
> virtio-input.tex | 135
> +++
> 2 files changed, 137 insertions(+)
> create mode 100644 virtio-input.tex
>
> diff --git
On 04/10/2014 09:27 AM, Alexander Graf wrote:
>
> Hrm, so what if we just ditch pre-2.0 support for PPC in libvirt? Then
> it'd become
>
> if (machine_type == pc || machine_type == pseries || machine_type ==
> ppce500)
> assume QEMU_CAPS_PCI_MULTIBUS
> else ...
>
> and everyone is happy, no? :
On Fri, 11 Apr 2014 01:11:10 +1000
Alexey Kardashevskiy wrote:
> On 04/04/2014 11:28 PM, Alexander Graf wrote:
> > On 04/04/2014 07:17 AM, Alexey Kardashevskiy wrote:
> >> On 03/24/2014 04:28 PM, Alexey Kardashevskiy wrote:
> >>> Currently only migration fails if CPU version is different even a b
On 10.04.14 17:38, Eric Blake wrote:
On 04/10/2014 09:27 AM, Alexander Graf wrote:
Hrm, so what if we just ditch pre-2.0 support for PPC in libvirt? Then
it'd become
if (machine_type == pc || machine_type == pseries || machine_type ==
ppce500)
assume QEMU_CAPS_PCI_MULTIBUS
else ...
and eve
On Thu, Apr 10, 2014 at 04:29:41PM +0300, Marcel Apfelbaum wrote:
> pair and
> pair
> are both optional.
> Do not reserve ranges if the above registers are not implemented.
>
> Signed-off-by: Marcel Apfelbaum
Reviewed-by: Michael S. Tsirkin
> ---
> src/fw/pciinit.c | 9 ++---
> src
On Thu, Apr 10, 2014 at 04:29:40PM +0300, Marcel Apfelbaum wrote:
> If a pci-2-pci bridge supports hot-plug functionality but there are no devices
> connected to it, reserve IO/mem in order to be able to attach devices
> later. Do not waste space, use minimum allowed.
>
> Signed-off-by: Marcel Apf
On 31.03.2014, at 12:40, Juan Quintela wrote:
>
> Hi
>
> Please, send any topic that you are interested in covering.
>
> Thanks, Juan.
>
> Call details:
>
> 10:00 AM to 11:00 AM EDT
> Every two weeks
>
> If you need phone number details, contact me privately.
>
For the next call, I woul
On Thu, Apr 10, 2014 at 04:29:39PM +0300, Marcel Apfelbaum wrote:
> v2 -> v3:
> - Addressed Michael S. Tsirkin's comments:
>- I/O and Prefetchable Memory are optional. Do not allocate ranges
> if they are not implemented (2/2).
> - Note that 2/2 patch can be seen as a separate fix. Howev
On 10 April 2014 16:49, Alexander Graf wrote:
> For the next call, I would propose to revive the "platform bus"
> (aka: how to create non-PCI devices with -device) discussions
> to make sure we're all on the same page.
I rather suspect we are not :-) Do you have a link to
the current proposals f
On 10.04.2014, at 17:52, Peter Maydell wrote:
> On 10 April 2014 16:49, Alexander Graf wrote:
>> For the next call, I would propose to revive the "platform bus"
>> (aka: how to create non-PCI devices with -device) discussions
>> to make sure we're all on the same page.
>
> I rather suspect we
On 04/08/2014 08:32 PM, Michael Mueller wrote:
> On Tue, 08 Apr 2014 20:04:42 +1000
> Alexey Kardashevskiy wrote:
>
>> On 04/08/2014 07:47 PM, Michael Mueller wrote:
>>> On Tue, 08 Apr 2014 11:23:14 +1000
>>> Alexey Kardashevskiy wrote:
>>>
On 04/08/2014 04:53 AM, Andreas Färber wrote:
commit f2ccc311df55ec026a8f8ea9df998f26314f22b2
dsdt: tweak ACPI ID for hotplug resource device
changes the DSDT, update test expected files to match
Signed-off-by: Michael S. Tsirkin
Reported-by: Igor Mammedov
---
tests/acpi-test-data/pc/DSDT | Bin 4485 -> 4480 bytes
tests/acpi-test-data
The following changes since commit efcc87d9aedb590b8506cd1a7c8abe557c760f9e:
Update version for v2.0.0-rc2 release (2014-04-08 18:52:06 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
for you to fetch changes up to 77547841
commit f2ccc311df55ec026a8f8ea9df998f26314f22b2
dsdt: tweak ACPI ID for hotplug resource device
changes the DSDT, update hex files to match
Otherwise the fix is only effective if QEMU is built
with iasl.
Signed-off-by: Michael S. Tsirkin
---
hw/i386/acpi-dsdt.hex.generated | 25
Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 18 ++
1 file changed, 18 inserti
Implement a subset of the Cortex-A57's implementation defined system
registers. We provide RAZ/WI or reads-as-constant/writes-ignored
implementations of the various control and syndrome reigsters.
We do not implement registers which provide direct access to and
manipulation of the L1 cache, since Q
The Cortex-A57, like most of the other ARM cores, has a CBAR
register which defines the base address of the per-CPU
peripherals. However it has a 64-bit view as well as a
32-bit view; expand the QOM reset-cbar property from UINT32
to UINT64 so this can be specified, and implement the
32-bit and 64-
Implement handling for the AArch64 SP_EL0 system register.
This holds the EL0 stack pointer, and is only accessible when
it's not being used as the stack pointer, ie when we're in EL1
and EL1 is using its own stack pointer. We also provide a
definition of the SP_EL1 register; this isn't guest visib
The current A32/T32 decoder bases its "is VFP/Neon enabled?" check
on the FPSCR.EN bit. This is correct if EL1 is AArch32, but for
an AArch64 EL1 the logic is different: it must act as if FPSCR.EN
is always set. Instead, trapping must happen according to CPACR
bits for cp10/cp11; these cover all of
From: Rob Herring
Implement exception handling for AArch64 EL1. Exceptions from AArch64 or
AArch32 EL0 are supported.
Signed-off-by: Rob Herring
[PMM: fixed minor style nits; updated to match changes in
previous patches; added some of the simpler cases of
illegal-exception-return support]
Sig
Implement the DC ZVA instruction, which clears a block of memory.
The fast path obtains a pointer to the underlying RAM via the TCG TLB
data structure so we can do a direct memset(), with fallback to a
simple byte-store loop in the slow path.
Signed-off-by: Peter Maydell
---
include/exec/softmmu
The ARM946 model currently uses the c5_data and c5_insn fields in the CPU
state struct to store the contents of its access permission registers.
This is confusing and a good source of bugs because for all the MMU-based
CPUs those fields are fault status and fault address registers, which
behave com
For system mode, we may have a 64 bit CPU which is currently executing
in AArch32 state; if we're dumping CPU state to the logs we should
therefore show the correct state for the current execution state,
rather than hardwiring it based on the type of the CPU. For consistency
with how we handle tran
Implement AArch64 view of the CONTEXTIDR register.
We tighten up the condition when we flush the TLB on a CONTEXTIDR
write to avoid needlessly flushing the TLB every time on a 64
bit system (and also on a 32 bit system using LPAE, as a bonus).
Signed-off-by: Peter Maydell
---
target-arm/cpu.h
Currently cpu.h defines a mixture of functions and types needed by
the rest of QEMU and those needed only by files within target-arm/.
Split the latter out into a new header so they aren't needlessly
exposed further than required.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
Move arm_log_exception() into internals.h so we can use it from
helper-a64.c for the AArch64 exception entry code.
Signed-off-by: Peter Maydell
---
target-arm/helper.c| 31 ---
target-arm/internals.h | 31 +++
2 files changed, 31 insert
Suppress the ID_AA64DFR0_EL1 PMUVer field, even if the CPU specific
value claims that it exists. QEMU doesn't currently implement it,
and not advertising it prevents the guest from trying to use it
and getting UNDEFs on unimplemented registers.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Cros
Add new helpers exception_with_syndrome (for generating an exception
with syndrome information) and exception_uncategorized (for generating
an exception with "Unknown or Uncategorized Reason", which have a syndrome
register value of zero), and use them to generate the correct syndrome
information f
Here's v5 of the AArch64 system emulation patchset.
Still missing/TODO:
* SMP support (needs PSCI emulation in QEMU; being prototyped)
* save/restore (I have a patch which adds this but I think it will
look better if we consolidate AArch32 cpsr and AArch64 pstate
handling)
but both of these
Add Cortex-A57 processor.
Signed-off-by: Peter Maydell
---
target-arm/cpu64.c | 43 +++
1 file changed, 43 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index d4fb1de..5be7d72 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@
From: Rob Herring
Set up the required syndrome information when we detect an MMU fault.
Signed-off-by: Rob Herring
[PMM: split out from exception handling patch, tweaked to bring
in line with how we create other kinds of syndrome information]
Signed-off-by: Peter Maydell
---
target-arm/helpe
Add the AArch64 ELR_EL1 register.
Note that this does not live in env->cp15: for KVM migration
compatibility we need to migrate it separately rather than
as part of the system registers, because the KVM-to-userspace
interface puts it in the struct kvm_regs rather than making
them visible via the O
Support the Cortex-A57 in the virt machine model.
Signed-off-by: Peter Maydell
---
This should perhaps not be just stealing the a15mpcore_priv
on the basis that it's a GICv2...
---
hw/arm/virt.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 2bbc9
In ARMv8 the 32 bit coprocessor ID register space is tidied up to
remove the wildcarded aliases of the MIDR and the RAZ behaviour
for the unassigned space where crm = 3..7. Make sure we don't
expose thes wildcards for v8 cores. This means we need to have
a specific implementation for REVIDR, an IMP
Implement the DAIF system register which is a view of the
DAIF bits in PSTATE. To avoid needing a readfn, we widen
the daif field in CPUARMState to uint64_t.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 20 +++
For AArch32 exceptions, the only information provided about
the cause of an exception is the individual exception type (data
abort, undef, etc), which we store in cs->exception_index. For
AArch64, the CPU provides much more detail about the cause of
the exception, which can be found in the syndrome
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, April 10, 2014 10:57 AM
> To: Peter Maydell
> Cc: Juan Quintela; KVM devel mailing list; qemu list; Yoder Stuart-
> B08248; Alistair Francis; Peter Crosthwaite; Christoffer Dall
> Subject: Re: [Qemu-devel
Implement the AArch64 SPSR_EL1. For compatibility with how KVM
handles SPSRs and with the architectural mapping between AArch32
and AArch64, we put this in the banked_spsr[] array in the slot
that is used for SVC in AArch32. This means we need to extend the
array from uint32_t to uint64_t, which re
For the A64 instruction set, the only FP/Neon disable trap
is the CPACR FPEN bits, which may indicate "enabled", "disabled"
or "disabled for EL0". Add a bit to the AArch64 tb flags indicating
whether FP/Neon access is currently enabled and make the decoder
emit code to raise exceptions on use of FP
From: Rob Herring
Implement AArch64 views of ESR_EL1 and FAR_EL1, and make the 32 bit
DFSR, DFAR, IFAR share state with them as architecturally specified.
The IFSR doesn't share state with any AArch64 register visible at EL1,
so just rename the state field without widening it to 64 bits.
Signed-
The Cortex-A15's CBAR register is actually read-only (unlike that
of the Cortex-A9). Correct our model to match the hardware.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/t
W dniu 2014-04-10 15:43, Marcel Apfelbaum pisze:
On Thu, 2014-04-10 at 14:55 +0200, Marcin Gibuła wrote:
Hi,
I've been playing with QEMU 2.0-rc2 and found a crash that isn't there
in 1.7.1.
Hi Marcin,
Thanks for reporting the bug!
Do you have a development environment?
If you do, and the repr
Implement the auxiliary fault status registers AFSR0_EL1 and
AFSR1_EL1. These are present on v7 and later, and have IMPDEF
behaviour; we choose to RAZ/WI for all cores.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target-arm/he
All the AArch32 ID registers are visible from AArch64
(in addition to the AArch64-specific ID_AA64* registers).
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 73 -
1 file changed, 44 insertions(+), 29 deletions(-)
diff --git a/target-
Implement the AArch64 address translation operations.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 3 +--
target-arm/helper.c | 53 -
2 files changed, 25 insertions(+), 31 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.
Implement the AArch64 view of the ACTLR (auxiliary control
register). Note that QEMU internally tends to call this
AUXCR for historical reasons.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target
Because unallocated encodings generate different exception syndrome
information from traps due to FP being disabled, we can't do a single
"is fp access disabled" check at a high level in the decode tree.
To help in catching bugs where the access check was forgotten in some
code path, we set this fl
On Thu, 2014-04-10 at 18:46 +0300, Michael S. Tsirkin wrote:
> On Thu, Apr 10, 2014 at 04:29:41PM +0300, Marcel Apfelbaum wrote:
> > pair and
> > pair
> > are both optional.
> > Do not reserve ranges if the above registers are not implemented.
> >
> > Signed-off-by: Marcel Apfelbaum
>
>
> Rev
09.04.2014 07:21, Serge Hallyn wrote:
> ENOENT (iiuc) means the kernel has an empty dirty bitmap for this
> slot. Don't abort in that case. This appears to solve the bug
> reported at
>
> https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/1303926
>
> which first showed up with commit b533f658a
On Wed, Apr 09, 2014 at 12:04:47PM +0100, Peter Maydell wrote:
> MacOSX clang silently swallows unrecognized -f options when doing a link
> with '-framework' also on the command line, so to detect support for
> the various -fstack-protector options we must do a plain .c to .o compile,
> not a compl
On 10 April 2014 17:31, Michael S. Tsirkin wrote:
> On Wed, Apr 09, 2014 at 12:04:47PM +0100, Peter Maydell wrote:
>> MacOSX clang silently swallows unrecognized -f options when doing a link
>> with '-framework' also on the command line, so to detect support for
>> the various -fstack-protector op
On Thu, 2014-04-10 at 18:24 +0200, Marcin Gibuła wrote:
> W dniu 2014-04-10 15:43, Marcel Apfelbaum pisze:
> > On Thu, 2014-04-10 at 14:55 +0200, Marcin Gibuła wrote:
> >> Hi,
> >>
> >> I've been playing with QEMU 2.0-rc2 and found a crash that isn't there
> >> in 1.7.1.
> > Hi Marcin,
> > Thanks f
On Thu, Apr 10, 2014 at 04:29:40PM +0300, Marcel Apfelbaum wrote:
[...]
> +for (i = 0, cap = pci_config_readb(pci->bdf, PCI_CAPABILITY_LIST);
> + (i <= 0xff) && cap;
> + i++, cap = pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_NEXT))
> +if (pci_config_readb(pci->bdf, cap
From: Rob Herring
Add support for v8 page table walks. This supports stage 1 translations
for 4KB, 16KB and 64KB page sizes starting with 0 or 1 level.
Signed-off-by: Rob Herring
[PMM: fix style nits, fold in 16/64K page support patch, use
arm_el_is_aa64() to decide whether to do 64 bit page t
On Thu, 2014-04-10 at 12:45 -0400, Kevin O'Connor wrote:
> On Thu, Apr 10, 2014 at 04:29:40PM +0300, Marcel Apfelbaum wrote:
> [...]
> > +for (i = 0, cap = pci_config_readb(pci->bdf, PCI_CAPABILITY_LIST);
> > + (i <= 0xff) && cap;
> > + i++, cap = pci_config_readb(pci->bdf, cap
The AArch64 implementation of the set_pc method needs to be updated to
handle the possibility that the CPU is in AArch32 mode; otherwise there
are weird crashes when doing interprocessing in system emulation mode
when an interrupt occurs and we fail to resynchronize the 32-bit PC
with the TB we nee
For ARMv8 there are two changes to the MVFR media feature registers:
* there is a new MVFR2 which is accessible from 32 bit code
* 64 bit code accesses these via the usual sysreg instructions
rather than with a floating-point specific instruction
Implement this.
Signed-off-by: Peter Maydell
The AArch64 usermode 'any' CPU type was accidentally specified
with the ARM_FEATURE_THUMB2EE bit set. This is incorrect since
ARMv8 removes Thumb2EE completely. Since we never implemented
Thumb2EE anyway having the feature bit set was fairly harmless
for user-mode, but the correct thing is to not s
For exceptions taken to AArch64, if a coprocessor/system register
access fails due to a trap or enable bit then the syndrome information
must include details of the failing instruction (crn/crm/opc1/opc2
fields, etc). Make the decoder construct the syndrome information
at translate time so it can b
On 04/10/2014 09:15 AM, Peter Maydell wrote:
> Implement the DC ZVA instruction, which clears a block of memory.
> The fast path obtains a pointer to the underlying RAM via the TCG TLB
> data structure so we can do a direct memset(), with fallback to a
> simple byte-store loop in the slow path.
>
Implement the AArch64 RVBAR register, which indicates the reset
address. Since the reset address is implementation defined and
usually configurable by setting config signals in hardware, we
also provide a QOM property so it can be set at board level if
necessary.
Signed-off-by: Peter Maydell
Revi
On 08.04.2014 22:53, Peter Lieven wrote:
Am 08.04.2014 um 15:15 schrieb Max Reitz :
On 07.03.2014 23:55, Max Reitz wrote:
Implement this function in the same way as raw_bsd does: Acknowledge
that this is a passthrough driver (always return BDRV_BLOCK_OFFSET_VALID
and BDRV_BLOCK_DATA and derive
As speed is an optional parameter for the QMP block-commit command, it
should be set to 0 if not given (as it is undefined if has_speed is
false), that is, the speed should not be limited.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
This patch was previously part of the "qemu-img: Imple
pair and
pair
are both optional.
Do not reserve ranges if the above registers are not implemented.
Signed-off-by: Marcel Apfelbaum
---
src/fw/pciinit.c | 9 ++---
src/hw/pci.c | 34 ++
src/hw/pci.h | 9 +
3 files changed, 45 insertions(+),
If a pci-2-pci bridge supports hot-plug functionality but there are no devices
connected to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Marcel Apfelbaum
---
src/fw/pciinit.c | 3 +++
src
v3 -> v4:
- Addressed Kevin O'Connor's comments:
- Refactored a for loop in patch 1/2.
- Addressed Michael S. Tsirkin's comments (patch 2/2):
- Removed not needed method
- Test only base registers (dropped limits tests)
- Renamed a helper method
- Used 0xFF to test if the memory is
On Thu, Apr 10, 2014 at 05:37:31PM +0100, Peter Maydell wrote:
> On 10 April 2014 17:31, Michael S. Tsirkin wrote:
> > On Wed, Apr 09, 2014 at 12:04:47PM +0100, Peter Maydell wrote:
> >> MacOSX clang silently swallows unrecognized -f options when doing a link
> >> with '-framework' also on the com
qemu-img should use QMP commands whenever possible in order to ensure
feature completeness of both online and offline image operations. For
the "commit" command, this is relatively easy, so implement it first
(in the hope that indeed others will follow).
As qemu-img does not have access to QMP (du
On Thu, Apr 10, 2014 at 08:48:10AM -0600, Eric Blake wrote:
> On 04/10/2014 08:43 AM, Eric Blake wrote:
> > On 04/10/2014 06:53 AM, Jeff Cody wrote:
> >
> +++ b/tests/qemu-iotests/common.rc
> @@ -178,10 +178,10 @@ _rm_test_img()
> local img=$1
> >>>
> >>> Since we are quoting $
On Thu, Apr 10, 2014 at 09:07:00PM +0300, Michael S. Tsirkin wrote:
> On Thu, Apr 10, 2014 at 08:44:18PM +0300, Marcel Apfelbaum wrote:
> > pair and
> > pair
> > are both optional.
> > Do not reserve ranges if the above registers are not implemented.
> >
> > Signed-off-by: Marcel Apfelbaum
> >
On 04/10/2014 12:39 PM, Marcel Apfelbaum wrote:
> On Thu, 2014-04-10 at 18:24 +0200, Marcin Gibuła wrote:
>> W dniu 2014-04-10 15:43, Marcel Apfelbaum pisze:
>>> On Thu, 2014-04-10 at 14:55 +0200, Marcin Gibuła wrote:
Hi,
I've been playing with QEMU 2.0-rc2 and found a crash that isn
Allow QMP users to manipulate the granularity used in the block-commit
command.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
---
block/commit.c| 16 +---
block/mirror.c| 4 ++--
blockdev.c| 22 --
include/block/block_i
Implement progress output for the commit command by querying the
progress of the block job.
Signed-off-by: Max Reitz
---
qemu-img-cmds.hx | 4 ++--
qemu-img.c | 44 ++--
qemu-img.texi| 2 +-
3 files changed, 45 insertions(+), 5 deletions(-)
di
qemu-img should use QMP commands whenever possible in order to ensure
feature completeness of both online and offline image operations. As
qemu-img itself has no access to QMP (since this would basically require
just everything being linked into qemu-img), imitate QMP's
implementation of block-comm
Introduce a new parameter for qemu-img commit which may be used to
explicitly specify the backing file into which an image should be
committed if the backing chain has more than a single layer.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
Reviewed-by: Fam Zheng
---
qemu-img-cmds.hx | 4 ++
v4 -> v5
- Addressed Michael S. Tsirkin's comments (patch 2/2):
- Open-coded pci_config_is_reserved() method.
v3 -> v4:
- Addressed Kevin O'Connor's comments:
- Refactored a for loop in patch 1/2.
- Addressed Michael S. Tsirkin's comments (patch 2/2):
- Removed not needed method
- T
If a pci-2-pci bridge supports hot-plug functionality but there are no devices
connected to it, reserve IO/mem in order to be able to attach devices
later. Do not waste space, use minimum allowed.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Marcel Apfelbaum
---
src/fw/pciinit.c | 3 +++
src
pair and
pair
are both optional.
Do not reserve ranges if the above registers are not implemented.
Signed-off-by: Marcel Apfelbaum
---
src/fw/pciinit.c | 9 ++---
src/hw/pci.c | 26 ++
src/hw/pci.h | 9 +
3 files changed, 37 insertions(+), 7 deleti
On Thu, Apr 10, 2014 at 08:44:18PM +0300, Marcel Apfelbaum wrote:
> pair and
> pair
> are both optional.
> Do not reserve ranges if the above registers are not implemented.
>
> Signed-off-by: Marcel Apfelbaum
> ---
> src/fw/pciinit.c | 9 ++---
> src/hw/pci.c | 34
Quoting Michael Tokarev (m...@tls.msk.ru):
> 09.04.2014 07:21, Serge Hallyn wrote:
> > ENOENT (iiuc) means the kernel has an empty dirty bitmap for this
> > slot. Don't abort in that case. This appears to solve the bug
> > reported at
> >
> > https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/1
On 04/10/2014 02:15 PM, Cole Robinson wrote:
> On 04/10/2014 12:39 PM, Marcel Apfelbaum wrote:
>> On Thu, 2014-04-10 at 18:24 +0200, Marcin Gibuła wrote:
>>> W dniu 2014-04-10 15:43, Marcel Apfelbaum pisze:
On Thu, 2014-04-10 at 14:55 +0200, Marcin Gibuła wrote:
> Hi,
>
> I've been
On 04/10/2014 02:15 PM, Cole Robinson wrote:
> On 04/10/2014 12:39 PM, Marcel Apfelbaum wrote:
>> On Thu, 2014-04-10 at 18:24 +0200, Marcin Gibuła wrote:
>>> W dniu 2014-04-10 15:43, Marcel Apfelbaum pisze:
On Thu, 2014-04-10 at 14:55 +0200, Marcin Gibuła wrote:
> Hi,
>
> I've been
Add passthrough functions for bdrv_aio_flush() and
bdrv_invalidate_cache().
Signed-off-by: Max Reitz
---
block/json.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/block/json.c b/block/json.c
index 591bc47..0e2d518 100644
--- a/block/json.c
+++ b/block/json.c
@@ -88,6 +88,
Add passthrough functions for bdrv_aio_ioctl(), bdrv_is_inserted(),
bdrv_media_changed(), bdrv_eject(), bdrv_lock_medium() and bdrv_ioctl().
Signed-off-by: Max Reitz
Reviewed-by: Benoit Canet
---
block/json.c | 40
1 file changed, 40 insertions(+)
diff
Add passthrough functions for bdrv_aio_discard(),
bdrv_co_write_zeroes(), bdrv_truncate() and bdrv_has_zero_init().
Signed-off-by: Max Reitz
Reviewed-by: Benoit Canet
---
block/json.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/block/json.c b/block/json.c
Implement this function by passing it through to bs->file.
Signed-off-by: Max Reitz
---
block/json.c | 8
1 file changed, 8 insertions(+)
diff --git a/block/json.c b/block/json.c
index cb83780..dfeec81 100644
--- a/block/json.c
+++ b/block/json.c
@@ -110,6 +110,13 @@ static coroutine_f
Add a passthrough function for bdrv_get_specific_info().
Signed-off-by: Max Reitz
Reviewed-by: Benoit Canet
---
block/json.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/block/json.c b/block/json.c
index 0c7d90d..d9348bc 100644
--- a/block/json.c
+++ b/block/json.c
@@ -181,6 +181,1
Commit 9561fda8d90e176bef598ba87c42a1bd6ad03ef7 changed the type of
'opaque' for link properties, but missed updating this call site.
Reproducer:
./x86_64-softmmu/qemu-system-x86_64 -qmp unix:./qmp.sock,server &
./scripts/qmp/qmp-shell ./qmp.sock
(QEMU) qom-list path=//machine/i440fx/pci.0/child[2
101 - 200 of 286 matches
Mail list logo
