On Wed, Feb 19, 2014 at 03:20:54PM -0500, Bandan Das wrote:
> The following patch depends on the value of rom_bar to
> determine rom blacklist behavior. Existing code shouldn't
> be affected by changing the default value of rom_bar since
> all relevant decisions only rely on whether rom_bar is zero
On Wed, Feb 19, 2014 at 01:36:45PM -0700, Alex Williamson wrote:
> On Wed, 2014-02-19 at 15:20 -0500, Bandan Das wrote:
> > The following patch depends on the value of rom_bar to
> > determine rom blacklist behavior. Existing code shouldn't
> > be affected by changing the default value of rom_bar s
On Thu, 02/20 00:08, Jeff Cody wrote:
> On Thu, Feb 20, 2014 at 01:01:38PM +0800, Fam Zheng wrote:
> > On Wed, 02/19 16:17, Jeff Cody wrote:
> > > On Wed, Feb 19, 2014 at 09:42:23PM +0800, Fam Zheng wrote:
> > > > This makes use of op_blocker and blocks all the operations except for
> > > > commit
On Thu, 02/20 00:57, Jeff Cody wrote:
> On Thu, Feb 20, 2014 at 12:37:17PM +0800, Fam Zheng wrote:
> > On Wed, 02/19 18:24, Jeff Cody wrote:
> > > On Wed, Feb 19, 2014 at 04:22:30PM -0500, Jeff Cody wrote:
> > > > On Wed, Feb 19, 2014 at 09:42:25PM +0800, Fam Zheng wrote:
> > > > > /*
> > > > > -
On 02/14/2014 07:26 PM, Alexey Kardashevskiy wrote:
> On 02/14/2014 06:29 PM, Paolo Bonzini wrote:
>> Il 14/02/2014 04:25, Alexey Kardashevskiy ha scritto:
>>> Nobody seems picking up the bits I am interested in from this :-/
>>> What can I possibly do to get this in upstream?... I feel I am doing
On 29/12/13 23:51, Olivier Danet wrote:
On SparcStations, the HostID field in the NVRAM is equal to the
last three bytes of the MAC address (which is also stored in the NVRAM).
This constant is used as an identification/serial number on Solaris.
signed-off-by : Olivier Danet
---
include/hw/nv
On 16/02/14 23:13, Olivier Danet wrote:
Two small fixes for the ESP (AM53C94) SCSI controller
* Signal the end of the DMA transfer after a SCSI command.
* The status register (RSTAT) is cleared after reading the interrupt
status register (RINTR), except for the TC bit (=Count To Zero) and the
Am 20.02.2014 um 08:18 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > If you specify the same option more than once (e.g. -o cluster_size=4k
> > -o lazy_refcounts=on), qemu-img silently ignores all but the last one. This
>
> Sounds like perfectly common behavior to me.
I guess it
On Wed, Feb 19, 2014 at 10:30:03AM -0800, Luigi Rizzo wrote:
> On Wed, Feb 19, 2014 at 7:30 AM, Stefan Hajnoczi wrote:
>
> > On Fri, Feb 14, 2014 at 05:40:24PM +0100, Vincenzo Maffione wrote:
> > > diff --git a/configure b/configure
> > > index 88133a1..61eb932 100755
> > > --- a/configure
> > >
Kevin Wolf writes:
> Am 20.02.2014 um 08:18 hat Markus Armbruster geschrieben:
>> Kevin Wolf writes:
>>
>> > If you specify the same option more than once (e.g. -o cluster_size=4k
>> > -o lazy_refcounts=on), qemu-img silently ignores all but the last one. This
>>
>> Sounds like perfectly commo
On Wed, Feb 19, 2014 at 04:57:28PM +0100, Vincenzo Maffione wrote:
> 2014-02-19 16:30 GMT+01:00 Stefan Hajnoczi :
>
> > On Fri, Feb 14, 2014 at 05:40:24PM +0100, Vincenzo Maffione wrote:
> > > @@ -56,31 +58,6 @@ typedef struct NetmapState {
> > > struct ioveciov[IOV_MAX];
> > > } Net
Hi,
This fix by Gal Hammer has been on list for quite a while, please pull.
The following changes since commit
46eef33b89e936ca793e13c4aeea1414e97e8dbb:
Fix QEMU build on OpenBSD on x86 archs (2014-02-17 11:44:00 +)
are available in the git repository at:
git://git.kernel.org/pub/scm/
On Sun, Feb 16, 2014 at 09:14:37PM -0500, Aryeh Friedman wrote:
> PetiteCloud is a layer 0 cloud platform (see site for details of what that
> means and how it fits into the virtualization/cloud computing land scape)
http://petitecloud.org/info.jsp doesn't do it for me. I see a lot of
buzzwords (
* Michael R. Hines (mrhi...@linux.vnet.ibm.com) wrote:
> On 02/19/2014 07:27 PM, Dr. David Alan Gilbert wrote:
> >
> >I was just wondering if a separate 'max buffer size' knob would allow
> >you to more reasonably bound memory without setting policy; I don't think
> >people like having potentially
On Wed, Feb 19, 2014 at 04:19:10PM +0100, Lluís Vilanova wrote:
> Stefan Hajnoczi writes:
>
> > On Mon, Feb 17, 2014 at 08:36:19PM +0100, Lluís Vilanova wrote:
> >> Minimizes the amount of backend code, making it simpler to add
> >> new/different
> >> backends.
> >>
> >> Also performs other clea
On Wed, Feb 19, 2014 at 07:23:24PM +0100, Andreas Färber wrote:
> Am 19.02.2014 15:50, schrieb Stefan Hajnoczi:
> > Reviewed by Paolo and Markus. Here is the pull request.
> >
> > v2:
> > * Don't call qtest_end() from SIGABRT handler to avoid reentrancy [Paolo]
> > * Use sigemptyset() to avoid
Tom,
I tested your patches [see below] and I found they work very well.
They solve all the immediate problems that libguestfs was hitting with
qemu not emulating certain POWER7 instructions.
I am now running a full libguestfs test which will take several hours,
but it looks as if -- even if this
On Wed, Feb 19, 2014 at 05:01:47PM +0100, Lluís Vilanova wrote:
> Stefan Hajnoczi writes:
>
> > Lluis: CCed you since Mohamad's LTTng 2.x patches conflict with your cleanup
> > series.
>
> Will rebase and adjust.
Sorry about that. I had most of these patches merged for a while and
forgot about
Looks good, ACK.
Christophe
On Wed, Feb 19, 2014 at 11:40:50AM +0100, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> hw/display/qxl.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/hw/display/qxl.c b/hw/display/qxl.c
> index 1471cc0..2a559eb 100644
Il 20/02/2014 09:37, Alexey Kardashevskiy ha scritto:
On 02/14/2014 07:26 PM, Alexey Kardashevskiy wrote:
> On 02/14/2014 06:29 PM, Paolo Bonzini wrote:
>> Il 14/02/2014 04:25, Alexey Kardashevskiy ha scritto:
>>> Nobody seems picking up the bits I am interested in from this :-/
>>> What can I
Il 20/02/2014 09:58, Mark Cave-Ayland ha scritto:
Hi Olivier,
I've applied the non-whitespace damaged patch (attached) but
unfortunately I still see the "!TC on DATA XFER" bug with my NetBSD 5
ISO under qemu-system-sparc :/ Note that the second part of the patch
showed some fuzz so I'm wonderi
There is no need to access backend->info->has_vnet_hdr() and friends
anymore. Use the qemu_has_vnet_hdr() API instead.
Signed-off-by: Stefan Hajnoczi
---
hw/net/vhost_net.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
index c9
This series is based on my net tree, which already has Vincenzo's "Add netmap
backend offloadings support" patch series merged.
After merging the series I realized we were bypassing the net.h API and
directly accessing nc->info->... in some cases. This series cleans that up, at
the cost of moving
The virtio_net offload APIs are used on the NIC's peer (i.e. the tap
device). The API was defined to implicitly use nc->peer, saving the
caller the trouble.
This wasn't ideal because:
1. There are callers who have the peer but not the NIC. Currently they
are forced to bypass the API and acces
qemu_get_queue() is a shorthand for qemu_get_subqueue(n->nic, 0). Use
the shorthand where possible.
Signed-off-by: Stefan Hajnoczi
---
hw/net/virtio-net.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 9218a09..3c0342e 100644
Dr. David Alan Gilbert wrote:
* Michael R. Hines (mrhi...@linux.vnet.ibm.com) wrote:
On 02/19/2014 07:27 PM, Dr. David Alan Gilbert wrote:
I was just wondering if a separate 'max buffer size' knob would allow
you to more reasonably bound memory without setting policy; I don't think
pe
Implement the remaining instructions in the SIMD 3-reg-same
and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,
FACGT, FMLA and FMLS.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper-a64.c| 60 ++
target-a
From: Janne Grunau
Signed-off-by: Janne Grunau
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
linux-user/main.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index cabc9e1..9192977 100644
--- a/linux-user/main.c
++
Implement the narrowing three-reg-diff operations: ADDHN,
RADDHN, SUBHN and RSUBHN.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 60 +-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/targe
Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_*
constant to include all the ones currently supported by the kernel
headers we are using.
Signed-off-by: Peter Maydell
---
target-arm/kvm-consts.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git
Implement the unprivileged load and store instructions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 69 +-
1 file changed, 37 insertions(+), 32 deletions(-)
diff --git a/target-arm/translate-a64.c b/ta
Several of the system registers handled via the ARMCPRegInfo
mechanism have access trap control bits controlling whether the
registers are accessible to lower privilege levels. Replace
the existing mechanism (allowing the read and write functions
to return EXCP_UDEF if access is denied) with a dedi
From: Alex Bennée
Add support for the floating-point pairwise operations
FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the
code which was previously handling only integer pairwise operations,
and push the integer-specific decode and handling of unallocated
cases up one level in the
Implement the wide three-reg-different operations:
SADDW, UADDW, SSUBW and USUBW.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/target-arm/t
14-02-17 11:44:00 +)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140220
for you to fetch changes up to 2ea5a2ca1f1dc302652d2ad5035e0b209ccaa177:
linux-user: AArch64: Fix exclusive store of the zero register (2014-02-2
Convert the remaining miscellaneous cases of reginfo read/write
functions returning EXCP_UDEF to use an accessfn instead:
TEEHBR, and the ATS address-translation operations.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 44 +++-
1 file changed, 19
The opcode switch in disas_simd_three_reg_diff() is missing the
customary comments indicating which cases correspond to which
instructions. Add them.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 22 +++---
1 file changed, 11 insert
Implement the 'long' operations in the vector x indexed
element category.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 144 +++--
1 file changed, 139 insertions(+), 5 deletions(-)
diff --git a/target-arm/tr
Add the remainder of the 64x64->128 operations in the three-reg-diff
category except for PMULL, PMULL2.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 109 -
1 file changed, 88 insertions(+), 21 deletions(
The read_raw_cp_reg and write_raw_cp_reg functions can now never
fail (in fact they should never have failed previously unless
there was a bug in a reginfo that meant no raw accessor was
provided for a might-trap register). This allows us to clean up
their prototypes so the write function returns v
System mode store-exclusive use a different code path to usermode ones;
implement this missing code, in a similar way to the 32 bit version.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 68 ++
1 file cha
Commit 40d225009ef accidentally changed the behaviour of
gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs,
so this meant we hit an assertion:
gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed.
Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore.
The ARMv8 instruction set includes a fused floating point
reciprocal square root step instruction which demands an
"(x * y + z) / 2" fused operation. Support this by adding
a flag to the softfloat muladd operations which requests
that the result is halved before rounding.
Signed-off-by: Peter Mayd
Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is
a hangover from the original separate system register implementation used
by the SuSE linux-user-mode-only AArch64 target.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h | 5 -
1 file
The write_raw_cp_reg's value argument should be a uint64_t, since
that's what all its callers hand it and what all the functions it
calls take. A (harmless) typo meant we were accidentally declaring
it as int64_t.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper
Implement the SIMD scalar indexed instructions. The encoding
here is nearly identical to the vector indexed grouping, so
we combine the two.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 115 -
1 file cha
Implement all the SIMD vector x indexed element instructions
in the subcategory which are not 'long' ops.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper-a64.c| 26 +
target-arm/helper-a64.h| 2 +
target-arm/translate-a64.c | 248
All cpreg read and write functions now return 0, so we can clean up
their prototypes:
* write functions return void
* read functions return the value rather than taking a pointer
to write the value to
This is a fairly mechanical change which makes only the bare
minimum set of changes to the c
The ARM946 has 8 PRBS (protection region base and size) registers.
Currently we implement these with a CP_ANY reginfo; however this
underdecodes (since there are 16 possible values of CRm but only
8 registers) and we catch the invalid values in the read and
write functions. However this causes issu
Convert the performance monitor reginfo definitions to use
an accessfn rather than returning EXCP_UDEF from read and
write functions. This also allows us to fix a couple of XXX
cases where we weren't imposing the access restrictions on
RAZ/WI or constant registers.
Signed-off-by: Peter Maydell
--
Log guest attempts to access unimplemented system registers via
the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
instruction sets). This is particularly useful for debugging
problems where the guest is trying to use a system register that
QEMU doesn't implement.
Signed-off-by: Pet
From: Alex Bennée
This adds all forms of the SIMD floating point and set instructions:
FCM(GT|GE|EQ|LE|LT)
Most of the heavy lifting is done by either the existing neon helpers or
some new helpers for the 64bit double cases. Most of the code paths are
common although the 2misc versions are a
Convert the reginfo structs for the generic timer registers
to use access functions rather than returning EXCP_UDEF from
their read handlers. In some cases this allows us to remove
a read handler completely.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c | 1
The SCTLR is full of bits for enabling or disabling various things, and so
there are many places in the code which check if certain bits are set.
Define some named constants for the SCTLR bits so these checks are easier
to read.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c| 2 +-
targe
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.
In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard
the use of them in check_ap() so that we don't get incorrect results
for ARMv8 CPUs.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/help
Implement the scalar three different instruction group:
it only has three instructions in it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 95 +-
1 file changed, 94 insertions(+), 1 deletion(-)
diff --g
Hello,
there's a bug in SP handling in disas_add_sub_ext_reg:
/* non-flag setting ops may use SP */
if (!setflags) {
tcg_rn = read_cpu_reg_sp(s, rn, sf);
tcg_rd = cpu_reg_sp(s, rd);
} else {
tcg_rn = read_cpu_reg(s, rn, sf);
tcg_rd = cpu_reg(s, rd);
Hello,
It looks ok to me.
Cheers
Vincenzo
2014-02-20 12:14 GMT+01:00 Stefan Hajnoczi :
> This series is based on my net tree, which already has Vincenzo's "Add
> netmap
> backend offloadings support" patch series merged.
>
> After merging the series I realized we were bypassing the net.h AP
On Thu, Feb 20, 2014 at 04:28:56PM +0800, Fam Zheng wrote:
> On Thu, 02/20 00:08, Jeff Cody wrote:
> > On Thu, Feb 20, 2014 at 01:01:38PM +0800, Fam Zheng wrote:
> > > On Wed, 02/19 16:17, Jeff Cody wrote:
> > > > On Wed, Feb 19, 2014 at 09:42:23PM +0800, Fam Zheng wrote:
> > > > > This makes use o
On 17 February 2014 17:35, Paolo Bonzini wrote:
> Anthony, Peter,
>
> The following changes since commit 89e4a51ca9546a7bbe1998c4e3d4a3ac3a0c19be:
>
> Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into
> staging (2014-01-31 11:13:08 +)
>
> are available in the git reposi
Am 11.12.2013 11:22, schrieb Alexey Kardashevskiy:
> QEMU supports firmware names for all devices in the QEMU tree but
> some architectures expect some parts of firmware path names in different
> format.
>
> This introduces a firmware-pathname-change interface definition.
> If some machines needs
Wenchao Xia writes:
> It is bad that same key was specified twice, especially when a union have
> two branches with same condition. This patch can prevent it.
>
> Signed-off-by: Wenchao Xia
> ---
> scripts/qapi.py |2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/sc
Wenchao Xia writes:
> Later other scripts will need to check the enum values.
>
> Signed-off-by: Wenchao Xia
> Reviewed-by: Eric Blake
> ---
> scripts/qapi.py| 18 ++
> tests/qapi-schema/comments.out |2 +-
> tests/qapi-schema/qapi-schema-t
Now that cpreg read and write functions can't fail and throw an
exception, we can remove the code from the translator that synchronises
the guest PC in case an exception is thrown.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 2 --
target-arm/translate.c | 4
2 files ch
Wenchao Xia writes:
> Before this patch, 'QAPISchemaError' scans whole input until 'pos'
> to get error line number. After this patch, the scan is avoided since
> line number is remembered in schema parsing. This patch also benefits
> other error report functions, which would be introduced later.
On Wed, Feb 19, 2014 at 09:39:09PM +, Mark Cave-Ayland wrote:
> On 19/02/14 13:35, Leandro Dorileo wrote:
>
> Hi Leandro,
>
> >>+static void cg3_realizefn(DeviceState *dev, Error **errp)
> >>+{
> >>+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> >>+CG3State *s = CG3(dev);
> >>+int ret
On 20 February 2014 11:51, Laurent Desnogues
wrote:
> Hello,
>
> there's a bug in SP handling in disas_add_sub_ext_reg:
>
> /* non-flag setting ops may use SP */
> if (!setflags) {
> tcg_rn = read_cpu_reg_sp(s, rn, sf);
> tcg_rd = cpu_reg_sp(s, rd);
> } else {
>
Anthony, Peter,
The following changes since commit 89e4a51ca9546a7bbe1998c4e3d4a3ac3a0c19be:
Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into
staging (2014-01-31 11:13:08 +)
are available in the git repository at:
git://github.com/bonzini/qemu.git configure
for y
From: Fam Zheng
Makefile.target includes rule.mak and unnested common-obj-y, then prefix
them with '../', this will ignore object specific QEMU_CFLAGS in subdir
Makefile.objs:
$(obj)/curl.o: QEMU_CFLAGS += $(CURL_CFLAGS)
Because $(obj) here is './block', instead of '../block'. This doesn't
From: Fam Zheng
With this change, main() calls qemu_init_exec_dir and uses argv[0] to
init exec_dir. The saved value can be retrieved with
qemu_get_exec_dir later. It will be reused by module loading.
Signed-off-by: Fam Zheng
Signed-off-by: Paolo Bonzini
---
include/qemu-common.h | 2 +-
inc
From: Fam Zheng
No longer adds flags and libs for them to global variables, instead
create config-host.mak variables like FOO_CFLAGS and FOO_LIBS, which is
used as per object cflags and libs.
This removes unwanted dependencies from libcacard.
Signed-off-by: Fam Zheng
[Split from Fam's patch to
While -mdynamic-no-pic can speed up the code somewhat, it is only used
on the legacy PowerPC Mac OS X, and I am not sure if anyone is still
testing that. Disabling PIC can cause problems when enabling modules,
so do not do that.
Signed-off-by: Paolo Bonzini
Signed-off-by: Fam Zheng
Signed-off-b
From: Fam Zheng
Install all the modules to ${MODDIR}.
Signed-off-by: Fam Zheng
Signed-off-by: Paolo Bonzini
---
Makefile | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Makefile b/Makefile
index 07d1ed7..57d83a3 100644
--- a/Makefile
+++ b/Makefile
@@ -368,6 +368,12 @@ install-datad
From: Fam Zheng
Add necessary rules and flags for shared object generation.
The new rules introduced here are:
1) %.o in $(common-obj-m) is compiled to %.o, then linked to %.so.
2) %.mo in $(common-obj-m) is the placeholder for %.so for pattern
matching in Makefile. It's linked to "-shared" wit
From: Fam Zheng
This patch adds loading, stamp checking and initialization of modules.
The init function of dynamic module is no longer directly called as
__attribute__((constructor)) in static linked version, it is called
only after passed the checking of presense of stamp symbol:
qemu_sta
From: Fam Zheng
The converted block drivers are:
curl
iscsi
rbd
ssh
glusterfs
Signed-off-by: Fam Zheng
Signed-off-by: Paolo Bonzini
---
configure | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/configure b/configure
index 136a8f0..66d7633 10
From: Don Slutz
Adjust TMPO and added TMPB, TMPL, and TMPA. libtool needs the names
to be fixed (TMPB).
Add new functions do_libtool and libtool_prog.
Add check for broken gcc and libtool.
Signed-off-by: Don Slutz
Signed-off-by: Paolo Bonzini
---
configure | 63
From: Fam Zheng
$(common-obj-m) will include $(block-obj-m), like $(common-obj-y) does
for $(block-obj-y).
Signed-off-by: Fam Zheng
Signed-off-by: Paolo Bonzini
---
Makefile| 4 +++-
Makefile.objs | 2 ++
Makefile.target | 6 +-
3 files changed, 10 insertions(+), 2 deletions(-)
On Thu, Feb 20, 2014 at 10:23:42AM +, Richard W.M. Jones wrote:
> I am now running a full libguestfs test which will take several hours,
> but it looks as if -- even if this test fails -- it won't be because
> of lack of emulation / missing instructions in qemu.
The tests ran. I hit two bugs,
On 20.02.2014, at 13:34, Richard W.M. Jones wrote:
> On Thu, Feb 20, 2014 at 10:23:42AM +, Richard W.M. Jones wrote:
>> I am now running a full libguestfs test which will take several hours,
>> but it looks as if -- even if this test fails -- it won't be because
>> of lack of emulation / mis
On Mon, Jan 20, 2014 at 06:22:28PM +0800, Fam Zheng wrote:
> On Fri, 01/10 09:45, Stefan Hajnoczi wrote:
> > QemuMutex does not guarantee fairness and cannot be acquired
> > recursively:
> >
> > Fairness means each locker gets a turn and the scheduler cannot cause
> > starvation.
> >
> > Recursiv
On Mon, Jan 20, 2014 at 06:29:50PM +0800, Fam Zheng wrote:
> On Fri, 01/10 09:45, Stefan Hajnoczi wrote:
> > +/* Take ownership of the AioContext. If the AioContext will be shared
> > between
> > + * threads, a thread must have ownership when calling aio_poll().
> > + *
> > + * Note that multiple
On Thu, Feb 20, 2014 at 01:36:57PM +0100, Alexander Graf wrote:
>
> On 20.02.2014, at 13:34, Richard W.M. Jones wrote:
>
> > On Thu, Feb 20, 2014 at 10:23:42AM +, Richard W.M. Jones wrote:
> >> I am now running a full libguestfs test which will take several hours,
> >> but it looks as if --
Am 19.02.2014 20:39, schrieb Eduardo Habkost:
> Some of my recent changes introduced variable declarations in the middle
> of code blocks.
>
> Fix the code so that it compiles without warnings when using
> -Wdeclaration-after-statement.
>
> Signed-off-by: Eduardo Habkost
> ---
> Changes v2:
> *
v2:
* Based off Igor's "-object/object-add support custom location and 2nd stage
initialization" series
* Dropped dedicated -iothread option in favor of -object
* Avoid re-acquiring rfifo in iothread_run() [mdroth]
v3:
* Fixed "Reliquinish" typo [fam]
* Rebased onto qemu.git/master which n
This is a stand-in for Michael Roth's QContext. I expect this to be
replaced once QContext is completed.
The IOThread object is an AioContext event loop thread. This patch adds
the concept of multiple event loop threads, allowing users to define
them.
When SMP guests run on SMP hosts it makes s
It can be useful to run an AioContext from a thread which normally does
not "own" the AioContext. For example, request draining can be
implemented by acquiring the AioContext and looping aio_poll() until all
requests have been completed.
The following pattern should work:
/* Event loop thread
get_pointer() assumes the string has unspecified lifetime (at least as
long as the object is alive). In some cases we can only produce a
temporary string that should be freed when get_pointer() is done.
Signed-off-by: Stefan Hajnoczi
---
hw/core/qdev-properties-system.c | 14 ++
1 f
Add a "iothread" qdev property type so devices can be hooked up to an
IOThread from the comand-line:
qemu -object iothread,id=iothread0 \
-device some-device,iothread=iothread0
Signed-off-by: Stefan Hajnoczi
---
hw/core/qdev-properties-system.c | 51
QemuMutex does not guarantee fairness and cannot be acquired
recursively:
Fairness means each locker gets a turn and the scheduler cannot cause
starvation.
Recursive locking is useful for composition, it allows a sequence of
locking operations to be invoked atomically by acquiring the lock around
Today virtio-blk dataplane uses a 1:1 device-per-thread model. Now that
IOThreads have been introduced we can generalize this to N:M devices per
threads.
This patch drops thread code from dataplane in favor of running inside
an IOThread AioContext.
As a bonus we solve the case where a guest keep
Il 20/02/2014 13:50, Stefan Hajnoczi ha scritto:
Today virtio-blk dataplane uses a 1:1 device-per-thread model. Now that
IOThreads have been introduced we can generalize this to N:M devices per
threads.
This patch drops thread code from dataplane in favor of running inside
an IOThread AioContex
Il 20/02/2014 13:50, Stefan Hajnoczi ha scritto:
Add a "iothread" qdev property type so devices can be hooked up to an
IOThread from the comand-line:
qemu -object iothread,id=iothread0 \
-device some-device,iothread=iothread0
Signed-off-by: Stefan Hajnoczi
---
hw/core/qdev-properties
The latest glibc provides a memrchr routine using an extended opcode
of the 'dcbt' instruction :
000a7cc0 :
a7cc0: 11 00 4c 3c addis r2,r12,17
a7cc4: b8 f8 42 38 addir2,r2,-1864
a7cc8: 14 2a e3 7c add r7,r3,r5
a7ccc: d0 00 07 7c
Thus this rule is useless.
Signed-off-by: Paolo Bonzini
---
Makefile.target | 2 --
1 file changed, 2 deletions(-)
diff --git a/Makefile.target b/Makefile.target
index 3945260..ba12340 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -130,8 +130,6 @@ else
obj-y += hw/$(TARGET_BASE_ARCH)/
On 02/20/2014 02:07 PM, Alexander Graf wrote:
>
> On 20.02.2014, at 14:01, Cédric Le Goater wrote:
>
>> The latest glibc provides a memrchr routine using an extended opcode
>> of the 'dcbt' instruction :
>>
>> 000a7cc0 :
>> a7cc0: 11 00 4c 3c addis r2,r12,17
>> a7cc4:
From: Fam Zheng
Adds extract-libs in LINK to expand any "per object libs", the syntax to define
such a libs options is like:
foo.o-libs := $(CURL_LIBS)
in block/Makefile.objs.
Similarly,
foo.o-cflags := $(FOO_CFLAGS)
is also supported.
"foo.o" must be listed in a nested var
On 20.02.2014, at 14:01, Cédric Le Goater wrote:
> The latest glibc provides a memrchr routine using an extended opcode
> of the 'dcbt' instruction :
>
> 000a7cc0 :
> a7cc0: 11 00 4c 3c addis r2,r12,17
> a7cc4: b8 f8 42 38 addir2,r2,-1864
> a7cc8:
On 17 February 2014 17:46, Luiz Capitulino wrote:
> On Sat, 15 Feb 2014 15:36:05 +
> Peter Maydell wrote:
>
>> On 13 February 2014 15:30, Luiz Capitulino wrote:
>> > The following changes since commit
>> > 9d74f6fef0801ca2ce5c9d38d59b85bf03c27669:
>> >
>> > Merge remote-tracking branch 'r
The latest glibc provides a memrchr routine using an extended opcode
of the 'dcbt' instruction :
000a7cc0 :
a7cc0: 11 00 4c 3c addis r2,r12,17
a7cc4: b8 f8 42 38 addir2,r2,-1864
a7cc8: 14 2a e3 7c add r7,r3,r5
a7ccc: d0 00 07 7c
1 - 100 of 280 matches
Mail list logo
