On 2012-10-08 23:11, Alex Williamson wrote:
> On Mon, 2012-10-08 at 23:40 +0200, Michael S. Tsirkin wrote:
>> On Mon, Oct 08, 2012 at 01:27:33PM -0600, Alex Williamson wrote:
>>> On Mon, 2012-10-08 at 22:15 +0200, Michael S. Tsirkin wrote:
On Mon, Oct 08, 2012 at 09:58:32AM -0600, Alex William
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron
>
> The current QEMUMachine definition has a 'use_scsi' field to indicate if a
> machine type should use scsi by default. However, Q35 wants to use ahci by
> default. Thus, introdue a new field in the QEMUMachine defintion, mach_if.
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron
>
> Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
> This allows q35 to specify its default disk type. It also allows q35 to
> differentiate between ahci and ide disks, such that -drive if=ide does not
>
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata
>
> pci capability must be in PCI space.
> It can't lay in PCIe extended config space.
>
> Signed-off-by: Isaku Yamahata
> Signed-off-by: Jason Baron
> ---
> hw/pci.c |5 ++---
> 1 files changed, 2 insertions(+), 3 deleti
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata
>
> Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
> standardized. PCI bridge swizzle is common logic, by introducing
> this function duplicated swizzle logic will be avoided later.
>
> [jba...@redhat.com:
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata
>
> Factor out pc nic initialization.
> This simplifies the pc initialization and will reduce the code
> duplication of q35 pc initialization.
>
> Signed-off-by: Isaku Yamahata
> Signed-off-by: Jason Baron
Reviewed-by: Paolo
Ping!
Any issues here? Should I [PULL] or can this go via arm-devs?
Regards,
Peter
On Thu, Oct 4, 2012 at 10:16 AM, Peter Crosthwaite
wrote:
> Patch 1 is dual core smp support.
> Patches 2-4 Implement the SLCR reset functionality.
>
> changed from v1:
> Addressed PMM review (P1)
> Patches 2-4 a
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron
>
> Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
> Rename ioapic_init -> ioapic_init_gsi.
>
> Signed-off-by: Jason Baron
Reviewed-by: Paolo Bonzini
> ---
> hw/pc.c | 24
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata
>
> Factor out smram/pam logic for later use.
> Which will be used by q35 too.
>
> [jba...@redhat.com: changes for updated memory API]
> Signed-off-by: Isaku Yamahata
> Signed-off-by: Jason Baron
Reviewed-by: Paolo Bonzini
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata
>
> Adds pci id constants which will be used by q35.
>
> [jba...@redhat.com: move #define PCI_CLASS_SERIAL_SMBUS to another patch]
> Signed-off-by: Isaku Yamahata
> Signed-off-by: Jason Baron
> ---
> hw/pci_ids.h |1 +
>
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka
>
> [jba...@redhat.com: add PCI_CLASS_SERIAL_SMBUS definition]
> Signed-off-by: Jan Kiszka
> Signed-off-by: Jason Baron
Reviewed-by: Paolo Bonzini
> ---
> hw/pci.c |1 +
> hw/pci_ids.h |1 +
> 2 files changed, 2 ins
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron
>
> This allows q35 to pass/set the size of the pcie window in its update routine.
>
> Signed-off-by: Jason Baron
> ---
> hw/pcie_host.c | 21 -
> hw/pcie_host.h |8 +---
> 2 files changed, 17 insert
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron
>
> Let's use PCIExpressHost with QOM.
>
> Acked-by: Andreas Färber
> Signed-off-by: Jason Baron
> ---
> hw/pcie_host.c | 14 ++
> hw/pcie_host.h |4
> 2 files changed, 18 insertions(+), 0 deletions(-)
>
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka
>
> Same as for i44fx: KVM does not support SMM yet. Signal it initialized
> to Seabios to avoid failures.
>
> Signed-off-by: Jan Kiszka
> Signed-off-by: Jason Baron
> ---
> hw/acpi_ich9.c |7 +++
> 1 files changed, 7 ins
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka
>
> Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
> an assertion.
>
> Signed-off-by: Jan Kiszka
> Signed-off-by: Jason Baron
> ---
> hw/q35.c |6 --
> 1 files changed, 4 insertions(+), 2 deletio
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka
>
> Both bits are added to the write-1-to-clear mask by default. As the
> smbus device does not allow writes at all, we have to remove it from
> that mask, also to avoid triggering a runtime assertion.
>
> Signed-off-by: Jan Kiszka
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata
>
> This was totally off: The CC registers are 16 bit (stored as little
> endian), their offsets run in reverse order, and D26IR as well as D25IR
> have 4 bytes offset to their successors.
>
> Reported-by: Jan Kiszka
> Signed-o
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron
>
> If -L is specified, and qemu does not find the bios file in , then
> the search fails. Add infrastructure such that the search will continue in
> the default paths, if not found in the -L path.
>
> Signed-off-by: Jason Baron
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron
>
> Automatically, locate the required q35 dsdt table on load. Otherwise we error
> out. This could be done in the bios, but its harder to produce a good error
> message.
Not just for q35, so the commit message is wrong, but the pa
On 9 October 2012 05:53, David Gibson wrote:
> The savevm code contains VMSTATE_ helpers for a number of commonly used
> types, but not for target_phys_addr_t. This patch fixes that deficiency
> implementing VMSTATE_TPA helpers in terms of VMSTATE_UINT32 or
> VMSTATE_UINT64 helpers as appropriate
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron
>
> Add piix style acpi hotplug to q35.
>
> Signed-off-by: Jason Baron
Not a thorough review, but it looks good.
Paolo
> ---
> hw/acpi_ich9.c | 172
> +++-
> hw/acpi_ich9.h
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka
>
> Signed-off-by: Jan Kiszka
> Signed-off-by: Jason Baron
> ---
> hw/pc_q35.c |3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> index b6a619a..48083bb 100644
> --- a/hw/p
Il 09/10/2012 10:02, Paolo Bonzini ha scritto:
> Il 09/10/2012 05:30, Jason Baron ha scritto:
>> From: Jason Baron
>>
>> Automatically, locate the required q35 dsdt table on load. Otherwise we error
>> out. This could be done in the bios, but its harder to produce a good error
>> message.
>
> Not
On Tue, Oct 09, 2012 at 10:27:26AM +0800, Dave Young wrote:
> On 10/05/2012 04:14 PM, Stefan Hajnoczi wrote:
>
> > On Sun, Sep 23, 2012 at 10:37:09AM +0800, Dave Young wrote:
> >> For the serial number decreasing issue, I think there's only these two
> >> ways to
> >> select, there's no ideal way
This is the current list of candidates for QEMU 1.2.1, which we're
planning to release on Thursday. Please review and respond with any additional
patches you think should be included. These patches are available at:
https://github.com/mdroth/qemu/commits/stable-1.2-staging
git://github.co
Hi,
On 10/09/2012 01:05 AM, Hans de Goede wrote:
Hi,
Some comments inline, I've a version with all the comments fixed here:
http://cgit.freedesktop.org/~jwrdegoede/qemu/commit/?h=qemu-kvm-1.2-usbredir&id=5e342d2d2186757cc41b2f834e3503cf10e98c2b
And I now also have redirecting super-speed mas
Hi,
> Not sure what will happen when we actually get UAS devices in this
> scenario though, will need to test, but UAS devices are very hard to
> find...
>
> Gerd, do you know where I can buy an UAS device (note a German
> source is fine) ?
No, I only have virtual ones ;)
/me got a usb3 stick
On Tue, Oct 09, 2012 at 03:33:13AM -0500, Michael Roth wrote:
Meant to cc stable and a couple other folks.
On 10/08/2012 07:21 PM, Andreas Färber wrote:
> Am 08.10.2012 18:46, schrieb Bharat Bhushan:
>> All devices are also placed under CCSR memory region.
>> The CCSR memory region is exported to pci device. The MSI interrupt
>> generation is the main reason to export the CCSR region to PCI device.
>> T
Oeh boy, do I like feeling like an idiot :) Thanks a lot for that easy
way to do it... the guides on forums and the spice-space.org page make
it look way more difficult than it needs to be. Big love to you man!
Regards, Tom
-Oorspronkelijk bericht-
Van: boun...@canonical.com [mailto:boun.
On Mon, Oct 08, 2012 at 03:00:04PM +0200, Paolo Bonzini wrote:
> Il 08/10/2012 13:39, Stefan Hajnoczi ha scritto:
> > 2. Thread pool for dispatching I/O requests outside the QEMU global mutex.
>
> I looked at this in the past and it feels like a dead end to me. I had
> a lot of special code in th
Hi,
> One possible alternative to re-combining would be to pass the
> short-not-ok flag along the chain all the way down into usbfs,
Yes, this is what I have in mind.
> but
> that won't work since the USBFS_URB_SHORT_NOT_OK flag does not
> work with XHCI controllers!
Oops.
> So lets try to s
On 10/09/2012 11:08 AM, Stefan Hajnoczi wrote:
> Here are the steps that have been mentioned:
>
> 1. aio fastpath - for raw-posix and other aio block drivers, can we reduce I/O
>request latency by skipping block layer coroutines?
Is coroutine overhead noticable?
> I'm also curious about vi
Hi
Please send in any agenda topics that you have.
Thanks, Juan.
Hi,
On 10/09/2012 10:38 AM, Hans de Goede wrote:
Hi,
On 10/09/2012 01:05 AM, Hans de Goede wrote:
Hi,
Some comments inline, I've a version with all the comments fixed here:
http://cgit.freedesktop.org/~jwrdegoede/qemu/commit/?h=qemu-kvm-1.2-usbredir&id=5e342d2d2186757cc41b2f834e3503cf10e98c2b
On 10/09/2012 05:16 AM, Rusty Russell wrote:
> Anthony Liguori writes:
>> We'll never remove legacy so we shouldn't plan on it. There are
>> literally hundreds of thousands of VMs out there with the current virtio
>> drivers installed in them. We'll be supporting them for a very, very
>> long ti
Il 09/10/2012 11:26, Avi Kivity ha scritto:
> On 10/09/2012 11:08 AM, Stefan Hajnoczi wrote:
>> Here are the steps that have been mentioned:
>>
>> 1. aio fastpath - for raw-posix and other aio block drivers, can we reduce
>> I/O
>>request latency by skipping block layer coroutines?
>
> Is c
Hi,
On 10/09/2012 11:21 AM, Gerd Hoffmann wrote:
So lets try to split this discussion into multiple questions:
1) Can we agree that re-combining input packets back into their original
transfers as done at the guest device driver level, is useful and given
the serial <-> usb converters case,
On 10/09/2012 12:36 PM, Paolo Bonzini wrote:
> Il 09/10/2012 11:26, Avi Kivity ha scritto:
>> On 10/09/2012 11:08 AM, Stefan Hajnoczi wrote:
>>> Here are the steps that have been mentioned:
>>>
>>> 1. aio fastpath - for raw-posix and other aio block drivers, can we reduce
>>> I/O
>>>request la
Il 09/10/2012 12:52, Avi Kivity ha scritto:
> On 10/09/2012 12:36 PM, Paolo Bonzini wrote:
>> Il 09/10/2012 11:26, Avi Kivity ha scritto:
>>> On 10/09/2012 11:08 AM, Stefan Hajnoczi wrote:
Here are the steps that have been mentioned:
1. aio fastpath - for raw-posix and other aio bloc
On 09.10.2012, at 06:17, David Gibson wrote:
> This patch adds some extra FPU state to CPUPPCState. Specifically,
> fpscr is extended to a target_ulong bits, since some recent (64 bit)
> CPUs now have more status bits than fit inside 32 bits. Also, we add
> the 32 VSR registers present on CPUs
On 09.10.2012, at 13:38, Alexander Graf wrote:
>
> On 09.10.2012, at 06:17, David Gibson wrote:
>
>> This patch adds some extra FPU state to CPUPPCState. Specifically,
>> fpscr is extended to a target_ulong bits, since some recent (64 bit)
>> CPUs now have more status bits than fit inside 32 b
On 4 October 2012 01:16, Peter Crosthwaite
wrote:
> @@ -400,6 +404,20 @@ static void zynq_slcr_write(void *opaque,
> target_phys_addr_t offset,
> goto bad_reg;
> }
> s->reset[(offset - 0x200) / 4] = val;
> +if (offset - 0x200 == A9_CPU * 4) {
On 09.10.2012, at 06:17, David Gibson wrote:
> Hi Alex,
>
> Here are some assorted pending pseries patches which should be ready
> to go. This clears the decks ready for a big series to add
> savevm/migration support for pseries.
>
Thanks, applied 1, 3 and 4. The FPU patch is still broken :)
On 4 October 2012 01:16, Peter Crosthwaite
wrote:
> From: Peter A. G. Crosthwaite
>
> The SLCR needs to be able to reset the CPUs, so link the CPUs to the slcr.
>
> Signed-off-by: Peter A. G. Crosthwaite
I think your patch 4/4 is the wrong approach to reset, so I'm not
going to review this one
On 4 October 2012 01:16, Peter Crosthwaite
wrote:
> From: Peter A. G. Crosthwaite
>
> Added linux smp support for the xilinx zynq platform (2x cpus are supported)
>
> Signed-off-by: Peter A. G. Crosthwaite
> ---
> Changed from v1:
> Addressed PMM review
> Shorted secondary bootloop using MVN ins
On 4 October 2012 01:16, Peter Crosthwaite
wrote:
> From: Peter A. G. Crosthwaite
>
> There is a gap in the reset region of the address space at offset 0x208. This
> throws out all these enum values by one when translating them to address
> offsets.
> Fixed by putting the corresponding gap in th
On 10/09/2012 01:08 PM, Paolo Bonzini wrote:
>>
>> That's not strictly a coroutine issue. Switching to ordinary threads
>> may make the problem worse, since there will clearly be contention.
>
> The point is you don't need either coroutines or userspace threads if
> you use native AIO. longjmp/
Il 09/10/2012 13:55, Avi Kivity ha scritto:
> Oh, agree 100% raw + native aio wants to bypass coroutines/threads
> completely.
Even posix-aio-compat can bypass coroutines.
> We could perhaps even avoid refcounting, by shutting down the device
> thread as part of hotunplug.
Yes, you "just" join t
On 2012-10-09 14:01, Paolo Bonzini wrote:
> Il 09/10/2012 13:55, Avi Kivity ha scritto:
>> Oh, agree 100% raw + native aio wants to bypass coroutines/threads
>> completely.
>
> Even posix-aio-compat can bypass coroutines.
>
>> We could perhaps even avoid refcounting, by shutting down the device
>
On 10/09/2012 02:01 PM, Paolo Bonzini wrote:
>
>> [could we also avoid refcounting by doing the equivalent of
>> stop_machine() during hotunplug?]
>
> That's quite an interesting alternative.
It's somewhat unattractive in that we know how much stop_machine is
hated in Linux. But maybe it makes
On 10/09/2012 02:18 PM, Jan Kiszka wrote:
> Not sure about the full context of this discussion, but I played with
> "stop-machine" (pause_all_vcpus) recently. The problem is, at least ATM,
> that it drops the BQL to wait for those threads, and that creates an
> unexpected rescheduling point over wh
Add declarations and templates of extended MMU helpers.
An extended helper takes an additional argument of the host address accessing
a guest memory which differs from the address of the call site to the helper
because helper call sites locate at the end of a generated code block.
Signed-off-by: Y
Hi, all.
Here is the 5th version of the series optimizing TCG qemu_ld/st code generation.
v5:
- Remove RFC tag
v4:
- Remove CONFIG_SOFTMMU pre-condition from configure
- Instead, add some CONFIG_SOFTMMU condition to TCG sources
- Remove some unnecessary comments
v3:
- Support CONFIG_T
Add optimized TCG qemu_ld/st generation which locates the code of TLB miss
cases at the end of a block after generating the other IRs.
Currently, this optimization supports only i386 and x86_64 hosts.
Signed-off-by: Yeongkyoon Lee
---
tcg/i386/tcg-target.c | 420
Am 04.10.2012 02:16, schrieb Peter Crosthwaite:
> From: Peter A. G. Crosthwaite
>
> Implement the CPU reset and halt functions of the A9_CPU_RST_CTRL register
> (offset 0x244).
>
> Signed-off-by: Peter A. G. Crosthwaite
> ---
>
> hw/zynq_slcr.c | 18 ++
> 1 files changed, 18
Enable CONFIG_QEMU_LDST_OPTIMIZATION for TCG qemu_ld/st optimization only when
a host is i386 or x86_64.
Signed-off-by: Yeongkyoon Lee
---
configure |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/configure b/configure
index e58846d..b02e079 100755
--- a/configure
+
On Tue, Oct 09, 2012 at 01:41:02PM +0200, Alexander Graf wrote:
> On 09.10.2012, at 13:38, Alexander Graf wrote:
> > On 09.10.2012, at 06:17, David Gibson wrote:
[snip]
> > This will still break TCG for qemu-system-ppc64, no?
>
> To be more precise:
>
> agraf@lychee:/home/agraf/release/qemu> grep
On Tue, Oct 09, 2012 at 09:03:21AM +0100, Peter Maydell wrote:
> On 9 October 2012 05:53, David Gibson wrote:
> > The savevm code contains VMSTATE_ helpers for a number of commonly used
> > types, but not for target_phys_addr_t. This patch fixes that deficiency
> > implementing VMSTATE_TPA helper
From: Hervé Poussineau
Add generic support for simple I/O port which, when written to, cause
QEMU to exit with the given written value.
There is no vmstate associated with the debugging port, simply because
the entire interface is a single, stateless, write-only port.
Changes from v1:
* Chang
Add a test device which supports the kvmctl ioports,
so one can run the KVM unittest suite.
Intended Usage:
qemu-system-x86_64 -device pc-testdev -serial stdio \
-device isa-debugexit,iobase=0xf4,access-size=4 \
-kernel /path/to/kvm/unittests/msr.flat
Where msr.flat is one of the KVM unittests,
These two patches introduce:
1) A ISA debugexit port device, that when written, causes qemu
to exit with the exit code passed as parameter.
2) A port of the existing testdev present on qemu-kvm to qemu
I think now I've got all comments made by Jan sorted out.
I did notice that with the new
Il 09/10/2012 14:22, Avi Kivity ha scritto:
> On 10/09/2012 02:01 PM, Paolo Bonzini wrote:
>>
>>> [could we also avoid refcounting by doing the equivalent of
>>> stop_machine() during hotunplug?]
>>
>> That's quite an interesting alternative.
>
> It's somewhat unattractive in that we know how much
All TCG hosts now support guest-base functionality, so we can
remove the setting of host_guest_base to 'yes' in every arm
of the case "$cpu" statement, and simply set guest_base to
default to 'yes'.
Signed-off-by: Peter Maydell
---
configure | 31 ++-
1 file changed
Yes it is independent.
Please queue to arm-devs,
Regards,
Peter
On Tue, Oct 9, 2012 at 9:53 PM, Peter Maydell wrote:
> On 4 October 2012 01:16, Peter Crosthwaite
> wrote:
>> From: Peter A. G. Crosthwaite
>>
>> There is a gap in the reset region of the address space at offset 0x208. This
>> th
On 10/09/2012 03:11 PM, Paolo Bonzini wrote:
>> But no, it's actually impossible. Hotplug may be triggered from a vcpu
>> thread, which clearly it can't be stopped.
>
> Hotplug should always be asynchronous (because that's how hardware
> works), so it should always be possible to delegate the act
On Mon, 8 Oct 2012 12:02:12 +0100
"Daniel P. Berrange" wrote:
> On Fri, Oct 05, 2012 at 05:52:35PM -0600, Eric Blake wrote:
> > Right now, 'query-block' has no way to filter to a single device, but
> > conversely, for each device, it shows only the first backing file,
> > rather than the entire b
Now that the sparc tcg backend has finally had guest-base support
added, we can declare that it is mandatory. This lets us (a)
drop the configure script support for a host CPU type not actually
supporting guest-base (b) remove the now unnecessary compile time
check for whether the TCG backend suppo
GUEST_BASE support is now supported by all TCG backends, and is
now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE
define (set by every backend) and the error if it is unset.
Signed-off-by: Peter Maydell
---
tcg/arm/tcg-target.h |2 --
tcg/hppa/tcg-target.h |2 --
tcg/i38
On 10/09/2012 06:16 AM, Peter Maydell wrote:
> That is, we could drop CONFIG_USER_GUEST_BASE. Does anybody have
> a practical use case for the --disable-guest-base configuration?
Nope, because the backends are good at eliminating the overhead
during tcg_target_qemu_prologue if guest_base turns out
On 10/09/2012 06:16 AM, Peter Maydell wrote:
> GUEST_BASE support is now supported by all TCG backends, and is
> now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE
> define (set by every backend) and the error if it is unset.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Richard Hen
Hi,
>>> 2a) The combining entity needs to know when the hcd is done with
>>> queuing up packets for an ep.
>>
>> Yes. We can add a USBDeviceClass method for that.
>
> Ok, this assumes that the combining / uncombining gets moved down
> into the usb-device level code. Which clearly has your pref
On 10/09/2012 06:16 AM, Peter Maydell wrote:
> All TCG hosts now support guest-base functionality, so we can
> remove the setting of host_guest_base to 'yes' in every arm
> of the case "$cpu" statement, and simply set guest_base to
> default to 'yes'.
>
> Signed-off-by: Peter Maydell
Reviewed-by
On Tue, Oct 9, 2012 at 9:41 PM, Peter Maydell wrote:
> On 4 October 2012 01:16, Peter Crosthwaite
> wrote:
>> @@ -400,6 +404,20 @@ static void zynq_slcr_write(void *opaque,
>> target_phys_addr_t offset,
>> goto bad_reg;
>> }
>> s->reset[(offset - 0x200)
Hi (Jeff?)
I was testing blockcommit operations qemu-git, as of Oct-6th (which
has your blockcommit code pulled in). And also w/ libvirt-git which
has Eric's libvirt blockcommit patches applied.
with the goal of :
actual state: [base] <-- [snap-1] <-- [snap-2] <-- [snap3] <-- [active-layer]
de
When we use SCSI generic device as disk image, function lseek
could not get the size of this kind of device.
So try to use SCSI command Read Capacity(10) when lseek failed to get
the size of SCSI generic device.
Signed-off-by: Chen Hanxiao
---
block/raw-posix.c | 46 +++
On Tue, Oct 9, 2012 at 9:52 PM, Peter Maydell wrote:
> On 4 October 2012 01:16, Peter Crosthwaite
> wrote:
>> From: Peter A. G. Crosthwaite
>>
>> Added linux smp support for the xilinx zynq platform (2x cpus are supported)
>>
>> Signed-off-by: Peter A. G. Crosthwaite
>> ---
>> Changed from v1:
Il 09/10/2012 15:21, Avi Kivity ha scritto:
> On 10/09/2012 03:11 PM, Paolo Bonzini wrote:
>>> But no, it's actually impossible. Hotplug may be triggered from a vcpu
>>> thread, which clearly it can't be stopped.
>>
>> Hotplug should always be asynchronous (because that's how hardware
>> works), s
Juan Quintela wrote:
> Hi
>
> Please send in any agenda topics that you have.
Hi
As there is no agenda, call gets cancelled.
Sorry for sending the request for agenda late.
Later, Juan.
On 9 October 2012 14:38, Peter Crosthwaite
wrote:
> On Tue, Oct 9, 2012 at 9:41 PM, Peter Maydell
> wrote:
>> We don't support per-CPU reset right now, and I don't think this is the
>> right approach. This external device shouldn't be reaching into the
>> implementation of the CPU object like th
Hi,
We are actually trying to use virtio devices with Virt-mmio bus.
The idea is to use theses patches I mentioned in a previous mail
(http://lists.gnu.org/archive/html/qemu-devel/2012-09/msg04913.html).
We are currently drawing the plan of how we can complete theses patches
to have it upstr
Rusty Russell writes:
> Anthony Liguori writes:
>> We'll never remove legacy so we shouldn't plan on it. There are
>> literally hundreds of thousands of VMs out there with the current virtio
>> drivers installed in them. We'll be supporting them for a very, very
>> long time :-)
>
> You will b
On 2012-10-09 15:03, Lucas Meneghel Rodrigues wrote:
> From: Hervé Poussineau
>
> Add generic support for simple I/O port which, when written to, cause
> QEMU to exit with the given written value.
>
> There is no vmstate associated with the debugging port, simply because
> the entire interface i
On 2012-10-09 15:03, Lucas Meneghel Rodrigues wrote:
> Add a test device which supports the kvmctl ioports,
> so one can run the KVM unittest suite.
>
> Intended Usage:
>
> qemu-system-x86_64 -device pc-testdev -serial stdio \
> -device isa-debugexit,iobase=0xf4,access-size=4 \
> -kernel /path/to
On Thu, 27 Sep 2012 09:59:33 +0930
Rusty Russell wrote:
> Hi all,
>
> I've had several requests for a more formal approach to the
> virtio draft spec, and (after some soul-searching) I'd like to try that.
>
> The proposal is to use OASIS as the standards body, as it's
> fairly light
This makes QEMU recognize the following CPU flag names:
Flags| Corresponding KVM kernel commit
-+
FSGSBASE | 176f61da82435eae09cc96f70b530d1ba0746b8b
AVX2, BMI1, BMI2 | fb215366b3c7320ac25dca766a0152df16534932
HLE, RT
Avi Kivity writes:
> On 10/09/2012 05:16 AM, Rusty Russell wrote:
>> Anthony Liguori writes:
>>> We'll never remove legacy so we shouldn't plan on it. There are
>>> literally hundreds of thousands of VMs out there with the current virtio
>>> drivers installed in them. We'll be supporting them
On Tue, Oct 9, 2012 at 2:01 PM, Paolo Bonzini wrote:
> Il 09/10/2012 13:55, Avi Kivity ha scritto:
>> Oh, agree 100% raw + native aio wants to bypass coroutines/threads
>> completely.
>
> Even posix-aio-compat can bypass coroutines.
Yes. I'll send benchmarks to show how much overhead there is fr
On Tue, Oct 09, 2012 at 02:16:48PM +0100, Peter Maydell wrote:
> Now that the sparc tcg backend has finally had guest-base support
> added, we can declare that it is mandatory. This lets us (a)
> drop the configure script support for a host CPU type not actually
> supporting guest-base (b) remove t
Hi,
On 10/09/2012 03:31 PM, Gerd Hoffmann wrote:
The core can and should do that for packets it owns (USBPacketState ==
USB_PACKET_QUEUED) because they are not (yet) passed to the USBDevice.
Packets owned by USBDevice (USBPacketState == USB_PACKET_ASYNC) must be
handled by the USBDevice itse
On 10/09/2012 03:50 PM, Paolo Bonzini wrote:
> Il 09/10/2012 15:21, Avi Kivity ha scritto:
>> On 10/09/2012 03:11 PM, Paolo Bonzini wrote:
But no, it's actually impossible. Hotplug may be triggered from a vcpu
thread, which clearly it can't be stopped.
>>>
>>> Hotplug should always be as
On Tue, Oct 09, 2012 at 09:37:29PM +0900, Yeongkyoon Lee wrote:
> Hi, all.
>
> Here is the 5th version of the series optimizing TCG qemu_ld/st code
> generation.
>
> v5:
> - Remove RFC tag
>
> v4:
> - Remove CONFIG_SOFTMMU pre-condition from configure
> - Instead, add some CONFIG_SOFTMMU
On Wed, 19 Sep 2012 18:38:38 +0200
Alexander Graf wrote:
>
> On 04.09.2012, at 17:13, Cornelia Huck wrote:
> > +static u32 virtio_ccw_get_features(struct virtio_device *vdev)
> > +{
> > + struct virtio_ccw_device *vcdev = to_vc_device(vdev);
> > + struct virtio_feature_desc features;
> > +
On Tue, Oct 9, 2012 at 11:52 PM, Peter Maydell wrote:
> On 9 October 2012 14:38, Peter Crosthwaite
> wrote:
>> On Tue, Oct 9, 2012 at 9:41 PM, Peter Maydell
>> wrote:
>>> We don't support per-CPU reset right now, and I don't think this is the
>>> right approach. This external device shouldn't b
Il 09/10/2012 16:24, Avi Kivity ha scritto:
> > But we are not Linux, and I think the tradeoffs are different for RCU in
> > Linux vs. QEMU.
> >
> > For CPUs in the kernel, running user code is just one way to get things
> > done; QEMU threads are much more event driven, and their whole purpose
>
On Thu, 20 Sep 2012 09:27:00 -0500
Anthony Liguori wrote:
> Cornelia Huck writes:
>
> > This patch enables using both virtio-xxx-s390 and virtio-xxx-ccw
> > by making the alias lookup code verify that a driver is actually
> > registered.
> >
> > (Only included in order to allow testing of virti
On 10/09/2012 04:35 PM, Paolo Bonzini wrote:
>> Of course we can violate that and it wouldn't know a thing, but I prefer
>> to stick to the established pattern.
>
> I wasn't suggesting that, just evaluating the different tradeoffs QEMU
> could make. Reference counting is complicated because it h
Ping for Peter,
This is a prerequisite for you ARM CPU reset as a GPIO idea. I'm on
board with it, if we can get this through which will make it
relatively painless to refactor my series.
Regards,
Peter
On Fri, Oct 5, 2012 at 5:15 AM, Eduardo Habkost wrote:
> From: Igor Mammedov
>
> [ehabkost:
On Wed, 3 Oct 2012 16:37:01 +0200
Paolo Bonzini wrote:
> Among others, before:
>
> $ qemu-system-x86_64 -chardev socket,port=12345,id=char
> inet_connect: host and/or port not specified
> chardev: opening backend "socket" failed
>
> After:
>
> $ x86_64-softmmu/qemu-system-x86_
On Tue, Oct 9, 2012 at 3:28 PM, Richard Henderson wrote:
> On 10/09/2012 06:16 AM, Peter Maydell wrote:
>> That is, we could drop CONFIG_USER_GUEST_BASE. Does anybody have
>> a practical use case for the --disable-guest-base configuration?
>
> Nope, because the backends are good at eliminating the
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