If -L is specified, and qemu does not find the bios file in , then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Signed-off-by: Jason Baron
---
vl.c | 28 +---
1 files changed, 21 insertions(+
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Signed-off-by: Jason Baron
---
hw/pc.c | 24
hw/pc.h |2 ++
hw/pc_piix.c | 25 +
3 files changed, 27 insertions(+), 24
From: Isaku Yamahata
Adds pci id constants which will be used by q35.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci_ids.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 301bf1c..6deeac0 100644
--- a/hw/pci_ids.
From: Isaku Yamahata
Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c | 1
From: Jan Kiszka
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pci.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 55e4ad3..3727afa 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1203,6 +1203,7 @@ static const pci_class_desc pci_clas
From: Jan Kiszka
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pc_q35.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 9d58519..b8c1196 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -69,6 +69,7 @@
#include "mc146818rtc.
From: Isaku Yamahata
This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.
Reported-by: Jan Kiszka
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/q3
From: Isaku Yamahata
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jba...@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |1 +
hw/pam.c | 121 +
From: Isaku Yamahata
Pass opaque argument to pci_map_irq_fn like pci_set_irq_fn.
ICH9 irq routing is not static, but configurable by chipset configuration
registers, so the corresponding irq mapping function of pci_map_irq_fn
needs to know the pointer to ich9.
[jba...@redhat.com: minor tweaks]
S
Add piix style acpi hotplug to q35.
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 173 +++-
hw/acpi_ich9.h | 10 +++
2 files changed, 182 insertions(+), 1 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 570ce0c..ba463a0 10
Rebase q35 to 1.2 - memory api updates, acpi updates, qom...
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 65
hw/acpi_ich9.h |9 +-
hw/pc.h|2 +
hw/pc_piix.c |4 +-
hw/pc_q35.c| 189 +++---
hw/q35.c | 477 +++
From: Isaku Yamahata
Introduce a helper function which initializes the ahci port with ide devices.
It will be used by q35 support.
Cc: Alexander Graf
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/ide.h |3 +++
hw/ide/ahci.c | 16
2 files changed,
On Thu, Sep 13, 2012 at 07:37:45PM +0200, Stefan Weil wrote:
> 32 bit x86 hosts don't need registers for helper function arguments
> because they use the default stack based calling convention.
>
> Removing the registers allows simpler code for function
> tcg_target_get_call_iarg_regs_count.
>
>
On Thu, Sep 13, 2012 at 07:37:46PM +0200, Stefan Weil wrote:
> The TCG targets no longer need individual implementations.
>
> Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,
> 'flags' is no longer used in tcg_target_get_call_iarg_regs_count.
>
> The remaining tcg_target_get_call_iarg_regs_
On Thu, Sep 13, 2012 at 07:37:44PM +0200, Stefan Weil wrote:
> While 64 bit hosts use the first three registers which are also used
> as function input parameters, 32 bit hosts use TCG_REG_EAX and
> TCG_REG_EDX which are not used in parameter passing.
>
> After defining new register macros for the
On Thu, Sep 13, 2012 at 07:37:43PM +0200, Stefan Weil wrote:
> TCG uses 6 registers for function arguments on 64 bit Linux hosts,
> but only 4 registers on W64 hosts.
>
> Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the number
> of arguments for some important helper functions from 4
On 09/13/2012 02:21 PM, Aurelien Jarno wrote:
>> > #if TCG_TARGET_REG_BITS == 32
>> > tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
>> > (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
>> > -tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[1], TCG_REG_ESP,
>
On 09/13/2012 04:29 PM, Paolo Bonzini wrote:
> Il 13/09/2012 21:44, Paolo Bonzini ha scritto:
>> Il 13/09/2012 21:04, Jeff Cody ha scritto:
> Perhaps we _should_ preserve that in bs->open_flags, while still using
> the initial value of BDRV_O_CACHE_WB to initialize bs->enable_write_cache.
>
On Thu, 2012-09-13 at 12:15 -0300, Erlon Cruz wrote:
> >> > lack of experience in the internals of the arch we would like you guys
> >> > to give us some design directions
> >> > and confirm if we going in the right direction. Our first idea is:
> >> >
> >> > 1 - to patch 'spapr.c' so it can
On Thu, Sep 13, 2012 at 02:30:36PM -0700, Richard Henderson wrote:
> On 09/13/2012 02:21 PM, Aurelien Jarno wrote:
> >> > #if TCG_TARGET_REG_BITS == 32
> >> > tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
> >> > (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
> >> >
Paolo,
Awesome!!! I just tried your patch, and it works beautifully.
I've been struggling with the lack of '--cache=writeback' for
months now with many work-arounds/kludges.
Thank you again for responding.
Qemu rocks!
Best regards,
Mark Trumpold
> -Original Message-
> From: Paolo Bon
On 13 September 2012 22:47, Aurelien Jarno wrote:
> On Thu, Sep 13, 2012 at 02:30:36PM -0700, Richard Henderson wrote:
>> On 09/13/2012 02:21 PM, Aurelien Jarno wrote:
>> >> > #if TCG_TARGET_REG_BITS == 32
>> >> > tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
>> >> > (A
On 09/13/2012 03:03 PM, Peter Maydell wrote:
> Hard to come up with a snappy name for "register which is the Nth
> input argument if input args are in registers, but an arbitrary
> temp reg otherwise, and which is in the forbidden list for the L
> constraint"...
I'm more than happy to let "registe
On Tue, 2012-09-11 at 18:07 +0300, Michael S. Tsirkin wrote:
> On Tue, Sep 11, 2012 at 08:46:34AM -0500, Anthony Liguori wrote:
> > On 09/10/2012 01:24 AM, Michael S. Tsirkin wrote:
> > >On Mon, Sep 10, 2012 at 08:16:54AM +0200, Paolo Bonzini wrote:
> > >>Il 09/09/2012 00:40, Michael S. Tsirkin ha
On 2012-09-13 21:56, Hervé Poussineau wrote:
> Jan Kiszka a écrit :
>> On 2012-09-13 07:55, Hervé Poussineau wrote:
>>> This option is described in RFC 1783. As this is only an optional field,
>>> we may ignore it in some situations and handle it in some others.
>>>
>>> However, MS Windows 2003 PXE
On 13.09.2012, at 22:12, Jason Baron wrote:
> Hi,
>
> Qemu bits for q35 support, I'm posting the seabios changes separately. The
> patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
> qemu command line. Hopefully, we can make it the default for x86 at some
> future
> point
On 11.09.2012, at 20:47, Aurelien Jarno wrote:
> From: Max Filippov
>
> Flags passed into float{32,64}_muladd are treated as bits; assign
> independent bits to float_muladd_negate_* to allow precise control over
> what gets negated in float{32,64}_muladd.
>
> Cc: Alexander Graf
> Cc: Peter Ma
Hi Richard,
On 14/09/12 03:34, Richard Henderson wrote:
On 09/12/2012 11:33 PM, g...@snapgear.com wrote:
+uint32_t HELPER(move_from_usp)(CPUM68KState * env)
+{
+return env->sp[M68K_USP];
+}
You don't need helpers for these.
DISAS_INSN(move_from_usp)
{
+TCGv reg;
if (IS_USE
From: Greg Ungerer
Fill out the code support for the move to/from usp instructions. They are
being decoded, but there is no code to support their actions. So add it.
Current versions of Linux running on the ColdFire 5208 use these instructions.
Signed-off-by: Greg Ungerer
---
target-m68k/tran
The Buildbot has detected a new failure on builder default_i386_rhel61 while
building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_i386_rhel61/builds/364
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_rhel61_32bit
On 13/09/12 20:29, Stefan Hajnoczi wrote:
On Thu, Sep 13, 2012 at 9:51 AM, Amos Kong wrote:
From: Jason Wang
Add a link status chang callback and change the link status bit in BMSR
& MSR accordingly. Tested in Linux/Windows guests.
The link status bit of MediaStatus is infered from BasicMode
Hi,
Any comments about that?
Regards,
Marcelo
On Tue, Sep 11, 2012 at 02:13:38PM -0400, Corey Bryant wrote:
> Are there any other requirements that need to be taken care of to
> enable execution of QEMU guests under separate unprivileged user IDs
> (ie. DAC isolation)?
>
> At this point, this p
** Attachment added: "Test case for bug..."
https://bugs.launchpad.net/bugs/1050694/+attachment/3313662/+files/harddisk.img
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You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1050694
Title:
Interrup
Public bug reported:
Hi,
I have been getting a GPF when I enable interrupts, working on
implementing processes and a scheduler. When I comment out the scheduler
code, I still get the GPF. I used the following QEMU command line to
capture a log:
qemu-system-i386 -smp 4 -monitor stdio -cpu core2du
Original conversation about this issue on osdev.org:
http://forum.osdev.org/viewtopic.php?f=1&t=25795
** Description changed:
Hi,
I have been getting a GPF when I enable interrupts, working on
implementing processes and a scheduler. When I comment out the scheduler
code, I still get th
Hi,
about the OOM issue, I plan to drop the OOM request for now in
implemention, and at next step use rpc to wrap these APIs, then
user can select to link directly against the library or the wrapped
API, what do you think about it?
> 于 2012-9-11 5:07, Eric Blake 写道:
>> On 09/10/2012 02:26 AM, Wen
From: Jason Wang
Add a link status chang callback and change the link status bit in BMSR
& MSR accordingly. Tested in Linux/Windows guests.
The LinkDown bit of MediaStatus is inverse with link status.
Signed-off-by: Jason Wang
Signed-off-by: Amos Kong
---
v2: don't add MediaState in RTL8139St
Thanks for the feedback. Nothing jumps out at me that I disagree with. I'll
get it updated and another patch out once I get the chance to incorporate
the info.
> +#include "hw/sysbus.h"
> +#include "dyngen-exec.h"
> +#include "cpu.h"
> +
> +struct altera_iic {
CamelCase
Yep. I missed that one
Thanks for the feedback. I'll see about getting things updated once I have
the chance. I wasn't too terribly concerned with performance as the target
processor being emulated is much slower than the host (about 100MHz). Even
the way things are now, Linux runs several times faster in emulation that
Am 14.09.2012 00:20, schrieb Richard Henderson:
On 09/13/2012 03:03 PM, Peter Maydell wrote:
Hard to come up with a snappy name for "register which is the Nth
input argument if input args are in registers, but an arbitrary
temp reg otherwise, and which is in the forbidden list for the L
constrai
On Fri, Sep 14, 2012 at 01:23:16AM +0200, Alexander Graf wrote:
>
> On 11.09.2012, at 20:47, Aurelien Jarno wrote:
>
> > From: Max Filippov
> >
> > Flags passed into float{32,64}_muladd are treated as bits; assign
> > independent bits to float_muladd_negate_* to allow precise control over
> > w
Il 14/09/2012 00:27, Nicholas A. Bellinger ha scritto:
> *) Keep vhost-scsi as a backend to virtio-scsi-pci
>
> - Reduces duplicated code amongst multiple virtio-scsi backends.
>
> - Follows the split for what existing vhost-net code already does.
>
> So that said, two quick questions for
Il 13/09/2012 23:45, Jeff Cody ha scritto:
> While there are more changes this way, I think it cleans up the code a
> bit. The advantage is that bs->open_flags actually reflects the open
> flags that are currently in use. One disadvantage I see is that it
> seems a bit odd to have BDRV_O_CACHE_WC
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