Changes from v9:
rename query-migrtion-supported-capabilities to
query-migrate-supported-capabilities
rename 'info migration_supported_capabilities' to 'info
migrate_supported_capabilities'
renamse migrate_set_cachesize to migrate_set_cache_size.
Add missing state to qmp_query_migrate_supported_c
On 08/04/2012 07:58 AM, Jamie Heilman wrote:
> Avi Kivity wrote:
>> On 07/25/2012 02:12 PM, Stefano Stabellini wrote:
>> > On Wed, 25 Jul 2012, Michael Tokarev wrote:
>> >> Stefano, Paul, can you take a look please?
>> >>
>> >> https://bugs.launchpad.net/bugs/1021649
>> >
>> > That is a very good
Changes from v9:
rename query-migrtion-supported-capabilities to
query-migrate-supported-capabilities
rename 'info migration_supported_capabilities' to 'info
migrate_supported_capabilities'
renamse migrate_set_cachesize to migrate_set_cache_size.
Add missing state to qmp_query_migrate_supported_c
Add migration capabilities that can be queried by the management using
query-migrate-supported-capabilities command.
The management can query the source QEMU and the destination QEMU in order to
verify both support some migration capability (currently only XBZRLE).
Signed-off-by: Orit Wasserman
S
The management can enable/disable a capability for the next migration by using
migrate-set-apabilities QMP command.
The management can query the current migration capabilities using
query-migrate-capabilities QMP command.
The user can use migrate_set_capability and 'info migrate_capabilities' HMP
c
In the outgoing migration check to see if the page is cached and
changed, then send compressed page by using save_xbrle_page function.
In the incoming migration check to see if RAM_SAVE_FLAG_XBZRLE is set
and decompress the page (by using load_xbrle function).
Signed-off-by: Benoit Hudzia
Signed-
Add MRU page cache mechanism.
The page are accessed by their address.
Signed-off-by: Benoit Hudzia
Signed-off-by: Petter Svard
Signed-off-by: Aidan Shribman
Signed-off-by: Orit Wasserman
---
Makefile.objs |1 +
cutils.c |9 ++
include/qemu/page_cache.h |
Change XBZRLE cache size in bytes (the size should be a power of 2, it will be
rounded down to the nearest power of 2).
If XBZRLE cache size is too small there will be many cache miss.
New query-migrate-cache-size QMP command and 'info migrate_cache_size' HMP
command to query cache value.
Signed-
Signed-off-by: Benoit Hudzia
Signed-off-by: Petter Svard
Signed-off-by: Aidan Shribman
Signed-off-by: Orit Wasserman
Signed-off-by: Juan Quintela
---
arch_init.c | 28
hmp.c| 13 +
migration.c | 17 +
migrati
Signed-off-by: Orit Wasserman
---
docs/xbzrle.txt | 136 +++
1 files changed, 136 insertions(+), 0 deletions(-)
create mode 100644 docs/xbzrle.txt
diff --git a/docs/xbzrle.txt b/docs/xbzrle.txt
new file mode 100644
index 000..ce577a9
---
From: Juan Quintela
Signed-off-by: Juan Quintela
---
arch_init.c | 24 +++-
1 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch_init.c b/arch_init.c
index 9833d54..21031d1 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -273,14 +273,16 @@ static void save_bl
Signed-off-by: Benoit Hudzia
Signed-off-by: Petter Svard
Signed-off-by: Aidan Shribman
Signed-off-by: Orit Wasserman
Signed-off-by: Juan Quintela
---
arch_init.c | 38 ++
hmp.c|6 ++
migration.c |6 ++
migration.h
For performance we are encoding long word at a time.
For nzrun we use long-word-at-a-time NULL-detection tricks from strcmp():
using ((lword - 0x0101010101010101) & (~lword) & 0x8080808080808080) test
to find out if any byte in the long word is zero.
Signed-off-by: Benoit Hudzia
Signed-off-by: Pe
Implement Unsigned Little Endian Base 128.
Signed-off-by: Orit Wasserman
---
cutils.c | 33 +
qemu-common.h |8
2 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/cutils.c b/cutils.c
index b0bdd4b..700f943 100644
--- a/cutils.c
+++
On 4 August 2012 20:27, Aakanksha Pudipeddi wrote:
> I came across this while working with qemu for a project. It looks like
> there is no support for mrrc/mcrr in qemu which results in the linux
> arch_timer code throwing a reserved instruction exception. Could you please
> let me know if anybody
On Fri, Aug 03, 2012 at 05:13:48PM +0200, Andreas Färber wrote:
> Am 03.08.2012 04:31, schrieb David Gibson:
> > On Thu, Aug 02, 2012 at 05:44:49PM +0200, Andreas Färber wrote:
> >> Am 02.08.2012 04:10, schrieb David Gibson:
[snip]
> >>> -static void spapr_cpu_reset(void *opaque)
> >>> -{
> >>> -
On Fri, Aug 3, 2012 at 4:26 PM, Stefan Hajnoczi wrote:
> On Fri, Aug 3, 2012 at 6:56 AM, Dong Xu Wang
> wrote:
>> On Thu, Aug 2, 2012 at 6:44 PM, Stefan Hajnoczi wrote:
>>> On Thu, Aug 2, 2012 at 8:09 AM, Dong Xu Wang
>>> wrote:
On Wed, Aug 1, 2012 at 9:55 PM, Stefan Hajnoczi wrote:
>>>
This series reworks the SSI bus framework for SPI and add some new SPI
controllers and devices:
Patches 1-5 reworks SSI to add chip-select support to SPI devices and allow for
multiple SPI devices attach
ed to the same bus.
Patches 6-7 fix the SPI setup in the stellaris machine model.
Patch 8
Removed assertion that only one device is attached to the SSI bus.
When multiple devices are attached, all slaves have their transfer function
called for transfers. Each device is responsible for knowing whether or not its
CS is active, and if not returning 0. The returned data is the logical or o
Device model for xilinx XPS SPI controller (v2.0)
Signed-off-by: Peter A. G. Crosthwaite
---
changed from v4 (Near total rewrite):
removed timer delay. This was innacturate anyways removed for simlicity.
updated for new SSI interface.
factored out txrx fifos using fifo.h
changed from v3:
typedef'
Added the two SPI controllers to the zynq machine model. Attached two SPI flash
devices to each controller.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/xilinx_zynq.c | 34 ++
1 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw
Signed-off-by: Dong Xu Wang
---
v1->v2: fix param leak.
qemu-img.c | 28 +---
1 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index 80cfb9b..36e1c77 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -1567,14 +1567,19 @@ static int img
Added device model for the Xilinx Zynq SPI controller (SPIPS).
Signed-off-by: Peter A. G. Crosthwaite
---
hw/arm/Makefile.objs |1 +
hw/xilinx_spips.c| 352 ++
2 files changed, 353 insertions(+), 0 deletions(-)
create mode 100644 hw/xilin
Added device model for m25p80 style SPI flash family.
Signed-off-by: Peter A. G. Crosthwaite
---
changed from v4:
Added write-1 flag (EEPROM mode).
n25q128 table entry indentation fix.
updated for new SSI interface.
various debug messages cleaned up and added.
changed from v3:
changed licence to
Added VMSD stub for SSI slaves. Fields may be added to this VMSD for generic
SSI slave state (e.g. the CS line state).
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ads7846.c |1 +
hw/max111x.c |1 +
hw/spitz.c |2 ++
hw/ssi.c | 10 ++
hw/ssi.h | 10 ++
Added default CS behaviour for SSI slaves. SSI devices can set a property
to enable CS behaviour which will create a GPIO on the device which is the
CS. Tristating of the bus on SSI transfers is implemented.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssd0323.c |6 ++
hw/ssi-sd.c |
stellaris_init() defines arrays of qemu_irq to decides what each of the GPIO
pins are connected to. This is ok for inputs (as an input can only have one
source) but is flawed for outputs as an output can connect to any number of
sinks. Removed the gpio_out array completely and just replaced its set
Added maintainership for SSI, M25P80 and the Xilinx SPI controllers.
Signed-off-by: Peter A. G. Crosthwaite
---
MAINTAINERS |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2d219d2..0f28f19 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
To be more consistent with the newer ways of error signalling. That and SIGABT
is easier to debug with than exit(1).
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssd0323.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index d8a0c14..0800
Allow multiple qdev_init_gpio_in() calls for the one device. The first call will
define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled
with different handlers. Needed when two levels of the QOM class heirachy both
define GPIO functionality, as a single GPIO handler with a
Added a FIFO API that can be used to create and operate byte FIFOs.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/Makefile.objs |1 +
hw/fifo.c| 79 ++
hw/fifo.h| 47
3 files changed, 127
Removed the explicit SSI mux and wired the CS line directly up to the SSI
devices.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssd0323.c |1 +
hw/ssi-sd.c|1 +
hw/stellaris.c | 98 ++--
3 files changed, 19 insertions(+), 81 de
Added SPI controller to the reference design, with two n25q128 spi-flashes
connected.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/petalogix_ml605_mmu.c | 28 +++-
1 files changed, 27 insertions(+), 1 deletions(-)
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_m
Slave creation function that can be used to create an SSI slave without
qdev_init() being called. This give machine models a change to set properties.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssi.c |9 +++--
hw/ssi.h |1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff -
are available in the git repository at:
git://developer.petalogix.com/public/qemu.git for-upstream/axi-stream.next
Anthony Liguori (1):
qom: Reimplement Interfaces
Peter A. G. Crosthwaite (1):
xilinx_axi*: Re-implemented interconnect
hw/Makefile.objs |1 +
hw/petalogi
From: Anthony Liguori
The current implementation of Interfaces is poorly designed. Each interface
that an object implements ends up being an object that's tracked by the
implementing object. There's all sorts of gymnastics to deal with casting
between these objects.
But an interface shouldn't
Re-implemented the interconnect between the Xilinx AXI ethernet and DMA
controllers. A QOM interface "stream" is created, for the two stream interfaces.
As per Edgars request, this is designed to be more generic than AXI-stream,
so in the future we may see more clients of this interface beyond AXI
[Original cover by Igor]
First patch introduces standard SD host controller model. This is accumulated
version of my previous patch I sent a while ago and a recent SDHCI patch by
Peter A. G. Crosthwaite. Second patch introduces Exynos4210-specific SDHCI
built on top of standard SDHCI model.
[Ne
From: Igor Mitsyanko
Custom Exynos4210 SD/MMC host controller, based on SD association standard host
controller ver. 2.00.
Signed-off-by: Igor Mitsyanko
---
changed from v5 (Igor):
Updated for new IRQ system
changed from v4 (Igor):
set irq on SLOTINT status instead of interrupt registers status
The Xilinx Zynq device has two SDHCI controllers. Added to the machine model.
Signed-off-by: Peter A. G. Crosthwaite
Reviewed-by: Peter Maydell
---
changed from v4:
removed redundant braces
changed from v3:
fixed indentation
tweaked commit msg
hw/xilinx_zynq.c | 10 ++
1 files changed
Allows for repeating of -sd arguments in the same way as -pflash and -mtdblock.
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Igor Mitsyanko
Reviewed-by: Peter Maydell
---
changed from v4:
fixed (another) commit msg typo
changed from v3:
fixed commit msg typo
vl.c |2 +-
1 files changed
- Original Message -
> On Thu, 02 Aug 2012 10:31:28 +0800
> Amos Kong wrote:
>
> > On 01/08/12 21:29, Luiz Capitulino wrote:
> > > On Wed, 01 Aug 2012 19:33:27 +0800
> > > Amos Kong wrote:
> > >
> > >> On 31/07/12 22:44, Luiz Capitulino wrote:
> > >>> On Fri, 27 Jul 2012 18:31:41 -0300
>
- Original Message -
> [cc: Juan & Amos]
>
> Luiz Capitulino writes:
>
> > On Wed, 1 Aug 2012 22:02:35 -0300
> > Luiz Capitulino wrote:
> >
> >> Next commit wants to use this.
> >>
> >> Signed-off-by: Luiz Capitulino
> >> ---
> >>
> >> This patch is an interesting case, because on
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