On Tue, May 17, 2011 at 17:46, Alexander Graf wrote:
>
> On 15.05.2011, at 18:41, Alexey Zaytsev wrote:
>
>> Hi again.
>>
>> After reverting 667bb59, ahci works fine in Linux, if I boot it with
>> -kernel, but grub seems to have some problems.
>> Grub2 gets to the rescue prompt. The disk and its p
On 05/17/2011 01:00 PM, Paolo Bonzini wrote:
This series includes the following improvements to the SCSI subsystem:
1) introduction of SCSIBusOps that generalize the existing
command_complete callback;
2) widespread use of the SCSIRequest abstraction, with simpler memory
management (refcounting
On 05/19/2011 09:12 AM, Avi Kivity wrote:
The memory API separates the attributes of a memory region (its size, how
reads or writes are handled, dirty logging, and coalescing) from where it
is mapped and whether it is enabled. This allows a device to configure
a memory region once, then hand it
On 05/17/2011 03:32 PM, Max Filippov wrote:
> +enum {
> +THREADPTR = 231,
> +FCR = 232,
> +FSR = 233,
> +};
> +
> typedef struct XtensaConfig {
> const char *name;
> uint64_t options;
> @@ -109,6 +115,7 @@ typedef struct CPUXtensaState {
> uint32_t regs[16];
> uint3
Am 19.05.2011 16:12, schrieb Avi Kivity:
The memory API separates the attributes of a memory region (its size, how
reads or writes are handled, dirty logging, and coalescing) from where it
is mapped and whether it is enabled. This allows a device to configure
a memory region once, then hand it of
On Thu, May 19, 2011 at 3:12 PM, Avi Kivity wrote:
> +struct MemoryRegion {
> + /* All fields are private - violators will be prosecuted */
> + const MemoryRegionOps *ops;
> + MemoryRegion *parent;
In the case where a region is aliased (mapped twice into the address
space at different ad
On 05/17/2011 03:32 PM, Max Filippov wrote:
> +uint32_t HELPER(nsa)(uint32_t v)
> +{
> +if (v & 0x8000) {
> +v = ~v;
> +}
> +return v ? 31 : clz32(v) - 1;
Condition is reversed here.
r~
On 05/17/2011 03:32 PM, Max Filippov wrote:
> +if (env->sregs[LEND] != v) {
> +tb_invalidate_phys_page_range(
> +env->sregs[LEND] - 1, env->sregs[LEND], 0);
> +env->sregs[LEND] = v;
> +tb_invalidate_phys_page_range(
> +env->sregs[LEND] - 1
On 05/17/2011 03:32 PM, Max Filippov wrote:
> +static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
> +{
> +tcg_gen_mov_i32(cpu_SR[sr], s);
> +/* This can change tb->flags, so exit tb */
> +gen_jumpi_check_loop_end(dc, -1);
> +}
Surely you have to flush all TB's when
On 05/17/2011 03:32 PM, Max Filippov wrote:
> See ISA, 4.4.4 for details.
>
> Correct (aligned as per ISA) address for unaligned access is generated
> in case this option is not enabled.
>
> Signed-off-by: Max Filippov
> ---
> target-xtensa/translate.c | 33 +++--
>
On 05/17/2011 03:32 PM, Max Filippov wrote:
> +DEF_HELPER_0(simcall, void)
> DEF_HELPER_0(dump_state, void)
>
> #include "def-helper.h"
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 3a0fa01..b170dbe 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op
OK, here's a patch that implements the virtio spec update that I
sent earlier. It supercedes the PUBLISH_USED_IDX patches
I sent out earlier.
Support is added in both userspace and vhost-net.
If you see issues or are just curious, you can
turn the new feature off. For example:
-global virtio-net
Add support for extended feature bits: up to 64 bit.
Only virtio-pci is actually implemented,
s390 and syborg are stubbed out (and untested).
Signed-off-by: Michael S. Tsirkin
---
hw/qdev-properties.c | 39
hw/qdev.h | 10 +
hw/s390-virtio-bus.c |
Add support for used_event feature, and utilize it to
reduce the number of interrupts and exits for the guest.
Signed-off-by: Michael S. Tsirkin
---
hw/vhost_net.c |6
hw/virtio.c| 92 ++-
hw/virtio.h|9 +-
3 files ch
Hello qemu-devel
Would you like to earn an extra $200 everyday?, for just 45 minutes work? You
could quit your job and make double the money at home working for yourself.
visit->http:tinyurl.com/42e38u9
Regards,
Carmille Burns
Survey Human Resources Dept.
Early ppc64 CPUs include a hack to partially simulate the ppc32 segment
registers, by translating writes to them into writes to the SLB. This is
not used by any current Linux kernel, but it is used by the openbios used
in the qemu mac99 model.
Commit 81762d6dd0d430d87024f2c83e9c4dcc4329fb7d, clea
On Thu, May 19, 2011 at 10:25:04AM +0200, Andreas Färber wrote:
> QEMU HEAD still uses a 32-bit binary for both 32-bit and
> 64-bit. That one uses mtsrin so will need the compatibility, it
> seemed affected, too.
>
> OpenBIOS SVN HEAD (blob) uses slb* as linked to. We're in the
> preparation of 1.
Early ppc64 CPUs include a hack to partially simulate the ppc32 segment
registers, by translating writes to them into writes to the SLB. This is
not used by any current Linux kernel, but it is used by the openbios used
in the qemu mac99 model.
Commit 81762d6dd0d430d87024f2c83e9c4dcc4329fb7d, clea
Hello qemu-devel
Would you like to earn an extra $200 everyday?, for just 45 minutes work? You
could quit your job and make double the money at home working for yourself.
visit->http:tinyurl.com/42e38u9
Regards,
Carmille Burns
Survey Human Resources Dept.
On 05/17/2011 09:11 PM, Christoph Hellwig wrote:
On Mon, May 16, 2011 at 04:10:21PM -0500, Anthony Liguori wrote:
To further clarify:
Today cache=none|writethrough|writeback does two things. It:
1) Changes the WCE flag that's visible to the guest
2) Determines whether the host page cache is
Hello qemu-devel
Would you like to earn an extra $200 everyday?, for just 45 minutes work? You
could quit your job and make double the money at home working for yourself.
visit->http:tinyurl.com/42e38u9
Regards,
Carmille Burns
Survey Human Resources Dept.
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