[Qemu-devel] qemu/hw m48t59.c

CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 09:03:44 Modified files: hw : m48t59.c Log message: Make debug printing consistent (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/m48t59.c?cvsroot=qemu&r

[Qemu-devel] qemu/hw m48t59.c sun4m.c

CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 09:05:30 Modified files: hw : m48t59.c sun4m.c Log message: M48T02 support (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/m48t59.c?cvsroot=qemu&r1=1.18&r

[Qemu-devel] qemu/hw sun4m.c

CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 09:07:00 Modified files: hw : sun4m.c Log message: Set SS-5 IOMMU version to Turbosparc to match default CPU (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/

Re: [Qemu-devel] MIPS COP1X (and related) instructions

Thiemo Seufer <[EMAIL PROTECTED]> writes: > Richard Sandiford wrote: >> All MIPS COP1X instructions currently require the FPU to be in 64-bit >> mode. My understanding is that this is too restrictive, and that the >> base conditions are different for different revisions of the ISA: >> >> MIPS I

[Qemu-devel] qemu/hw sun4m.c

CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 18:34:23 Modified files: hw : sun4m.c Log message: Fix SS-2 boot mode CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemu&r1=1.75&r2=1.76

[Qemu-devel] qemu/pc-bios README openbios-sparc32

CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 18:45:56 Modified files: pc-bios: README openbios-sparc32 Log message: Update Sparc32 OpenBIOS image to SVN revision 183. Changes: r182: Add handlers for timer interrupts

Re: [Qemu-devel] MIPS COP1X (and related) instructions

Richard Sandiford wrote: > Thiemo Seufer <[EMAIL PROTECTED]> writes: > > Richard Sandiford wrote: > >> All MIPS COP1X instructions currently require the FPU to be in 64-bit > >> mode. My understanding is that this is too restrictive, and that the > >> base conditions are different for different re

[Qemu-devel] qemu/hw slavio_intctl.c slavio_timer.c sun4m.c

CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 20:09:57 Modified files: hw : slavio_intctl.c slavio_timer.c sun4m.c Log message: Fix CPU timer interrupts CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_intctl

Re: [Qemu-devel] MIPS COP1X (and related) instructions

Thiemo Seufer <[EMAIL PROTECTED]> writes: > Richard Sandiford wrote: >> What should the patch do instead for MIPS IV? Enable them unconditionally? > > Given that it is currently theoretical, as the only MIPS IV CPU > supported is the VR5432: Add a comment to the MIPS IV test that it is > too restr